KR101409629B1 - Interlock of read column select and read databus precharge control signals - Google Patents

Abstract

The present invention relates to column selection and data bus precharge signal interlock schemes for DRAM memories. A signal interlock system includes a column select signal for coupling data to a common read data bus and a column read enable associated with each bank of DRAM memory for generating a read data bus precharge disable signal to disable the read data bus precharge device Circuit. Each column read enable circuit includes a pulse generator circuit having a tunable component that generates a read data bus precharge disable pulse and at least one column select signal pulse during a read operation. The pulse generator circuit ensures that the column select pulse is always nested for the read data bus precharge disable pulse. Thus, there is no overlap between the active column select device and the active read data bus precharge device.

Description

INTERLOCK OF READ COLUMN SELECT AND READ DATABUS PRECHARGE CONTROL SIGNALS}

The present invention relates generally to semiconductor memories. More particularly, the present invention relates to column selection and precharge signal timing control.

DRAM memory is widely used in computer systems due to its high density and high performance compared to other commercially available memories. The DRAM memory can be used in other applications where large amounts of data storage, such as hard disk drive buffers, for example, can be accessed quickly. Although SRAM performance is comparable, SRAM memory cells are relatively large, resulting in a chip with a low storage density per unit area. On the other hand, the flash memory has a storage density higher than the storage density of the DRAM, but the read and write (program) performance is comparatively poor. Thus, the DRAM provides an optimal balance between storage density and performance.

Those skilled in the art should be very familiar with the DRAM architecture. The DRAM memory array consists of columns of word lines and rows of bit lines arranged in a generally folded bit line structure, with the memory cells located at the intersections of the word lines and the bit lines. The bit line sense amplifier detects the charge stored in the memory cell storage capacitor via the bit line, and the column selection device transmits the sensed data to the data bus.

DRAM used in a computer system is a merchandise device that is connected to a printed circuit board (PCB), but the DRAM may be embedded as a macro within the system, such as a microcontroller or an ASIC (Application Specific Integrated Circuit). In either implementation, the DRAM core remains the same as a number of peripheral circuits required to enable its operation.

1 is a block diagram showing an example of a general DRAM macro or an embedded DRAM. The DRAM macro 10 includes four memory blocks 12, a local block input / output (I / O) circuit 14, and a macro I / O and control circuit 16. Each memory block 12 is divided into four banks 18, each of which can be further subdivided into quarters. Within each block 12 are a plurality of local read data bus (DB) pairs (DB / DB *) 22 shared between the four banks 18 of the block 12. Only one local read DB pair 22 is shown in FIG.

In the present illustrative example, data is provided from one of the four blocks 12 in a read operation. Within the selected block 12, data is asserted from one of the four blocks 18 to the local read DB pairs. The data on the local read DB pairs 22 is provided to the local block I / O circuit 14 and is eventually passed to the system via the macro I / O and control circuitry 16. The write operation proceeds in the opposite direction through the local write DB pairs, not shown in FIG.

2 is a detailed block diagram of one memory block 12 shown in FIG. From this point forward, the signal names ending in [n] indicate the bank to which the signal is associated, where n can be any integer. Each bank, bank [0] to bank [3] includes two arrays (or blocks) of bit sense amplifier / column selectors (BLSA and Y-sel devices) 30 and a WL driver 32). ≪ / RTI > The bit lines in the memory array may be folded and interleaved. Each bank 18 has at least two Y-driver circuits 36 where each Y-driver circuit 36 can provide any predetermined number of Y-select signals Y-sel, The number depends on the architecture of the DRAM. It should be understood by those skilled in the art that each bank may include additional circuitry not shown in FIG. It is located in the local block I / O circuit 14 at the bottom of FIG. 2, and the circuit includes a read DB pre-charge circuit. A read DB pair 22 is coupled to the BLSA and Y-sel device 30 of all four banks 18 and the local block I / O circuit 14. [

Each Y-driver circuit 36 receives a different decoded column address signal and a global enable signal (Y-selr) such as AYi [0] for bank [0]. AYj [0] is received by another Y-driver circuit 36 of bank [0]. AYi [0] / AYj [0] may include column address information and bank address information. Those skilled in the art will appreciate that multiple column address signals may be used to activate one or more of the plurality of column select devices in circuit block 30. [ Y-selr_gen is a global general enable signal which is a command decoded from the read command. More specifically, this signal may be a pulse with a rising period of time relative to the global bit line sense timing signal. Figure 3 shows how this signal is applied. Local block I / O circuit 14 includes a read data precharge and equalization device controlled by signal Rdb_pre. Note that although any precharge scheme may be used, for purposes of the following example, the read DB pair 22 is precharged to VDD.

Fig. 3 is a schematic circuit diagram showing one Y-driver circuit 36. Fig. More specifically, FIG. 3 shows a Y-driver circuit 36 that receives a column address signal AYi [0]. This is a simple circuit consisting of a NAND gate 40 and three serially connected inverters 42, 44 and 46. NAND gate 40 receives at least one column addressing signal AYi [0] and a global enable signal Yselr_gen. The resulting signal Y-sel drives the gate of one or more column selectors. AYi [0] includes the bank address and the column address information, so that only the column selectors in the selected bank will be activated. AYi [0] is generated by the appropriate column decoding logic, which is well known to one of ordinary skill in the art. The driver circuit 36 will be enabled only when Yselr-gen is at the active level (i.e., logic 1 or logic high for this example). The Y-driver circuit 36 may include a plurality of similar circuits each receiving a Yselr-gen and a different column addressing signal.

4 is a schematic circuit diagram showing one possible configuration of the read DB pair precharge circuit and the BLSA and Y-sel device 30. As discussed above, the read DB pair precharge circuitry is typically implemented in the local block I / O circuitry 14. The BLSA and Y-sel device 30 circuits illustrate complementary bit lines (BL0 and BL0 *) and are sensed and amplified by a well known cross-coupled bit line sense amplifier 50, To the buses DB and DB *. The illustrated bit line sense amplifier 50 is well known in the art and is activated by the signals sp * and sn through the enable transistors 52 and 54. The read select circuit includes n-channel serial pull-down transistors (also called column selectors) 56, 58, 60 and 62 for the bit line pair (BL0 and BL0 *). For purposes of illustration only, additional read select circuitry having n-channel serial pull-down transistors 57, 59, 61 and 63 for bit line pair BLn and BLn * are shown. Transistors 56 and 58 are connected in series between DB * and supply voltage VSS while transistors 60 and 62 are connected in series between DB and VSS. The gate terminals of the transistors 56 and 60 receive the column select signal Y-sel0 and the gate terminals of the transistors 58 and 62 are respectively connected to BL0 and BL0 *. This circuit is well known in the art and is known as a high speed circuit for placing read data on a VDD precharged data bus line. The data bus precharge circuit 64, which is a pair of p-channel transistors 66 and 68, connects VDD to DB and DB * in response to the precharge control signal Rdb_pre inverted by the inverter 70.

Preferably, the DRAM shown in Figs. 2 to 4 can be operated at high speed, which means that, for example, successive read operations from any bank can be executed at high speed. In the DRAMs of Figures 2 to 4, interleaved bank operations are possible, allowing one bank 18 to place data in the read data bus pair 22 in one clock cycle, while the other bank 18 Thereby allowing data to be placed in the same pair of read data buses 22 in the next clock cycle. The read data bus pair 22 must be precharged before the next bank can place data on itself. The pre-charge pulse must be released after the end of the Y-sel pulse of the first bank and before the Y-sel pulse of the next bank. If Y-sel is asserted in any other bank while the timing is off and overlap occurs, i.e., when the precharge pulse is activated, the data of the read data bus pair 22 may be lost and a direct current (Vdd) A pass can occur. When the DRAM is designed to operate at low frequencies, a large timing margin can be provided between the signal edges to avoid any overlap. However, if a high clock rate is required (i.e. 1 GHz), the relative timing of the column selection and data bus precharge signals must be accurate since there is not enough time to provide a large timing margin.

A discussion of the inaccurate timing of prior art DRAMs follows with reference to the circuit shown in FIG. 2 and the sequence diagram of FIG. The sequence diagram is similar to that of FIG. 1 except that the clock signal CLK, the enable signal Yselr_gen, the precharge control signal Rdb_pre, the column select signals Y-sel [3] and Y-sel [ / DB *). ≪ / RTI > A column select signal Y-sel [3] is generated for the bank [3] while Y-sel [0] is generated for the bank [0]. This sequence diagram shows a sequence in which data is first read from the bank [3] and then from the bank [0] in the interleave operation. In this scheme, Yselr_gen and Rdb_pre are generated in synchronization with the system clock (CLK).

Prior to the read operation, Rdb_pre is in a high logic state to turn on precharge transistors 66 and 68 in FIG. Therefore, DB and DB * start in a high logic state. The read operation in bank [3] starts at transition arrow 80, where Yselr_gen is pulsed high as Rdb_pre falls to low in response to the rising edge of CLK. Rdb_pre falling to low releases DB and DB * from precharge devices 66 and 68. In response to decoded addresses such as Yselrgen and AYi [3], Y-sel [3] is driven high at transition arrow 82 to couple data to DB and DB * via the column selection device. In this particular example, DB falls to a low logic state while DB * remains in a high logic state. Thereafter, Yselr_gen is driven low at transition arrow 84 to disable all column selectors. Since DB and DB * must be precharged, Rdb_pre is driven high to pre-charge DB and DB * to a high logic state, as shown in transition arrow 86. [

Thus, the first read access cycle is completed, and the second read access cycle begins. Yselrgen is again driven high to drive Y-sel [0] at transition arrow 88 and Rdb_pre is driven low to disable precharge transistors 66 and 68. The timing of the falling and rising edges of the precharge signal Rdb_pre becomes constant with respect to the CLK signal. However, due to the physical distance of the Y-driver circuit 36 from the source of Yselr_gen to the bank [0], there is a propagation delay of Yselr_gen rising and falling edges. Due to the later arrival of Yselrgen, the generation of Y-sel [0] for Rdb_pre is delayed as shown by transition arrow 90, causing Y-sel [0] to remain high after Rdb_pre rises. Thus, the data on DB and DB * may be lost because the column select device is turned on during time t1 while the pre-charge transistors 66 and 68 are turned on.

In addition, since DB and DB * hold only data from bank [0] for a short duration, the data bus sense amplifiers (not shown) are enabled to sense data if some data is continuously applied to DB and DB * You may not have enough time. Also, turning on both of the precharge transistors 66 and 68 at the same time as the column select transistors (i.e., transistors 56 and 60) are turned on creates an undesired DC path between VDD and VSS.

As discussed above, due to the inherent geometry of the memory banks (banks [0] through [3]) of the DRAM, the timing of the Y-sel signal depends on the timing of the precharge signal Rdb_pre . ≪ / RTI > More timing margins may be provided to account for signal propagation delays to ensure data integrity, but this results in a slower execution device.

Therefore, it is desirable to provide a DRAM circuit and system for reliably reading data from different banks at high speed.

It is an object of the present invention to eliminate or alleviate at least one drawback of the prior art. In particular, it is an object of the present invention to provide circuits and systems for generating non-overlapping read data bus precharge and column select enable signals.

According to a first aspect, the present invention provides a dynamic random access memory having first and second banks, each bank having a sense amplifier sensing data and a column selection device coupling the sensed data to a read data bus . The memory includes a first timing interlock circuit, a second timing interlock circuit, a precharge logic circuit and a read data bus precharge circuit. The first timing interlock circuit corresponds to the first bank. The first timing interlock circuit provides a first data bus pre-charge disable pulse having a first column select enable pulse and a second duration having a first duration, wherein the first column select enable pulse 1 < / RTI > data bus precharge disabling pulse. And the second timing interlock circuit corresponds to the second bank. The second timing interlock circuit provides a second column select enable pulse having a first duration and a second data bus precharge disabling pulse having a second duration, 2 < / RTI > data bus precharge disabling pulse. The precharge logic circuit, in turn, responds to the first data bus precharge disabling pulse in response to a first master data bus precharge disabling pulse and a second data bus precharge disabling pulse, Thereby generating an Able pulse. The first master pre-charge disable pulse and the first column select enable pulse have substantially the same timing relationship as the timing relationship of the second master pre-charge disable pulse and the second column select enable pulse. The read data bus precharge circuit precharges the read data bus. The first master data bus precharge disable pulse and the second master data bus precharge disable pulse respectively disable the read data bus precharge circuit for a first duration.

According to one embodiment of this aspect, the second timing interlock circuit and the first timing interlock circuit have the same circuit configuration. The first timing interlock circuit may include an activation delay circuit, a pre-charge disable pulse generator circuit, and a column select pulse generator circuit. The activation delay circuit receives and delays the access signal. The activation delay circuit provides a first time delayed access signal. The precharge disable pulse generator circuit generates a first data bus precharge disable pulse having a second duration in response to the first time delayed access signal. The precharge disable pulse generator circuit provides a second time delayed access signal in response to the first time delayed access signal. The column select pulse generator circuit generates a first column select enable pulse having a first duration in response to the second time delayed access signal. The first duration is less than the second duration.

In this embodiment, the activation delay circuit includes a programmable delay circuit that receives and delays the access signal, wherein the delay circuit provides a first time delayed access signal. The precharge disable pulse generator circuit includes a first logic gate having a first input terminal receiving a first time delayed access signal and a second input terminal coupled to a series chain of inversion elements, The serial chain receives the first time delayed access signal. In this embodiment, one of the inversion elements includes a programmable delay circuit, the other of the inversion elements having a first input terminal coupled to the programmable delay circuit and a second input terminal coupled to the synchronization control signal, And a logic gate.

In another aspect of this embodiment, the column select pulse generator includes a first logic gate having a first input terminal for receiving the second time delayed access signal and a second input terminal coupled to a series chain of inverting elements, The serial chain of inverting elements receives the second time delayed access signal. In this embodiment, one of the inversion elements includes a programmable delay circuit and the other of the inversion elements has a first input terminal coupled to the programmable delay circuit and a second input terminal coupled to the synchronization control signal. 2 logic gates.

In a second aspect, the present invention provides a timing interlock circuit for controlling read access to one bank of memory. The timing interlock circuit includes an activation delay circuit, a pre-charge disable pulse generator circuit, and a read column select pulse generator circuit. The activation delay circuit receives and delays the read access signal and provides a read access signal that is delayed by the first time. A precharge disable pulse generator circuit generates a data bus precharge disable pulse having a first duration in response to the first time delayed read access signal. In addition, the pre-charge disable pulse generator circuit provides a read access signal that is delayed in response to the first time delayed read access signal. A read column select pulse generator circuit generates a column select enable pulse having a second duration in response to the second time delayed read access signal. The second duration is less than the first duration, and the column select enable pulse is nested with respect to the data bus precharge disable pulse.

Embodiments of this aspect are as follows. The activation delay circuit includes a programmable delay circuit for receiving and delaying the read access signal, wherein the programmable delay circuit provides the first time delayed read access signal. The precharge disable pulse generator circuit includes a first logic gate having a first input terminal receiving the read access signal of the first time delay and a second input terminal coupled to a first series chain of inverting elements. The first serial chain of inverting elements receives the first time delayed read access signal. Wherein one of the inverting elements of the serial chain of the inverting element comprises a programmable delay circuit and the other of the inverting elements of the serial chain of the inverting element comprises a first input terminal coupled to the programmable delay circuit, And a second logic gate having a second input terminal coupled thereto. The read column select pulse generator includes a third logic gate having a first input terminal receiving the second time delayed read access signal and a second input terminal coupled to a second series chain of invert elements. The second serial chain of inverting elements receives the second time delayed read access signal. One of the inverting elements of the second serial chain of the inverting element comprises a third programmable delay circuit and the other of the inverting elements of the second serial chain of the inverting element is coupled to the third programmable delay circuit 1 input terminal and a second input terminal coupled to the synchronization control signal. In yet another embodiment, the second programmable delay circuit and the third programmable delay circuit are similarly configured.

In a third aspect, the invention provides a method of transferring data from a bit line of at least one memory bank to a read data bus. The method comprises the steps of: a) generating a local data bus pre-charge disable pulse and a local column select enable pulse; b) generating a master data bus precharge pulse; c) disabling the read data bus precharge circuit; And d) driving a column selection device of at least one memory bank. The local data bus precharge disabling pulse has a first duration and is generated in response to the bank access signal. The local column select enable pulse has a second duration and is generated in response to the bank access signal. Local data bus precharge disable pulse, local column select enable pulse and bank access signal all correspond to at least one memory bank. The master data bus precharge pulse is generated in response to the local data bus precharge disabling pulse. The read data bus precharge circuit is disabled for a first duration in response to the master data bus precharge pulse. The column selection device of at least one memory bank is driven in response to a local column select enable pulse while the read data bus precharge circuit is disabled.

An embodiment of this aspect is as follows. Wherein step a) comprises the steps of: i) generating a second local data bus precharge disabling pulse having the first duration, and ii) generating a second local column select enable pulse having the second duration . Wherein the second local data bus precharge disabling pulse is generated in response to a second bank access signal, wherein the second local data bus precharge disabling pulse and the second bank access signal correspond to a second memory bank do. The second local column select enable pulse is generated in response to the second bank access signal, wherein the second bank access signal is provided at a predetermined time after the bank access signal. Step b) further comprises generating a second master disable precharge pulse in response to the second local data bus precharge disabling pulse after the master data bus precharge pulse is generated. Wherein step c) includes disabling the read data bus precharge circuit for the first duration in response to the second master data bus precharge pulse, step d) And driving the column select device of the second memory bank in response to the second local column select enable pulse while being disabled in response to the second master data bus precharge pulse.

In another embodiment of this aspect, the local column select enable pulse is nested with respect to the local data bus precharge disabling pulse, and the timing relationship between the master data bus precharge pulse and the column select enable pulse is the second The timing relationship between the master data bus precharge pulse and the second column selection enable pulse is the same. Also, a first duration of the local data bus precharge disable pulse and a second duration of the local column select enable pulse may be applied to the synchronous control signal when the memory operates at a frequency below the maximum operating frequency of the memory Lt; / RTI >

Other aspects and features of the present invention will become apparent to those skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying drawings.

According to the present invention, it is possible to obtain a circuit and a system for generating a read data bus precharge and a column select enable signal which do not overlap.

Embodiments of the present invention will now be described by way of example only with reference to the accompanying drawings.
1 is a block diagram of a conventional embedded DRAM.
2 is a block diagram showing details of one memory block of the embedded DRAM of FIG.
3 is a circuit diagram of the column driver circuit.
4 is a circuit diagram showing a read data bus precharge circuit, a bit line sense amplifier, and a column select device.
5 is a sequence diagram illustrating an interleaved read operation for the memory block shown in FIG.
6 is a block diagram of a DRAM having column select and precharge signal interlock circuits in accordance with an embodiment of the present invention.
7 is a circuit diagram of the timing interlock circuit of Fig. 6 according to an embodiment of the present invention.
8 is a circuit diagram of the precharge logic circuit of FIG. 6 according to an embodiment of the present invention.
9 is a circuit diagram of the column driver circuit of FIG.
10 is a sequence diagram illustrating the operation of a column selection and precharge signal interlock scheme according to an embodiment of the present invention.

A column selection and precharge signal interlock scheme for a DRAM memory is disclosed. The signal interlock system includes a column selection signal for coupling data to a common read bus and a column associated with each bank of DRAM memory for generating a read data bus precharge disable signal for disabling the read data bus precharge device, And a read enable circuit. Each column read enable circuit includes a pulse generator circuit having a tunable part for generating at least one column select signal pulse and a read data bus precharge disable pulse. The circuitry within the pulse generator circuit ensures that the column select pulse is always nested with respect to the read data bus precharge disable pulse. Thus, there is no overlap between the active column select device and the active read data bus precharge circuit.

In fact, the pre-charge disable signal pulse and the column select signal pulse generated from any one timing circuit are not interlocked with each other, and have a relative timing to be mixed for all the banks in the block. More specifically, the data bus precharge device is disabled and an appropriate column select signal is activated based on the signal generated from each bank. Thereafter, the column select signal is disabled and the data bus precharge device is enabled. Thus, the column read enable circuit for each bank can disable the data bus precharge device. In this way, it is certain that timing conflicts can not occur during the interleaved read operation.

6 is a block diagram illustrating a DRAM memory block having a column select and read data bus precharge signal interlock scheme in accordance with an embodiment of the present invention. The signal name and label to which the "[n]" label is attached refers to the particular bank to which it is associated, where n may be an integer including zero. The DRAM memory block 100 includes banks [0], banks [1], and banks [1], each having a memory cell array 102, an array of word line drivers 104 and a BLSA and Y- 2] and the bank [3]. All BLSA and Y-sel device blocks 106 are connected to a pair of local read data buses 108. These circuits may be the same as those shown in the prior art DRAM memory block 12 of FIG. Preferably, a read DB circuit block 110 comprising a DB pre-charge device similar to that shown in Figure 4 is located in the middle of the banks (in this example between bank [1] and bank [2]). Those skilled in the art will appreciate that other circuits that may be required to enable proper operation of the DRAM memory block are not shown to simplify the illustration.

There is a column read enable circuit 112 associated with each bank, where each column read enable circuit generates a column select signal Y_sel and a read DB precharge disable signal. The read DB precharge disable signal for bank [0] is shown as rdbeq_gen [0]. Y_sel may be at least one signal line for activating at least one column selection device. Precharge logic circuit 114 generates a master precharge disable signal Rdb_pre in response to a data bus precharge disabling pulse from any bank in the block (such as rdbeq_gen [0] in this example).

The circuit block of one column read enable circuit 112 associated with bank [0] is shown in FIG. 6 and the description below of this particular column read enable circuit 112 is for another column read enable 0.0 > 112 < / RTI > The column read enable circuit 112 includes a column select driver circuit (Y-driver circuit) 116, a timing interlock circuit 118, and a sense amplifier enable circuit 120.

Each Y-driver circuit 116 of bank [0] receives a column address signal AYi [0] or AYj [0] to select at least one circuit 116. [ The selected Y-driver circuit (s) 116 are enabled in response to the column enable signal Ydrv_en [0] for bank [0] to generate one or more column select signals Y-sel. The circuit details of one Y-driver circuit 116 are shown in Fig.

The timing interlock circuit 118 generates the enable signal Ydrv_en [0] and the precharge enable signal rdbeq_gen [0] as pulsed signals in response to the two signals saen [0] and rd_bk_ltch [0] I have a responsibility. The bit line sense amplifier enable signal saen [0] is generated in response to the bank activation signal Bk_act [0]. Although not shown in FIG. 6, the bit line sense amplifiers in the BLSA and Y-sel device blocks 106 are enabled by a version of the saen [0] signal in any read, write or refresh operation. In the illustrated memory architecture, write and refresh operations do not require the use of a local read DB pair and a read column selector. Therefore, an additional read signal rd_bk_ltch [0] is used to limit the operation of the timing interlock circuit 118 only to the read operation. 0] and rdbeq_gen [0] when the synchronizing signal bk_clk [0] is received by the timing interlock circuit 118 and the memory operates at a frequency lower than the maximum operating frequency, according to an embodiment of the present invention. Thereby expanding the pulse width of the signal. A further discussion of this feature will be described below.

The timing interlock circuit 118 is associated with another bank that generates the same signal when a read operation for that bank is performed. The timing interlock circuit 118 includes a tunable asynchronous delay circuit for generating Ydrv_en [0] and rdbeq_gen [0]. Specifically, the Ydrv_en [0] pulse is nested within the rdbeq_gen [0] pulse, and the timing between the two is fixed or interlocked with each other by a circuit in the timing interlock circuit 118. The duration of the pulse is variable, as shown in the circuit diagram of the timing interlock circuit 118 of FIG.

Sense amplifier enable circuit 120 includes circuitry for generating at least one signal used to enable a bit line sense amplifier related to activation of a word line. Those skilled in the art will appreciate that the bit line sense amplifier is activated at a predetermined time after the word line is activated such that the voltage on the bit line can be reliably sensed. The sense amplifier enable circuit 120 includes a sense amplifier enable signal saen routed to another circuit (not shown) for generating the bit line sense amplifier control signals sp * and sn shown in Figure 4, . In this example, the signal saen is also used by the timing interlock circuit 118 to generate Ydrv_en [0] and rdbeq_gen [0]. The generation of the saen signal starts from the rising edge of the bank activation signal, i.e. Bk_act [0] for bank [0], indicating that the operation in the selected bank is taking place. The bank enable signal Bk_act [0] is driven into an active logic state for any bank activity including read, write or refresh operations.

 Note that there is no global block enable signal received or generated by any of the column read enable circuits 112. It is apparent from Fig. 6 that each column read enable circuit 112 receives its own set of signals AYi, Bk_act, rd_bk_ltch Ayj and bk_clk and generates its own control signals Ydrv_en and rdbeq_gen.

The precharge logic circuit 114 receives four local precharge disabling signals rdbeq_gen [0] to rdbeq_gen [3] from each bank (bank [0] to bank [3] And a circuit for generating the charge signal Rdb_pre. The master read data bus precharge signal Rdb_pre is pulsed inactive by any one of the four rdbeq_gen [0] to rdbeq_gen [3] pulsed signals. The Rdb_pre signal is used to turn on and off the precharge transistors 66 and 68 of FIG. In the present embodiment, only the master pre-charge disable signal Rdb_pre is generated by the pre-charge logic circuit 114. [ This is due to the read data bus pre-charge scheme used in FIG. However, those skilled in the art will appreciate that a sophisticated read data bus precharge scheme requiring more control signals may be generated from the precharge logic circuit 114 in response to any of the rdbeq_gen [n] pulses.

Using the example in which a read access from the bank [0] is performed, in a typical operation, the timing interlock circuit 118 first sets rdbeq_gen [0] inactive to disable the read DB precharge devices 66 and 68 And will be driven to a logic state. Then, after a predetermined delay, yselr_gen [0] is pulsed into an active logic state for a duration to activate the appropriate Y-Sel signal. Rdbeq_gen [0] is then driven into an active logic state to enable the DB precharge device in preparation for subsequent reads from different banks in the same block. Thus, the timing interlock circuit 118 of each bank provides a read DB precharge device for a duration sufficient to ensure that data can be fully transferred from the bit line sense amplifier to the read DB via the active n- Can be disabled. One of ordinary skill in the art will understand that the active or inactive logic state of the signal depends on the circuit being used.

7 is a circuit diagram of the timing interlock circuit 118 shown in Fig. 6 according to an embodiment of the present invention. This circuit is responsible for generating the column select and DB precharge disable signals in response to a read operation for each bank. The circuit includes an activation delay circuit 200, a data bus pre-charge disable pulse generator circuit 202 and a read column select pulse generator circuit 204. The activation delay circuit 200 delays the propagation of the read signal (s) rising edge at the start of the read operation in each bank. In response to this rising edge, precharge pulse generator circuit 202 generates a low logic state rdbeq_gen [n] pulse and read column select pulse generator circuit 204 generates a high logic state Ydrv_en [n] pulse in parallel do. Referring to FIG. 4, note that the read select DB precharge device is turned off for the duration of the low rdbeq_gen [n] pulse while the column select device is turned on for the duration of the high Ydrv_en [n] pulse. The high logic state Ydrv_en [n] rising and falling edges occur within the falling and rising edges of the rdbeq_gen [n] pulse (i.e., Ydrv_en [n] is nested for rdbeq_gen [n]).

The activation delay circuit 200 includes a NAND gate 206 receiving signals saen [n] and rd_bk_ltch [n], a first delay circuit 206 for delaying the output of the NAND gate 206 and providing an inverted output (208). In this embodiment, saen and rd_bk_ltch are used, but any suitable signal (s) effective for use as the timing reference start time in memory may be used to generate the trigger of the signal pulse. The data bus precharge disabling pulse generator circuit 202 includes an inverter 210 connected in series between the output of the first delay circuit 208 and one input of the NAND gate 220, an inverter 212, A delay circuit 214, an inverter 216, and a NAND gate 218. The second input of the NAND gate 220 is coupled to the output of the first delay circuit 208. The output of NAND gate 220 is connected to inverters 222 and 224, where inverter 224 provides signal rdbeq_gen [n]. The second input of the NAND gate 218 receives the clock signal Bk_clk [n].

The read column select pulse generator circuit 204 includes a third delay circuit 226, an inverter 228 and a NAND gate 230 connected in series between the output of the inverter 212 and one input of the NAND gate 232, . The second input of NAND gate 232 is coupled to the output of inverter 212 and the second input of NAND gate 230 receives signal bk_clk [n]. The output of NAND gate 232 is coupled to inverter 234 providing signal Ydrv_en [n].

The configuration of the gates used for pulse generation in circuits 202 and 204 is well known and those skilled in the art will appreciate that the duration of the generated pulse depends on the asynchronous propagation delay of the rising edge through the cascaded circuit elements. In the read column select pulse generator circuit 204, the delay is determined by the circuit elements 226, 228 and 230. The delay circuits 208, 214, and 226 are programmable, which means that the magnitude of the delay can be customized and set by the blowing fuse and / or programming registers. Those skilled in the art should be familiar with a number of different ways in which a programmable delay circuit can be implemented.

Each delay circuit is specially tuned (or programmed) to establish a timing relationship between the various signals, particularly those signals used during a read operation for the bank. The first delay circuit 208 provides a bit line sense amplifier setup time so that the bit line sense amplifier has enough time to latch the bit line data before being coupled to the read DB pair. Alternatively, if the delay is too short, there will be insufficient differences generated on the complementary bit line, and incorrect data may appear in the read DB pair. The second delay circuit 214 sets the primary duration of the low rdbeq_gen [n] pulse and the third delay circuit 226 sets the primary duration of the high Ydrv_en [n] pulse. In one embodiment, both delay circuits 214 and 216 may be independently tuned. As a result, the width of the rdbeq_gen [n] pre-charge disable pulse can be longer than the falling edge of Ydrv_en [n]. The actual limit of tunability is determined by the amount of time available in the cycle, the minimum required width of Ydrv_en [n], and the minimum required time to guarantee proper precharging of the read data bus pair for subsequent cycles. In an alternate embodiment, both delay circuits 214 and 226 have substantially the same delay. In such an embodiment, the delay circuit 226 is unnecessary and the output of the delay circuit 214 can be coupled to the input of the inverter 228. [ Inverters 210 and 212 ensure that the rising edge of the high Ydrv_en [n] pulse occurs after the falling edge of the low rdbeq_gen [n] pulse and that the low rdbeq_gen [n] pulse is lengthened accordingly.

An inherent feature of circuits 202 and 204 is the inclusion of a synchronization signal bk_clk [n] for gating the delayed rising edge provided by activation delay circuit 200. In this embodiment, the signal bk_clk [n] is used as the secondary control of the rising edge of rdbeq_gen [n] and the falling edge of Ydrv_en [n]. Preferably, the falling edge of rdbeq_gen [n] and the rising edge of Ydrv_en result in a signal generated from the second rising clock edge in a read cycle for a particular bank. In the present example, this signal may be the sense amplifier enable signal saen. The signal bk_clk [n] preferably rises in response to the third rising clock edge in the read cycle for that bank and remains in a high logic state for two clock cycles. The effects of the blk_clk signal on the data bus precharge disable pulse generator circuit 202 and the read column select pulse generator circuit 204 are as follows.

NAND gate 218 generates a low logic state when both inputs thereof are in a high logic state. Therefore, if only one of the inputs is high logic, the output remains high logic until the other input rises to a high logic state. Thus, the duration of the pulse at the output of NAND gate 220 is determined by the delay through inverters 210, 212, 216 and second delay circuit 214, when bk_clk [n] is first raised. On the other hand, if the rising edge generated by the activation delay circuit 200 first reaches the NAND gate 218, the duration of the pulse at the output of the NAND gate 220 will rise to a logic high with bk_clk [n] , That is, when bk_clk [n] rises after the third rising clock edge in the read cycle. Note that the same effect applies to the outputs of the NAND gate 230 and the NAND gate 232.

At high speed operation, i. E. At fast clock CLK, bk_clk [n] rises to a high logic state to enable NAND gates 218 and 230 first. The pulse durations of rdbeq_gen [n] and Ydrv_en [n] are then determined by the second delay circuit 214 and the third delay circuit 226, respectively. The rising edge output of the activation delay circuit 200 is delayed regardless of the clock CLK speed and in the low clock CLK operation, the rising edge output from the delay circuit 200 is input to the NAND gates 218 and 230 at bk_clk [n] And then rise to a high logic state. This allows for greater flexibility at test and at speed binning without the need for a large number of delay elements.

The sequence of rising and falling edges of rdbeq_gen [n] and Ydrv_en [n] is as follows. The precharge pulse generator circuit 202 drives rdbeqgen [n] to a low logic state to cause the read DB precharge device to be disabled, and then the read column select pulse generator circuit 204 sets Ydrv_en [n] And is driven in a high logic state. This sequence is determined by the delay through inverters 210 and 212 and ensures that the data from the bit line sense amplifier is transferred to the read DB pair after the read DB precharge device is turned off. After Ydrv_en [n] remains in the high logic state for a suitable amount of time (high pulse width is set by the read column select pulse generator circuit 204), Ydrv_en [n] is driven to a low logic state, The device is not selected, and the read DB pair is separated from the bit line sense amplifier. Thereafter, rdbeq-gen [n] is driven to a high logic state to enable the read-out DB pre-charge device, and prepare a read-out DB pair for a read operation from another bank.

8 is a circuit diagram of the data bus pre-charge logic circuit 114. In Fig. This circuit generates a master precharge disabling Rdb_pre pulse in response to any of the local data bus precharge disabling signals rdbeq_gen [0], rdbeq_gen [1], rdbeq_gen [2] and rdbeq_gen [3] . The precharge logic circuit 114 includes NAND gates 300 and 302, a NOR gate 304, and two serially connected inverters 306 and 308. NAND gate 300 receives signals rdbeq-gen [0] and rdbeqgen [1], while NAND gate 302 receives signals rdbeq_gen [2] and rdbeqgen [3]. The outputs of the NAND gates 300 and 302 are provided to two inputs of a NOR gate 304. The output of NOR gate 304 is then provided to the input of inverter 306 having an output coupled to the input of inverter 308. [ The output of the inverter 308 drives the master precharge disable signal Rdb_pre. This circuit also allows devices to propagate at a lower rate so that the falling edge of rdbeq_gen [n] propagates at high speed to produce a row Rdb_pre while the rising edge of rdbeq_gen [n] propagates at a slower rate to delay the rising edge of Rdb_pre By scaling in a series of logic gates, it may serve as a secondary delay to extend the duration of the rdbeq_gen [n] pulse.

The operation of the precharge logic circuit 114 will be described below with reference to the circuit of FIG. In this embodiment, when there is no read operation performed in any bank of the block, all four local data bus precharge disable signals remain in a high logic state and keep the signal Rdb_pre in a high logic state. This in turn keeps the read-out DB pre-charging device of Fig. 4 in a turned-on state. In a read operation for a bank, one of the local data bus precharge disable signals is pulsed into a low logic state for a duration. This causes the signal Rdb_pre to be pulsed correspondingly in a low logic state. The circuit configuration of the pre-charge logic circuit 114 is an example of a logic circuit for achieving this desired result. Those skilled in the art will appreciate that a variety of circuit configurations are possible that perform the same logical function.

9 is a circuit diagram of one Y-driver circuit in Y-driver circuit block 116 associated with bank [0]. This circuit is the same as the Y-driver circuit 36 in Fig. The Y-driver circuit 116 includes a NAND gate 400 and inverters 402, 404 and 406 connected in series. NAND gate 400 receives column address signal AYi [0] and enable signal Ydrv_en [0] via inverters 402, 404 and 406 and generates a corresponding Y-sel pulse. This Y-sel pulse is provided to a column selection device such as transistors 56 and 60 of FIG. Those skilled in the art will appreciate that there may be multiple Y-driver circuits within the Y-driver circuit block 116 that receive different column address signals, respectively, but all receive Ydrv_en [0] signals.

10 is a sequence diagram illustrating the operation of a column selection and precharge signal interlock scheme according to an embodiment of the present invention. The sequence diagram will be described with reference to Figs. 4 and 6 to 9. Fig. This sequence diagram shows the interleaved bank read operation from the bank [3] first to the bank [0] thereafter in the same block. The following signal traces: a clock CLK, a clocked enable signal bk_clk, a word line WL, a sense amplifier enable signal saen, a column enable signal Ydrv_en, a column select signal Y-sel, a read DB v precharge disable signal rdbeq_gen, The master precharge disable signal Rdb_pre is shown in FIG. Except for signal Rdb_pre, all identified signals associated with bank [3] are denoted by bank identifier [3], while signals identified by bank [0] are denoted by bank identifier [0].

It is assumed that all the banks of banks [0] to [3] of the block start in an idle state meaning that there is no read access to any bank of the block. In particular, since there is no access to bank [3] and bank [0] at the beginning of the sequence diagram, signals rdbeq_gen [3] and rdbeq_gen [0] remain in a high logic state, To maintain the read DB pair in the precharged state via the transistors 66 and 68 of FIG. The read cycle for bank [3] starts at the first rising clock edge (C1) at which the read command is decoded by the memory. This may include row address decoding to activate word line WL [0] in transition arrow 500. [ By activating WL [3], a voltage difference will occur in the pre-charged bit line when the memory cells connected to WL [3] are coupled to the bit line. The bit line sense amplifier is then enabled by saen [3], which is enabled from the second rising edge of CLK in transition arrow 502 (in response to bank enable signal Bk_act [3]). The saen [3] signal is delayed from Bk_act [3] to ensure that there is sufficient delay between the wordline rise and bitline sense amplifiers enabled to guarantee the proper bitline difference before bitline sense occurs .

When saen [3] rises to a high logic state and rd_bk_ltch [3] is in a high logic state to designate a read operation for bank [3], the activation delay circuit 200 of Figure 7 generates a rising edge do. This rising edge propagates through read column select pulse generator circuit 204 and data bus precharge disable pulse generator circuit 202 of FIG. As shown by transition arrow 504, rdbeq_gen [3] falls to a low logic state after a delay time of t1 for the falling edge of gate 206 in Fig. This causes rdb_pre to fall and release the read data bus precharge device of FIG. The falling edge of rdbeq_gen [3] causes Ydrv_en [3] to rise to a high logic state after a delay time of t2, thereby increasing the selected Y-sel [3] in turn. The clocked enable signal bl_clk [3] rises from the third rising edge of CLK to enable NAND gates 218 and 230 of FIG. In this example, bl_clk [3] effectively enables the output of the delay circuits 214 and 226. As a result, Ydrv_en [3] drops to the low logic state after the rising edge output from the activation delay circuit 200 propagates through the delay circuit 226 after the delay time t3. This ensures that the Y-sel [3] signal generated by the circuit of FIG. 9 is pulsed to a high logic state long enough to couple the bit line sense amplifier data to the read DB pair 22.

After a while, rdbeq_gen [3] rises to a high logic state after a delay time of t4 to precharge the read DB pair 22 via the Rdb_pre signal. The delay between the selected Y-sel [3] signal fall and Rdb_pre rise ensures that the column select device is turned on without the read DB precharge device being turned on at the same time. This terminates the active read data bus portion of the read cycle from bank [3], and the read DB pair is precharged to the preparation of the bank [0] read cycle, which began earlier on the second rising edge of CLK. The read cycle for bank [0] proceeds in the same manner as described above for bank [3], and more importantly, the same timing relationship is maintained between Rdb_pre and Y-sel [0]. Note that the Y-sel [n] pulse has a duration substantially equal to the Ydrv_en [n] pulse, but is delayed for Ydrv_en [n] due to the number of logic gates connected in series in the Y-driver circuit of FIG. Similarly, the Rdb_pre pulse is delayed for the corresponding rdbeq_gen [n] due to the number of logic gates connected in series in the precharge logic circuit of Fig.

As can be seen in Fig. 10, only signals Ydrv_en [3] and Ydrv_en [0] are pulsed in a high logic state while Rdb_pre is pulsed in a low logic state. Thus, there is never a time when the read DB pre-charge device is turned on while the column select device is turned on. Thus, a fast interleaved read operation can be reliably performed without a timing conflict.

Timing delays t1, t2, t3, and t4 are further discussed below with respect to timing interlock circuit 118 of FIG. 7, where n = 0 and associated with the falling edge output of NAND gate 206. Time t1 is the sum of the delay through the first delay circuit 208 and the gate delay through the logic elements 220, 222 and 224. Time t2 is the sum of the delay through the first delay circuit 208 and the gate delay through the logic elements 210, 212, 232 and 234. The falling edge of Ydrv_en [3] and the rising edge of Rdb_pre are set by the latter of the rising edge of the bk_clk [3] signal and the falling edge of the NAND gate 206 output through the delay circuits 214 and 226, do.

In an embodiment of the invention, the signal bk_clk [3] is not used and the NAND gates 218 and 230 function as simple inverters. In this embodiment, time t3 is the sum of the delays through delay circuit 208, logic elements 210, 212, 228, 230, 232, 234 and delay circuit 226. [ Time t4 is the sum of the delays through delay circuit 208, logic elements 210, 212, 216, 218, 220, 222, 224 and delay circuit 214.

In another embodiment of the present invention, the signal bk_clk [3] is used as shown in Figure 7, and when the clock frequency is lower, the falling output of the NAND gate 206 is such that bk_clk [3] And propagate through inverters 216 and 218 before rising at the rising edge. In this case, the duration of Ydrv_en [3] and rdbeq_gen [3] may be extended. More specifically, time t3 is delayed through the delay circuit 208, the logic elements 210, 212, 228, 230, 232, 234 and the delay circuit 226, the output rise of the + logic element 228, -clk [3] is the sum of the time differences between rising. Correspondingly time t4 corresponds to the delay through the delay circuit 208, the logic elements 210, 212, 216, 218, 220, 222 and 224 and the delay circuit 214, the output rise of the + logic element 216 and bk -clk [3] is the sum of the time differences between rising. However, regardless of the magnitude at which the pulse extends, the timing relationship between the falling edge of Ydrv_en [3] and rdbeq_gen [3] is maintained.

As discussed above, the delay circuit of Fig. 7 is programmable. Adjusting the delay of the first delay circuit 208 shifts the Ydrv_en [3] and rdbeq_gen [3] pulses by the same magnitude to the output of the NAND gate 206. The second and third delay circuits 214 and 226 preferably have the same delay and the adjustment of the delay affects the duration of the Ydrv_en [3] and rdbeq_gen [3] pulses.

Thus, according to one embodiment of the present invention, the column selection and data bus precharge signal interlock schemes currently shown are suitable for high speed DRAM. The read DB precharge device for the block is disabled and re-enabled at the same relative timing for the column select signal in any bank in which the read access operation is to be performed. In other words, each bank can independently control the timing of the reading DB pre-charging device of the block.

Although embodiments of the present invention are described for DRAM memory, embodiments of the column selection and precharge signal interlock schemes are suitable for any type of memory that is partitioned into memory portions that share a common read data bus. Of course, those skilled in the art will understand that the presently described embodiments are configured to accommodate DRAM specific circuits, such as bit line sense amplifier circuits. The presently-shown embodiments of the present invention may be adapted to alternate memories such as SRAM or non-volatile memory.

The above-described embodiments of the present invention are by way of example only. Modifications, variations and modifications may be effected by those skilled in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.

100: DRAM memory block
102: memory cell array
104: Word line driver
106: Y-sel device block
108: Local read data bus pair
110: Read DB circuit block
112: column read enable circuit
114: pre-charge logic circuit

Claims (31)

1. A dynamic random access memory having first and second banks each having a sense amplifier for sensing data and a column selector for coupling sensed data to a read data bus,
A first timing interlock circuit corresponding to the first bank and providing a first data bus precharge disable pulse having a first column select enable pulse and a second duration having a first duration, A first column select enable pulse is generated after the first data bus precharge disuse pulse is started and occurs during the first data bus precharge disuse pulse;
A second timing interlock circuit corresponding to the second bank and providing a second data bus precharge disabling pulse having a second column select enable pulse and a second duration having a first duration, A select enable pulse is generated after the start of the second data bus precharge disable pulse and occurs during the second data bus precharge disable pulse;
In response to the first data bus precharge disabling pulse, a second master data bus precharge disabling pulse in response to the first master data bus precharge disabling pulse and the second data bus precharge disabling pulse Wherein the first master precharge disable pulse and the first column select enable pulse are substantially equal to the timing relationship of the second master precharge disable pulse and the second column select enable pulse, Have a timing relationship; And
Wherein the first master data bus pre-charge disable pulse and the second master data bus pre-charge disable pulse are respectively applied to the readout data bus precharge circuit for precharging the read data bus, A dynamic random access memory that disables the data bus precharge circuit. The dynamic random access memory according to claim 1, wherein the second timing interlock circuit and the first timing interlock circuit have the same circuit configuration. The circuit according to claim 2, wherein the first timing interlock circuit comprises:
An activation delay circuit for receiving and delaying the access signal and providing a first time delayed access signal,
Generating the first data bus precharge disabling pulse having the second duration in response to the first time delayed access signal and providing a second time delayed access signal in response to the first time delayed access signal Pre-charge disable pulse generator circuit, and
And a column select pulse generator circuit responsive to the second time delayed access signal to generate the first column select enable pulse having the first duration, the first duration being less than the second duration, Dynamic random access memory. 4. The dynamic random access memory of claim 3, wherein the activation delay circuit includes a programmable delay circuit that receives and delays the access signal, and wherein the delay circuit provides a first time delayed access signal. 4. The circuit of claim 3, wherein the pre-
A first input terminal receiving the first time delayed access signal and a second input terminal coupled to a serial chain of inverting elements, the serial chain of inverting elements receiving the first time delayed access signal, Dynamic random access memory. 6. The dynamic random access memory of claim 5, wherein one of the inverting elements comprises a programmable delay circuit. 7. The dynamic random access memory of claim 6, wherein the other of the inverting elements comprises a second logic gate having a first input terminal coupled to the programmable delay circuit and a second input terminal coupled to the synchronization control signal. The plasma display apparatus of claim 3,
And a first logic gate having a first input terminal receiving the second time delayed access signal and a second input terminal coupled to a serial chain of inverting elements, the serial chain of inverting elements being coupled to the second time delayed access A dynamic random access memory that receives signals. 9. The dynamic random access memory of claim 8, wherein one of the inverting elements comprises a programmable delay circuit. 10. The dynamic random access memory of claim 9, wherein the other of the inverting elements comprises a second logic gate having a first input terminal coupled to the programmable delay circuit and a second input terminal coupled to the synchronization control signal. A timing interlock circuit for controlling read access to one bank of memory,
An activation delay circuit for receiving and delaying a read access signal and providing a read access signal that is delayed by a first time;
Generating a data bus precharge disable pulse having a first duration in response to the first time delayed read access signal and generating a data bus precharge disable pulse in response to the first time delayed read access signal, A charge disable pulse generator circuit; And
And a read column selection pulse generator circuit responsive to the second time delayed read access signal to generate a column select enable pulse having a second duration, the second duration being less than the first duration, A column select enable pulse is generated after the data bus precharge disabling pulse is started and occurs during the data bus precharge disabling pulse. 12. The timing interlock circuit of claim 11, wherein the activation delay circuit includes a programmable delay circuit that receives and delays the read access signal, and wherein the programmable delay circuit provides the first time delayed read access signal. 12. The circuit of claim 11, wherein the pre-
And a first logic gate having a first input terminal receiving the first time delayed read access signal and a second input terminal coupled to a series chain of inversion elements, the series chain of inversion elements having a first time delay A timing interlock circuit for receiving a read access signal. 14. The timing interlock circuit of claim 13, wherein one of the inverting elements of the series chain of inverting elements comprises a programmable delay circuit. 15. The method of claim 14 wherein the other of the inversion elements of the series chain of inverting elements comprises a second logic gate having a first input terminal coupled to the programmable delay circuit and a second input terminal coupled to the synchronization control signal , Timing interlock circuit. 12. The apparatus of claim 11, wherein the read column selection pulse generator comprises:
And a first logic gate having a first input terminal receiving the second time delayed read access signal and a second input terminal coupled to a series chain of inversion elements, the series chain of inversion elements being coupled to the second time delayed A timing interlock circuit for receiving a read access signal. 17. The timing interlock circuit of claim 16, wherein one of the inversion elements of the series chain of inversion elements comprises a programmable delay circuit. 19. The programmable delay circuit of claim 17, wherein the other of the inversion elements of the series chain of inverting elements comprises a second logic gate having a first input terminal coupled to the programmable delay circuit and a second input terminal coupled to the synchronization control signal , Timing interlock circuit. The method of claim 11,
Wherein the precharge disable pulse generator circuit includes a first logic gate having a first input terminal receiving the first time delayed read access signal and a second input terminal coupled to a first series chain of inversion elements, A first serial chain of inverting elements receives the first time delayed read access signal,
The read column select pulse generator includes a second logic gate having a first input terminal receiving the second time delayed read access signal and a second input terminal coupled to a second series chain of inversion elements, Wherein the second serial chain of read access signals receives the second time delayed read access signal. 21. The semiconductor device according to claim 19, wherein the first series chain of inverting elements comprises:
A first programmable delay circuit, and
And a third logic gate having a first input terminal coupled to the first programmable delay circuit and a second input terminal coupled to the synchronization control signal. 21. The device of claim 20, wherein the second serial chain of inverting elements comprises:
A second programmable delay circuit, and
A fourth logic gate having a first input terminal coupled to the second programmable delay circuit and a second input terminal coupled to the synchronization control signal. 23. The timing interlock circuit of claim 21 wherein the first programmable delay circuit and the second programmable delay circuit are similarly configured. A method for transferring data from a bit line of at least two memory banks to a common read data bus,
a) generating a first local data bus pre-charge disable pulse having a first duration in response to a first bank access signal, generating a first local data bus pre-charge disable pulse having a first duration in response to the first bank access signal, Generating an enable pulse, wherein the first local data precharge disable pulse, the first local column select enable pulse, and the first bank access signal correspond to a first memory bank;
b) generate a second local data bus pre-charge disable pulse having said first duration in response to a second bank access signal for which said first bank access signal is received and received after one or more clock cycles, Generating a second local column select enable pulse having the second duration in response to a two-bank access signal, wherein the second local column select enable pulse, the second local column select enable pulse, A second bank access signal corresponding to a second memory bank;
c) generating a sequential master data bus precharge pulse corresponding to the first local data bus precharge disabling pulse and the second local data bus precharge disabling pulse;
d) disabling the read data bus precharge circuit during the first duration in response to each of the master data bus precharge pulse; And
e) driving the column select device of the first memory bank in response to the first local column select enable pulse while the read data bus precharge circuit is disabled, and wherein the read data bus precharge circuit is disabled And driving the column selection device of the second memory bank in response to the second local column selection enable pulse. 24. The method of claim 23, wherein the first local column select enable pulse is generated after the first local data bus precharge disabling pulse begins and occurs during the first local data bus precharge disabling pulse, Wherein the column select enable pulse is generated after the second local data bus precharge disabling pulse is started and occurs during the second local data bus precharge disabling pulse. A method for transferring data from a bit line of at least one memory bank to a read data bus,
a) generating a local data bus precharge disable pulse having a first duration in response to a bank access signal, and generating a local column select enable pulse having a second duration in response to the bank access signal, The local data bus precharge disabling pulse, the local column select enable pulse and the bank access signal corresponding to at least one memory bank;
b) generating a master data bus precharge pulse in response to the local data bus precharge disabling pulse;
c) disabling the read data bus precharge circuit during the first duration in response to the master data bus precharge pulse; And
d) driving the column selection device of the at least one memory bank in response to the local column select enable pulse while the read data bus precharge circuit is disabled. 26. The method of claim 25, wherein the local column select enable pulse is generated after the local data bus precharge disabling pulse is started and occurs during the local data bus precharge disabling pulse. 26. The method of claim 25, wherein step a)
I) generating a second local data bus precharge disable pulse having the first duration in response to a second bank access signal, the second local data bus precharge disable pulse having the second local data bus precharge disable pulse and the second bank access signal Corresponds to a second memory bank, and
Ii) generating a second local column select enable pulse having the second duration in response to the second bank access signal, wherein the second bank access signal comprises a predefined Wherein the data is transmitted in time. 29. The method of claim 27, wherein step b) comprises generating a second master disable precharge pulse in response to the second local data bus precharge disabling pulse after the master data bus precharge pulse is generated. Data transmission method. 29. The method of claim 28, wherein step c) includes disabling the read data bus precharge circuit for the first duration in response to the second master data bus precharge pulse, wherein step d) And driving the column select device of the second memory bank in response to the second local column select enable pulse while the bus precharge circuit is disabled in response to the second master data bus precharge pulse. Data transmission method. 29. The method of claim 28, wherein the timing relationship between the master data bus precharge pulse and the column selection enable pulse is the same as the timing relationship between the second master data bus precharge pulse and the second column selection enable pulse, Lt; / RTI > 26. The method of claim 25 wherein the first duration of the local data bus precharge disable pulse and the second duration of the local column select enable pulse are synchronized when the memory operates at a frequency below the maximum operating frequency of the memory. A method of transmitting data, the method being extendable by a control signal.

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