CN103123806B - The control circuit of the array selecting signal of DRAM and include its access memorizer - Google Patents
The control circuit of the array selecting signal of DRAM and include its access memorizer Download PDFInfo
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- CN103123806B CN103123806B CN201110369979.6A CN201110369979A CN103123806B CN 103123806 B CN103123806 B CN 103123806B CN 201110369979 A CN201110369979 A CN 201110369979A CN 103123806 B CN103123806 B CN 103123806B
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- selecting signal
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- dynamic random
- access memory
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Abstract
The invention belongs to dynamic random access memory technical field, relate to the control circuit of the array selecting signal of a kind of dynamic random access memory.Described control circuit includes array selecting signal generative circuit, also includes: redundancy unit corresponding with the memory element of described dynamic random access memory and redundant word line drive module;Wherein, when the amplification read-out voltage of described redundancy unit matches with preset voltage threshold, described array selecting signal generative circuit generates array selecting signal.This dynamic random access memory, it includes the read path of the memory element in storage array, storage array, it is characterised in that also include in described storage array that redundancy unit, described dynamic random access memory also include the control circuit of this array selecting signal.This dynamic random access memory, while ensureing to read reliability, improves read operation speed.
Description
Technical field
(Dynamic Random Access Memory, dynamic random is deposited to the invention belongs to DRAM
Access to memory) technical field, relate to the control circuit of the array selecting signal of DRAM, especially relate to
And the control circuit of a kind of array selecting signal including redundancy unit.
Background technology
DRAM has been widely used in the electronic products such as computer, its technology lead-time
Longer, relative maturity.But, owing to DRAM is the memorizer storing information based on electric charge,
Its read operation is relatively slow.Along with the requirement of the speed to DRAM is more and more higher, current master
Wanting means is to improve reading speed by the most scaled to DRAM (scaling down)
Degree.
Normally, DRAM includes that storage array and peripheral circuit (are used for realizing reading and writing and brush
The new control waiting operation), storage array is by multiple memory element form row in rows and columns equally
Row composition, each memory element is arranged at the infall between bit line and the wordline of corresponding coupling.
Specifically, memory element generally includes an access transistor T (having gate action) and is used for
The electric capacity C of storage electric charge.Peripheral circuit is according to external command, by the bit line chosen and word
Line biasing corresponding electric signal, to realize the operation of the memory element to the most a certain address.
Wherein, the peripheral circuit of DRAM include decoder (such as line decoder and column decoder),
Bit-line drive module, bit-line drive module, Logic control module and sense amplifier (such as spirit
Quick amplifier, SA), sense amplifier coupled on storage array, and it is for performing from/to quilt
Memory element reading/the write operation selected.The output of sense amplifier is also coupled to DRAM simultaneously
I/O buffer in.During read operation, whether sense amplifier starts working, it make
Can control signal control;When sense amplifier outputs it the I/O buffering coupleding to DRAM
In device, then controlled by corresponding array selecting signal YL.
Fig. 1 show the DRAM column selection of prior art and leads to control mode schematic diagram.At this example
In, sense amplifier is conventional SA (Sense Amplifier, sense amplifier), column selection
Signal YL is provided separately, and in order to be able to read correct information, YL is in the enable of sense amplifier
Control signal SA_en is activated after activating, and makes the output of sense amplifier coupled to DRAM's
In I/O buffer MA.DRAM column selection shown in Fig. 1 is led to control mode and is mainly had the disadvantage that
If YL activates too early, then the voltage on bit line may be made rapid by the bulky capacitor on IO line
Drag down, low to again being amplified by SA, cause read error.Therefore, in the prior art,
Generally use delay required under worst case, i.e. YL is later to be activated, but this brings extra
Read latency, have impact on reading rate.
In view of this, it is necessary to the row gated fashion for DRAM proposes a kind of novel control
Circuit is to produce array selecting signal, while ensureing the reading reliability of DRAM, to improve it
Read operation speed.
Summary of the invention
The technical problem to be solved in the present invention is, improves the read operation speed of DRAM.
It is an aspect of this invention to provide that provide the array selecting signal of a kind of dynamic random access memory
Control circuit, described control circuit includes array selecting signal generative circuit, it is characterised in that institute
State control circuit also to include: redundancy corresponding with the memory element of described dynamic random access memory
Unit and redundant word line drive module;
Wherein, match with preset voltage threshold when the read-out voltage that amplifies of described redundancy unit
Time, described array selecting signal generative circuit generates array selecting signal.
The preferred embodiment of the control circuit of sense amplifier is provided according to the present invention, wherein, described
Array selecting signal generative circuit also includes comparator, and described comparator is for relatively described redundancy unit
Amplify read-out voltage and described preset voltage threshold.
It is preferred that work as the amplification read-out voltage of described redundancy unit and described preset voltage threshold
When difference is less than the minimum sensitive volume of described comparator, the amplification read-out voltage of described redundancy unit
Match with described preset voltage threshold.
The another preferred embodiment of the control circuit of sense amplifier is provided according to the present invention, wherein,
Described control circuit also includes the voltage generation circuit for generating described preset voltage threshold.
It is preferred that described voltage generation circuit is for generating adjustable described preset voltage threshold
Value.
The further embodiment of the control circuit of sense amplifier is provided according to the present invention, wherein,
Described redundancy unit is storage " 0 " all the time or storage " 1 " all the time during read operation.
According to another aspect of the present invention, it is provided that a kind of dynamic random access memory, it includes depositing
The read path of the memory element in storage array, storage array, it is characterised in that described storage array
In also include that redundancy unit, described dynamic random access memory also include such as claim 1 to 10
According to any one of the control circuit of array selecting signal.
It is preferred that described memory element and described redundancy unit are in described dynamic random access memory
Storage array in prepare formation simultaneously.
The solution have the advantages that, by the control circuit at the array selecting signal of memory element
Increase redundancy unit, thus, it is matched with preset electricity by the read-out voltage that amplifies of redundancy unit
Pressure threshold value, controls the delay phase of array selecting signal and the peripheral circuit of the read path of memory element
Join.Therefore, on the one hand, the delay of control circuit can the prolonging of read path of effective tracking memory cell
Late, and the change of delay of the read path that technological fluctuation is caused can be followed the tracks of at any time;On the other hand,
Once the amplification read-out voltage of memory element reaches degree (certain the predetermined electricity that can be read correctly
Pressure, can be VDD or certain be slightly below the voltage Vini of VDD), row control can be immediately generated
Signal processed, to coupled to the output of sense amplifier in the I/O buffer MA of DRAM.From
And, while ensureing the reading reliability of DRAM, improve its read operation speed.
Accompanying drawing explanation
From combine accompanying drawing described further below, it will make above and other objects of the present invention and
Advantage is more fully apparent from, and wherein, same or analogous key element is adopted and is indicated by the same numeral.
Fig. 1 is that in prior art, control mode schematic diagram is led in DRAM column selection;
Fig. 2 is the control electricity of the array selecting signal of the DRAM according to one embodiment of the invention offer
The basic structure schematic diagram on road;
Fig. 3 is the yet another embodiment signal of the control circuit of the array selecting signal of DRAM shown in Fig. 2
Time diagram.
Detailed description of the invention
Be described below is that the multiple of the present invention may some in embodiments, it is desirable to provide to this
Bright basic understanding, it is no intended to confirm that the crucial of the present invention or conclusive key element or limit is wanted
The scope of protection.Easy to understand, according to technical scheme, in the reality not changing the present invention
Under matter spirit, one of ordinary skill in the art can propose other the realization side that can mutually replace
Formula.Therefore, detailed description below and accompanying drawing are only the examples to technical scheme
Property explanation, and be not to be construed as the whole of the present invention or be considered as the restriction to technical solution of the present invention
Or limit.
Fig. 2 is the control electricity of the array selecting signal of the DRAM according to one embodiment of the invention offer
The basic structure schematic diagram on road.As in figure 2 it is shown, the control circuit of this array selecting signal, described control
Circuit processed includes array selecting signal generative circuit, and wherein, described control circuit also includes dynamic with described
The corresponding redundancy unit of memory element 208 of state random access memory and redundant word line drive
Module 209;Wherein, as amplification read-out voltage and the preset voltage threshold Vref of described redundancy unit
When matching, described array selecting signal generative circuit generates array selecting signal.For example, it is assumed that redundancy
Unit 208 deposits 1.WL drives while activating memory element 202 and also activates redundancy unit 208.
The current potential of redundant bit line BLd raises, and the voltage difference of bit line pair exports after being amplified by SA207 and is added to
Comparator COM's 205 "-" end, comparator COM "+" end be connected to reference voltage Vref,
Thered is provided by reference voltage maker Vref_gen 206.The output signal of comparator 205 is YL,
Activate column select switch, the storage content of memory element 202 is exported I/O through BL and SA203
On line and I/O ' line, then amplify through main amplifier MA 204, finally export data.Here,
Physical memory location read path followed the tracks of by the present embodiment redundancy unit read path so that actual storage list
The SA output voltage of unit once reaches predetermined value Vref and (can be VDD, or certain can
Voltage Vini to be read correctly) after again through the process of a comparator, i.e. activate YL.Cause
And YL can be opened in time, while ensureing to read reliability, improve reading rate.Preferably,
SA 203 and SA 207 structure is identical, and starts simultaneously.Redundancy unit 208, redundancy function
Line is to BLd and BLd ', with physical memory location 202 and actual bit line BL and BL ', complete phase
With.
Preferably, this array selecting signal generative circuit also includes comparator COM205, described comparison
Device amplifies read-out voltage and described preset voltage threshold Vref for relatively described redundancy unit.
Specifically, comparator COM205 compares the amplification read-out voltage of redundancy unit 208 and preset electricity
Pressure threshold value Vref, as amplification read-out voltage and the preset voltage threshold Vref of described redundancy unit
When matching, as equal in both or difference is less than certain voltage difference scope, described array selecting signal
Generative circuit generates array selecting signal.Connect example, the voltage of the current potential bit line pair of redundancy unit 208
After difference is amplified by SA207, output is added to comparator COM's 205 "-" end, comparator COM's
"+" end is connected to reference voltage Vref, reference voltage maker Vref_gen 206 provide.Ratio
The relatively output signal of device 205 is YL, activates column select switch, by the storage of memory element 202
Content exports on I/O line and I/O ' line through BL and SA203, then through main amplifier MA 204
Amplify, finally export data.
It is highly preferred that work as the amplification read-out voltage of described redundancy unit and described preset voltage threshold
Difference less than the minimum sensitive volume of described comparator time, the amplification of described redundancy unit reads electricity
Pressure matches with described preset voltage threshold.Such as, (the deltV when Vref is VDD-deltV
It is the minimum sensitive volume of comparator COM 205, i.e. makes the phase inverter in comparator to occur
The minimum voltage amplitude of upset), once the voltage of BLd is amplified to VDD, comparator COM 205
Work, produces YL activation signal.Now the storage data of physical memory location 202 through BL and
After SA203 amplifies, through YL be output to I/O line to (I/O and I/O ') on.Total delay therein
Time: SA 207 amplifies the delay of the delay+comparator COM 205 of BLd to VDD.Because
Having the delay of comparator COM 205, now reading rate is the slowest.For another example, as Vref it is
During VDD-deltV-Vx, Vx is small voltage difference, and BLd can be made to reach VDD-Vx
Time begin to allow comparator work, the setting of Vx shall be such that SA is amplified to prolonging of VDD-Vx
Late plus the delay of comparator COM 205, BL voltage difference is amplified to VDD by exactly SA
Delay.Consider the delay of comparator the most in advance, so that the voltage of BL is once put
Big to VDD, YL can be activated and export data.And for example, if actual storage need not BL
Reach VDD to be transferred on IO line through YL and not have read error, then needed for can use
After bit line amplifies, voltage Vini replaces VDD, i.e. reference voltage to be set to Vbl-deltV, or
Vbl-deltV-Vx, then can activate YL when the voltage of BLd reaches Vbl or Vbl-Vx.
Preferably, the control circuit of this array selecting signal also includes for generating described preset voltage
The voltage generation circuit 206 of threshold value.Specifically, this voltage generation circuit 206 generates preset electricity
Pressure threshold value Vref, and provide it to this control circuit, for the amplification with described redundancy unit
Read-out voltage matches and compares, and when such a match occurs, described array selecting signal generative circuit generates row
Select signal.
It is highly preferred that this voltage generation circuit is for generating adjustable described preset voltage threshold
Value, such as Vdd-deltV or Vdd-deltV-x, wherein x is the most small.Here, deltV be SA (or
Person comparator COM) minimum sense voltage scope, such COM so that only to BLd
Voltage when reaching Vdd, YL just opens.For design DRAM, BL voltage not over
Vdd, so the BL that voltage is Vdd necessarily can correctly be read, so the most only needing to ensure
BL voltage is Vdd, but once YL opens, and BL voltage can reduce, and YL also can open?
As long as also meeting the sensitive volume of SA, it is possible to be amplified to VDD.But after just now opening,
The voltage of YL has arrived the degree that MA can read, it is not necessary to BL repeats and is exaggerated.Enter
The explanation of one step: Vref can be Vdd-deltV.Can be that Vdd-deltV-x, x are the most small,
To consider the delays in work of COM.Or to shift to an earlier date a bit, then to consider to reduce further Vref.
The size of Vref depends on electric capacity and the actual size of dummy BL electric capacity of IO line.
Fig. 3 is the yet another embodiment signal of the control circuit of the array selecting signal of DRAM shown in Fig. 2
Time diagram.In conjunction with Fig. 3, the operation principle that the present embodiment is expanded on further is as follows:
1) structure in Fig. 2 is combined, when the voltage difference of BL and BL ' reaches the amplitude that SA can work
Time, SA_en is effective, and SA 203 starts working, when the voltage on BL and BL ' once
When being amplified to VDD and 0V, YL immediately turns on, and outputs data to I/O line pair
On.(this figure correspond to situation during Vref=VDD-deltV-Vx)
2) as Vref=VDD-deltV, the unlatching of YL is late a period of time than in Fig. 3, this section
The time delay equal to comparator COM 205.
3) as Vref=Vini-deltV-Vx, wherein Vini is less than or equal to VDD, once BL
Being amplified to Vini (being also not up to VDD), YL is i.e. unlocked.
4) as Vref=Vini-deltV, wherein Vini is less than or equal to VDD, and once BL is put
Big to Vini (being also not up to VDD), in the delay through one section of comparator COM 205,
YL is i.e. unlocked.
Preferably, described redundancy unit 208 stores " 0 " during read operation all the time or deposits all the time
Storage " 1 ".
A kind of dynamic random access memory, it includes the storage list in storage array, storage array
The read path of unit, it is characterised in that also include redundancy unit in described storage array, described dynamically
Random access memory also includes the control circuit of the array selecting signal as described by previous embodiment.
The DRAM of this embodiment includes storage array, each memory element in storage array concrete
Version is not restrictive, and such as, it can be the memory element of 1T1C structure.Multiple
Memory element form arrangement in rows and columns, in this example, several memory element are in rows and columns
Form arrangement formed memory block (block), multiple pieces then arrangement formed storage array.At this
In embodiment, storage array also includes redundancy unit, as redundancy unit includes with memory element
Device cell, the two be identical unit and can prepare simultaneously and together arrangement formed storage battle array
Row.In a particular application, it is also possible to the memory element specifying certain string or certain a line is redundancy unit.
In the example shown in fig. 2, one of them memory element being only shown schematically in storage array
202 and this redundancy unit 208 corresponding to memory element 202, it should be noted that every
Individual redundancy unit is not required to and concrete each memory element one_to_one corresponding, and multiple memory element can
With corresponding to a redundancy unit.Memory element 202, the particular number of redundancy unit 208 are not
Restrictive, in other words, the memory capacity size of storage array is not restrictive;Meanwhile,
Storage array has been only shown schematically the corresponding bit line pair connecting or coupling of memory element 202
BL and BL ', wordline WL, redundant word line WLr that redundancy unit 208 is corresponding to be connected or couple,
Redundant bit line is to BLr and BLr '.
The DRAM of this embodiment similarly includes peripheral circuit, and peripheral circuit can be according to outside
Input is ordered, by the bit line chosen and wordline are biased corresponding electric signal, to realize wherein
The operation (write operation, read operation and refresh operation etc.) of the memory element of a certain address.At this
In bright, due to its purpose primarily to improve the speed of read operation, for making those skilled in the art
Understand the improvements of this invention, to corresponding to other operation, known to one of skill in the art
The parts of peripheral circuit or circuit module list the most one by one.Peripheral circuit at least includes reading
Amplifier 203, as a example by the read operation of memory element 202, its bit line voltage to BL and BL '
Difference signal can input to sense amplifier 203, be then passed through sense amplifier 203 export to
The I/O buffer of peripheral circuit.The storage electric charge of memory element 203 makes its bit line pair coupled
The amplitude (i.e. Δ V) that the voltage difference of BL and BL ' reaches to allow SA normally work needs certain
Time, namely there is delay, it is normally expressed as the bitline delays of memory element.In this enforcement
In example, sense amplifier 203 is in particular sense amplifier (Sense Amplifier, SA),
Whether SA starts working is controlled by its enable control signal.Preferably, SA is cross-couplings type
SA。
Example above primarily illustrates the control circuit of the array selecting signal of the present invention and includes this control
The DRAM of circuit processed.Although only some of them embodiments of the present invention being described, but
Those of ordinary skill in the art it is to be appreciated that the present invention can without departing from its spirit with in scope
Implement with other forms many.Therefore, the example shown and embodiment are considered schematic
And nonrestrictive, without departing from the present invention as defined in appended claims spirit and model
In the case of enclosing, the present invention may contain various amendments and replacement.
Claims (4)
1. a control circuit for the array selecting signal of dynamic random access memory, institute
State control circuit and include array selecting signal generative circuit, it is characterised in that described control electricity
Road also includes: redundancy list corresponding with the memory element of described dynamic random access memory
Unit and redundant word line drive module;
Wherein, when amplification read-out voltage and the preset voltage threshold phase of described redundancy unit
During coupling, described array selecting signal generative circuit generates array selecting signal;
Described array selecting signal generative circuit also includes comparator, described comparator for than
Amplification read-out voltage and the described preset voltage threshold of more described redundancy unit;
Wherein, when amplification read-out voltage and the described preset voltage threshold of described redundancy unit
When the difference of value is less than the minimum sensitive volume of described comparator, putting of described redundancy unit
Big read-out voltage matches with described preset voltage threshold;
Described control circuit also includes the voltage for generating described preset voltage threshold
Generative circuit;Described voltage generation circuit is for generating adjustable described preset voltage
Threshold value.
2. the array selecting signal of dynamic random access memory as claimed in claim 1
Control circuit, it is characterised in that described redundancy unit is deposited during read operation all the time
Storage " 0 " or all the time storage " 1 ".
3. a dynamic random access memory, it includes storage array, storage array
In the read path of memory element, it is characterised in that described storage array also includes superfluous
Remaining unit, described dynamic random access memory also includes as appointed in claim 1 to 2
The control circuit of one described array selecting signal.
4. dynamic random access memory as claimed in claim 3, it is characterised in that
Described memory element and described redundancy unit depositing in described dynamic random access memory
Storage array prepares formation simultaneously.
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Citations (3)
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US5596539A (en) * | 1995-12-28 | 1997-01-21 | Lsi Logic Corporation | Method and apparatus for a low power self-timed memory control system |
CN101523500A (en) * | 2006-10-25 | 2009-09-02 | 高通股份有限公司 | Memory device with configurable delay tracking |
CN101874271A (en) * | 2007-10-11 | 2010-10-27 | 莫塞德技术公司 | Interlock of read column select and read databus precharge control signals |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5596539A (en) * | 1995-12-28 | 1997-01-21 | Lsi Logic Corporation | Method and apparatus for a low power self-timed memory control system |
CN101523500A (en) * | 2006-10-25 | 2009-09-02 | 高通股份有限公司 | Memory device with configurable delay tracking |
CN101874271A (en) * | 2007-10-11 | 2010-10-27 | 莫塞德技术公司 | Interlock of read column select and read databus precharge control signals |
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