JPH11176155A - Dram-refreshing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a data transfer rate by performing control so that a refreshing operation is prohibited based on a signal for indicating whether a DRAM is being accessed or not. SOLUTION: An address in one sector and each sector are specified by an offset address and a pointer address, respectively, and the 7-bit row address out of 8-bit row address is accessed by data writing of one sector. Therefore, only the row address that cannot be accessed may be refreshed while data are being buffered to a DRAM. A write control circuit 4 outputs a write request to a DRAM 1 and also stops outputting it. A command from the CPU is controlled in sector units and the output/non-output of the write request are also made in sector units. With the B-side input of a sector 8, a request (refresh request) is outputted only in the case of an address that cannot be accessed when writing data to a DRAM from a second decoder 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (DRA).
M).

[0002]

2. Description of the Related Art Conventionally, this type of DRAM refresh circuit always refreshes all row addresses of a DRAM at regular intervals. Also, in order to reduce unnecessary refresh, a RAM for storing which address was accessed when the DRAM was accessed was prepared, and the next refresh was not performed for that address. Structure is Japanese Patent Laid-Open No. 60-322.
No. 00 publication.

A similar method is disclosed in Japanese Patent Laid-Open No. 59-12169.
Japanese Patent Application Laid-Open No. 63-191 proposes a refresh control method for omitting the next refresh operation when the address at the time of normal memory access matches the address to be refreshed next time.
Japanese Patent No. 397 discloses a means for storing address information corresponding to an address of a DRAM accessed in the past, a means for simultaneously erasing all address information stored in the storage means at predetermined time intervals, Means for determining whether or not the refresh address has already been accessed, and sending a refresh access signal when it is determined that the refresh address has not been accessed; and a DR based on the refresh access signal and a normal memory access signal.
An information processing device having an arbiter circuit for arbitrating the right to use AM has been proposed.

[0004]

However, the prior art has the following problems.

[0005] The first problem is that an address that is refreshed at a fixed cycle is not refreshed once for an accessed address. Therefore, an address is accessed immediately after a certain address is refreshed. If the address is not accessed, about 2
Because refresh will not be performed for the cycle,
This means that the refresh cycle of the DRAM may not be satisfied.

A second problem is that a storage means (RAM) for storing an accessed address is required, so that the scale of hardware is increased.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to improve the data transfer speed, reduce the power consumption, and reduce the DRA.
An object of the present invention is to provide a DRAM refresh circuit that reliably satisfies M refresh cycles and suppresses and reduces an increase in hardware scale.

[0008]

In order to achieve the above object, a DRAM refresh circuit according to the present invention is a refresh circuit for refreshing the stored contents of a DRAM at regular time intervals to determine whether or not the DRAM is being accessed. A means for controlling so as to inhibit the refresh operation based on the signal shown is provided. Hereinafter, the present invention will be described in accordance with preferred embodiments.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment, a DRAM refresh circuit according to the present invention includes one DRAM in a refresh cycle so that unnecessary refresh is not performed.
A decode circuit for decoding an address which is never accessed, a circuit for generating a timing at which a certain address is accessed in a refresh cycle, and outputting a signal requesting refresh to all necessary refresh addresses, Alternatively, there is provided a selecting means for selecting whether to output a refresh request only to an address which is never accessed in a refresh cycle.

More specifically, in a preferred embodiment of the DRAM refresh circuit of the present invention, a refresh address generation means and an address output of the refresh address generation means are input to the DRAM so as to satisfy a DRAM refresh cycle. A first decoder for outputting a refresh request, a second decoder for receiving an address output of the refresh address generation means as an input, and outputting a refresh request to refresh only a certain address, and a write control circuit. And selecting means for inputting a signal indicating a mode in which data is written to the DRAM from the memory as a selection signal, selecting one of the outputs of the first and second decoders, and outputting to the arbiter circuit as a refresh request. Including the DRAM write Sometimes, the second decoder is selected, a refresh request is output only to an address that is not accessed, and during a period in which writing to the DRAM is not performed, a refresh is performed for all row addresses based on the output of the first decoder. Perform the operation.

According to the embodiment of the present invention, unnecessary access to the DRAM bus is reduced, data transfer speed is improved, and power consumption is reduced.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a diagram showing a configuration of a DRAM refresh circuit according to one embodiment of the present invention. Referring to FIG. 1, in one embodiment of the present invention, a DRAM 1 to be refreshed, a counter 2, first and second decoders 3 and 9, a DRA write control circuit (write control) 4, and a DRAM A read control circuit (read control) 5, a bus arbiter (arbitration circuit) 6,
An address selector 7 and a selector 8 are provided.

The DRAM 1 is connected to an address selected and output from the address selector 7. The address selector 7 is connected to an address output from a circuit (counter 2) for generating a write address, a read address, and a refresh address for the DRAM 1, and selects an address of a block for which the bus arbiter 6 is permitted to use the bus.

The bus arbiter 6 receives a bus use request from each block, assigns a priority order, and assigns an address to the address selector 7.
Output the selection signal to

The counter 2 is a counter for counting refresh cycles, and outputs a refresh address to the address selector 7 and also outputs a count value to the first and second decoders 3 and 9.

The first decoder 3 outputs a refresh request to the DRAM 1 to the selector 8 so as to satisfy the refresh cycle of the DRAM 1, and the second decoder 9
A refresh request is output to the selector 8 so as to refresh only a certain address.

The selector 8 receives a signal RFSEL from the DRAM write control circuit 4 indicating whether the mode is a mode for writing input data to the DRAM 1, and receives the first decoder 3 and the second decoder 3.
The output of the decoder 9 is switched and output to the bus arbiter 6.

The bus arbiter 6 has a selector 8, a DRA
Outputs from the M write control circuit 4 and the DRAM read control circuit 5 are received, and these are prioritized.

The operation of one embodiment of the present invention will be described. Here, an example in which the present invention is applied to a case where a 1-M (mega) -bit DRAM is used as a CD-ROM controller will be described. The format of the CD-ROM is
One sector is 2352 bytes. Assuming that an address in one sector is designated by an offset address and each sector is designated by a pointer address, if an address configuration as shown in FIG. 3 is used, 7 bits out of an 8-bit row address can be written by one sector of data. Will be accessed. Then, while data is being buffered in the DRAM, only the row address that is not accessed needs to be refreshed.

Based on this idea, this embodiment will be described with reference to FIG. The write control circuit 4 includes a CPU (not shown)
And outputs a write request to the DRAM 1 and stops the output in accordance with the instruction from the CPU. Since instructions from the CPU are controlled on a sector-by-sector basis, the output and non-output of write requests are also on a sector-by-sector basis.

For a sector that outputs a write request, the RFSEL signal becomes "1", and the selector 8 which inputs the RFSEL signal as a selection control signal selects the B side. The input (B side) of the selector 8 outputs a request (refresh request) only when the address is not accessed by the second decoder 9 during DRAM writing.

On the other hand, when a sector in which writing to the DRAM 1 is not performed is input (that is, a period in which writing to the DRAM is not performed), the RFSEL signal becomes “0”, the selector 8 selects the A side, and Decoder 3
, A refresh operation is performed for all the row addresses.

FIG. 2 is a timing chart showing the above operation. Referring to FIG.
I is a synchronization pattern detection signal of the CD-ROM. D
When a write signal (DRAM WRITE) to the RAM is output, access is made by writing data from 00h to 49h (h indicates hexadecimal notation), so that refresh is performed on row addresses from 4Ah to FFh. .

On the other hand, a write signal (DR) to the DRAM
AMWRITE) is not output, RFSE
The L signal becomes “0”, and all row addresses 00h to FF are output.
h to perform a refresh operation.

Next, a second embodiment of the present invention will be described.

Here, a CD-ROM controller is used.
An example in which the present invention is applied to a case where a DRAM having a width of 1M bits and 16 bits is used will be described. The format of the CD-ROM is 2352 bytes and one sector. Assuming that an address in one sector is designated by an offset address and each sector is designated by a pointer address, an address configuration as shown in FIG. 6 is employed, so that all 11-bit row addresses are accessed by writing data in one sector. become. Then, the refresh operation is not required while data is buffered in the DRAM.

Based on this concept, a second embodiment of the present invention will be described with reference to FIG. Referring to FIG. 4, in the second embodiment of the present invention, instead of the decoder 9 and the selection circuit 8 of FIG. 1, the output of the decoder 3 for outputting a refresh request to the DRAM 1 so as to satisfy the refresh cycle of the DRAM 1 And an AND gate 8 to which an inverted value ￣ REFENB of the signal REFENB from the write control circuit 4 is input.

The write control circuit 4 includes a CPU (not shown).
And outputs a write request to the DRAM and stops the output in accordance with the instruction from the CPU. Since instructions from the CPU are controlled in sector units, the output and non-output of write requests are also in sector units. For the sector that outputs the write request, the REFENB signal becomes "1", the refresh request output from the AND gate 8 becomes "0", and the refresh stops. However, as mentioned earlier, DRAM
In the case of performing data output to, since all row addresses are accessed, there is no problem even if refreshing stops.

On the other hand, when a sector to which a write request is to be output is being input (time during which writing to the DRAM is not performed), the REFENB signal becomes "0" and the refresh operation is performed.

This situation is shown in the timing chart of FIG. In FIG. 5, SYNCI is a CD-ROM synchronization pattern detection signal. When the write signal to the DRAM is being output, the refresh stops and the DRA
Refresh is performed when M is not written.

[0032]

As described above, according to the present invention,
The following effects are obtained.

The first effect of the present invention is that the transfer speed is increased.

The reason is that, in the present invention, unnecessary refresh is reduced, so that the time available for data transfer on the data bus of the DRAM is increased.

A second effect of the present invention is that current consumption can be reduced.

The reason is that, in the present invention, unnecessary refresh is reduced, so that the charge and discharge of the refresh current and the control signal of the DRAM are reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first exemplary embodiment of the present invention.

FIG. 3 is a diagram for explaining the first embodiment of the present invention, and is a diagram showing an address configuration of a DRAM.

FIG. 4 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the second exemplary embodiment of the present invention.

FIG. 6 is a diagram for explaining a second embodiment of the present invention, and is a diagram showing an address configuration of a DRAM.

[Explanation of symbols]

 1 DRAM 2 Counter 7 Address Selector 3 Decoder 4 Write Control Circuit 5 Read Control Circuit 6 Bus Arbiter 8 Selector 9 Decoder

Claims (6)

[Claims] 1. A refresh circuit for refreshing storage contents of a dynamic random access memory (hereinafter referred to as "DRAM") at regular intervals.
A means for controlling a refresh operation to be inhibited based on a signal indicating whether or not access is being performed. 2. A refresh circuit for refreshing stored contents of a DRAM at predetermined time intervals, wherein a refresh request signal is issued to all necessary refresh addresses based on a signal indicating whether or not the DRAM is being accessed. A DRAM refresh circuit comprising means for selecting whether to output a refresh request or to output a refresh request only to an address which is never accessed in a refresh cycle. 3. A dynamic random access memory (“DRA”) having a refresh address generating means as an input and an address output of the refresh address generating means as an input.
M ”) to satisfy the refresh cycle
A first decoder that outputs a refresh request to the RAM, a second decoder that receives an address output of the refresh address generation unit as an input, and outputs a refresh request so as to refresh only a certain address. Selecting means for inputting a signal indicating a mode for writing data to the DRAM from a control circuit as a selection signal, selecting one of the outputs of the first and second decoders, and outputting the selected signal as a refresh request. In a write mode to the DRAM, the second decoder is selected, a refresh request is output only to an address that is not accessed, and during a period in which writing to the DRAM is not performed, the first decoder is selected.
A refresh operation for all row addresses based on the output of the decoder. 4. A dynamic random access memory ("DRA") having a refresh address generating means as an input and an address output of said refresh address generating means as an input.
M ”) to satisfy the refresh cycle
A decoder for outputting a refresh request to the RAM; a signal from the write control circuit indicating writing of data to the DRAM and an output of the decoder as inputs; and a signal indicating writing of data to the DRAM is inactive. Selecting means comprising a gate circuit for outputting a refresh request and controlling to stop the refresh operation of the DRAM when a signal indicating writing of data to the DRAM is active, the DRAM comprising: Refresh circuit. 5. An arbiter circuit which receives outputs of the write control circuit, the read control circuit, and the selecting means, and prioritizes them to arbitrate the right to use the DRAM; 5. An address selection circuit for selecting an address for which a bus use is permitted by the arbiter circuit, out of an address of the refresh address and an address of the refresh address generation means.
Or the DRAM refresh circuit according to 5. 6. The DR according to any one of claims 1 to 5,
CD-ROM controller provided with an AM refresh circuit.