JPH01316828A - Interruption circuit for microcomputer - Google Patents

Abstract

PURPOSE:To freely attach priority on interruption input by incorporating an interruption circuit in a microcomputer. CONSTITUTION:When the priority is set on a priority setting register 1, a first multiplexer 4 is controlled by the above priority, and an interruption request signal from an interruption factor is outputted to the prescribed bit of a flag register 5, then, an interruption flag is set, and a vector generation circuit 7 generates a prescribed interruption vector. Furthermore, a second multiplexer 6 changes the spatial arrangement of the flag register corresponding to a changed priority, which functions so as not to change a vector as a result.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in interrupt circuits for microcomputers.

(b) Conventional technology Micro combinators are equipped with a plurality of interrupt inputs for processing equipment troubles, urgent programs from peripheral devices, or randomly occurring interrupt factors. Standard microcomputers are equipped with trap interrupts, restart interrupts, and INTR interrupts.
These interrupts have fixed priorities, such as the highest priority for trap interrupts and the lowest priority for lNTR interrupts, and there is no provision available today that allows the user to change the priority of interrupts. .

(c) Problems to be Solved by the Invention In microcomputer systems in which the priority of interrupts is fixed, priorities are set for interrupts whether we like it or not. A problem arises in that an interrupt factor connected to a low interrupt input will not accept interrupts forever. Furthermore, depending on the system, stable priority relationships are often not maintained between interrupt sources, and it is necessary to constantly change priorities in order to improve system response. Fixed microcomputers were not always easy to use.

Therefore, there are microcomputers that intentionally do not give priority to interrupt input, but when using this in a system that requires priority,
This has the disadvantage that the processing time of the original program is shortened due to the processing of the program for scheduling the interrupt processing.

(d) Means for Solving the Problems By incorporating a simple and programmable interrupt circuit into a microcomputer, the present invention can be used as a microcomputer with no priority for interrupt input, or can be used as a microcomputer with no priority for interrupt input. The present invention provides a microcomputer which can also be used as a microcomputer whose input priority can be changed, and which can reduce the number of schedule programs for interrupt processing.

In order to solve this problem, the present invention provides a priority setting register (1) for setting the priority of each interrupt input, and a predetermined value of a flag register based on the data of the priority setting register (1) and the interrupt input. A first multiplexer (4) that sets flags on bits.
, a flag register (5), a vector generation circuit (7) that generates an interrupt vector, and a priority setting register (
a second multiplexer (6) that changes the spatial arrangement of the flag register (5) input to the vector generation circuit based on the difference between the priority set in (1) and its initial value;
).

(*> Effect) The present invention having the above configuration has a priority setting register (1
), this controls the first multiplexer (4), outputs the interrupt request signal from the interrupt source to a predetermined bit of the flag register (5), sets the interrupt flag, and transfers the vector The generation circuit (7) is configured to generate a predetermined interrupt vector, and the second multiplexer (6) changes the spatial arrangement of the flag registers according to the changed priority so that the vector does not change as a result. It acts on

(F) Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that (1) is the priority setting register, (2) is the initial value setting register, (3) is the comparator, (4) is the first multiplexer, (5) is the flag register, and (6) is the second multiplexer. , (7> is a vector generation circuit, (8) is a reset circuit, (9) is an interrupt enable flag signal, (10)
-(12) are interrupt inputs, and (13) is an internal data bus.

The priority setting register (1) uses 2 bits for each interrupt input in the embodiment illustrating 3 interrupt inputs. By the way, in order to extend the present invention and apply it to 8 interrupt inputs, for example, 3 interrupt inputs are required for each interrupt input.
Bits are required.

First, data is set in the priority setting register (1) via the internal data bus (13) using a well-known method. If it is immediately after the system is started, it is also set in the initial value register (2). Now interrupting human power (10)
The priority of 11H=3 is the highest, and the interrupt input (
12) is set to the lowest priority of 01H-1, the priority setting register (1)
is set to 111001-39H.

The multiplexer (4) that can be controlled by the data of the priority setting register (1) is an AND gate G, ~
Consisting of G,, inverters ■, ~■, and a matrix circuit, 1 is now input to one gate input of AND gates G1 to G and G according to the data of the priority setting register (1), and AND gates G4 and G , 0 is input to one input of .

For ease of understanding here, all interrupt inputs (10)
Assuming that the interrupt request signal is output at ~(12),
The outputs of AND gates G, ~G, and G are 1, and the outputs of AND gates G4 and G are 0. The outputs of these AND gates are connected to inverters ■1 to 1. An inverted output is generated and output to the next stage matrix circuit together with a non-inverted output.

As shown in the figure, this matrix circuit outputs O to inverter I when both two bits of the pair of priority setting registers are 1, outputs O to inverter I when they are 10, and outputs O to inverter ! when they are 01. , outputs O to . In this example, therefore all inverters I, ~1. O is output to all inverters I, ~
I outputs 1 to the flag register (5).

The flag register (5) includes three R8-flip-flops or clock R3-flip-flops FF, ~F
In this example, an example using an R8 flip-flop will be explained first. Now inverter I
, . . . , the Q outputs of all flip-flops in the flag register (5) are set to 1. When the interrupt permission flag signal (9) is output, the AND gates G, .about.G output 1 to the vector generation circuit (7) via the second multiplexer (6). This second multiplexer (6) will also be described later, but for ease of understanding, for now, the output of the AND gate G is connected to the C input of the vector generation circuit (7) as shown by the dotted line in the drawing. It is assumed that the outputs of , , and , are connected so that they can be output to the b input, and the output of , G, can be output to the C input.

Now, when all the AND gates G, ~G, output 1, the output of the inverter 11°, which receives the output 1 of the AND gate G, becomes 0, and therefore the AND gate G
1. The output of will be 0. Also, or gate ORI and OR
Yo outputs 1.

The outputs of the OR gates OR+ and OR, obtained in this way, V! , VI become the lower second and third bits of the vector address by well-known means, and it becomes possible to execute the interrupt processing routine written at that address. The vector generation circuit (7) also outputs the vector to the reset circuit (8), and resets the vector generation flag, here FF, at a predetermined timing.

When the flip-flop FF is reset and there is no new interrupt request signal at the interrupt input (10), the flip-flop FF and FF are reset at the interrupt input (11) and (12).
Since it remains set by the interrupt request signal of
, outputs 1. At this time, the inverter □ of the vector generation circuit (7). Since it still outputs O, this AND gate G8. The OR gate OR, to which the 0 output of and the O output of the AND gate G, is input, outputs 0. Note that since one output of the AND gate G is input to the OR gate OR, it outputs 1. That is, the vector generation circuit (7) outputs 1.0 as vector outputs V, , V, respectively. This is nothing but the vector of interrupt input (11).

Now, when the flag register (5) is constituted by a clock R8 flip-flop, the present invention is provided with yet another function. That is, the basic operation is the same as the one described above, so it will be omitted, but by setting the clock input C of the clock RS-flip-flop to O by the first interrupt request signal, the first interrupt input is transferred to the flag register ( 3) can be latched, so that interrupt requests can be processed in the order of interrupt causes without priority. Such functions are strongly required depending on the application.

With the above explanation, priority setting register (1)
It is understood that a vector of addresses in which processing routines for each interrupt factor are written is set in the . Therefore, it must be noted that simply changing the contents of the priority setting register (1) may cause the problem that the processing address for the interrupt factor will be changed.

However, the present invention can also meet the request to set the priority of the human interrupt (10) to the lowest immediately after the interrupt processing of the human interrupt (10) is executed, for example. explain.

An example will now be described in which the priority of the interrupt input (10) is set to the lowest and the priority of the interrupt input (11) is set to the highest immediately after the interrupt processing of the interrupt input (10) is completed.

A processor (not shown) receives an interrupt input (10
), the priority of interrupt input (10) is set to 0IH-1, the priority of interrupt input (11) is set to l0H-3, and the priority of interrupt input (12) is set to IIH-3. Data 011011-IB
It is programmed to output H to the internal data bus (13) and set it in the priority setting register (1>).

When the priority is changed as above, the flip-flop whose interrupt input (10) sets the flag is FF
, interrupt input (11) is FF, and interrupt input (1
2) The flip-flop that sets the flag is changed to FF.

Here, a comparator (3) that compares the data of the priority setting register (1) and the initial value setting register (2) connects the output of the AND gate G to the C input of the vector generation circuit based on the comparison result. In order to output the output of G to the C input and the output of G to the b input, that is, interrupt human power (10〉
The second multiplexer (6) is controlled to maintain the original connection relationship in which the interrupt flag of is connected to the C input of the vector generation circuit (7). As a result, a priority changing circuit in which the vectors do not change is achieved.

(G) As described in detail, the interrupt circuit of the present invention is simple, but it is also possible to set a priority for the interrupt input, eliminate the priority, or even change the priority. , it is possible to provide a highly versatile microcomputer.

[Brief explanation of the drawing]

The drawing is a circuit diagram showing an embodiment of the present invention. (1) is the priority setting register, (2) is the initial value setting register, (3) is the comparator, (4) is the first multiplexer, (5> is the flag register, (6) is the second multiplexer, ( 7) is a vector generation circuit, (8> is a reset circuit, (9) is an interrupt enable flag signal, (10) to (
12) is an interrupt input, and (13) is an internal data bus.

Claims (3)

[Claims] (1) A priority setting register, a multiplexer that sets a flag in a predetermined bit of a flag register based on the data of the priority setting register and an interrupt input, a flag register, and a vector that sets a flag based on the flag of the flag register. A microcomputer interrupt circuit consisting of a vector generation circuit that outputs. (2) The interrupt circuit for a microcomputer according to claim 1, wherein the flag register is constituted by a clock RS flip-flop. (3) The spatial arrangement of the flag register input to the vector generation circuit is changed based on the difference between the priority set in the priority setting register and its initial value. The microcomputer interrupt circuit described in .