JPS60254487A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a circuit which generates a control signal for low power consumption by generating and outputting the signal which sets an external semiconductor integrated circuit in power-down mode when this circuit executes a specific instruction. CONSTITUTION:An input terminal 1 to which the signal indicating the state of an interrupt enable flag IF is inputted is held at an ''L'' level when the IF is set. Further, there are an input terminal 4 for inputting the inversion signal of a masking interrupt request input INTR, an input terminal 3 for inputting a signal which is set to the ''L'' level when a halt instruction is executed to stop a microprocessor, etc., an input terminal 4 for a mode switching signal, an input terminal 5 for inputting a masking disabling request input NMI signal, an input terminal 6 for a reset signal, an output terminal 7 for a power-down signal, an input terminal for a clock phi, and an input terminal -8 for the inverted clock -phi of the clock phi. Consequently, the power-down signal is generated and outputted when the halt instruction is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit, particularly to an application circuit of a complementary MO3 integrated circuit (0MO3IC).

[Prior art]

Conventionally, for example, a microprocessor has a circuit configuration using a single conductivity type MO3I-transistor.
The reality is that there is no circuit whose purpose is to reduce power consumption.

In a semiconductor integrated circuit configured with such a single conductivity type MO3) transistor, if you want to reduce power consumption, use a complementary type MO3) transistor (0MO3IC).
However, in this case, it is necessary to separately create a signal for setting the semiconductor integrated circuit to a state with low power consumption, and to apply this signal to the semiconductor integrated circuit to control the circuit. Also, depending on the type of integrated circuit, it may not be possible to completely convert it to CMO3 due to the chip size, etc.
It may be necessary to configure one side with a 0MO3 IC and the remaining with a single conductivity type MOS transistor, and even in such a circuit, it is possible to reduce power consumption by the above method.

[Summary of the invention]

The present invention has been made in view of the above, and is designed to create and output a signal for controlling the switch means when an external semiconductor integrated circuit having a switch means capable of reducing power consumption is executing a specific command. By doing so, it is an object of the present invention to provide a semiconductor integrated circuit that can reduce the power consumption not only of a complete CMO3 integrated circuit but also of an incomplete CMO3 integrated circuit.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a semiconductor integrated circuit according to an embodiment of the present invention. In the figure, 1 is an input terminal to which a signal indicating the state of an interwoven enable flag (hereinafter referred to as TF) is input, and when IF is set, terminal 1 becomes "L" level. 2 is an input terminal to which an inverted signal of a maskable interrupt request input (hereinafter referred to as lNTR) is input, and 3 is a halt (hereinafter referred to as HALT) for stopping the microprocessor, etc.
An input terminal to which a signal that is set to "L" level when an instruction is executed is input; 4 is an input terminal to which a mode switching signal is input; 5 is an input terminal to which a non-maskable interrupt request input (hereinafter referred to as NMI) signal is input. 6 is an input terminal for recent signals, 7 is an output terminal for power down signals,
8 is an input terminal of the clock φ, and 2 is an input terminal of the inverted clock φ of the clock φ.

Further, 9 is a power down signal generation circuit that generates a power down (hereinafter referred to as PD) signal (first control signal), 10 is a power down release signal generation circuit that generates a signal (second control signal) for canceling PD, 11 12 is a launch circuit that holds the outputs of the signal generation circuits 9 and 10, and 13 is the output of the latch circuit 12 and the mode switching circuit 11. This is a NOR circuit that requires two people to output the output.

2(a) to (1 is the clock φ, the signal state of each part A to E in the power down signal generation circuit 9, and the output terminal +'
l) (,4 ni state,) Kay, a7. Kaya, Yasha. The first operation will be explained.

In the power-down signal generation circuit 9, the signal state of the input terminal 3 appears at point A, and when the HALT command is executed, it becomes the II L 11 level in positive synchronization with the inverted clock (Fig. 2 +81. b)). At point B,
The signal state of the input terminal 3 appears after passing through the transfer gate 14 and inverter 152, which are turned on when the clock φ is "H", and the transfer gate 1-16, which is turned on when the inverted clock is "H" (see FIG. 2). See C)
. At point 0, the output of the AND circuit 11, which takes the product of the inverted signal at point B and the inverted signal at point A, appears (see Figure 2 (d+)).
. At point D, transfer gate 18. Inverter 1
After passing through the 9° transfer gate 20, the signal from the AND circuit 17 appears, which passes through an inverter 21 and a transfer gate 22 in order to be synchronized with the clock φ at point E, and is then passed through an inverter 23 for waveform shaping. The launch circuit 1 passes through the inverter 24 for positive logic.
2 (see FIG. 2(e) Tf)).

The circuit 1o that generates the PD release signal has the following logic.

(IF) * (INTR) + (NMI) +
(RESET) +: logical sum *: logical product and normally, in the mode switching circuit 11, the input terminal
is set to "L" level, and the state of the output cuff is determined by the signal generating circuit 9.
Controlled by 10.

Further, the latch circuit 12 holds the output signals of the signal generation circuits 9 and 1o, and maintains the current state until it changes to the next state.

In addition, in the mode switching circuit 11, the input terminal 4 is set to “H”.
In this case, the output terminal 7 becomes "L level" regardless of other inputs, PD is no longer performed, and the function is the same as that of a conventional circuit that does not take power consumption into consideration.

In the device of this embodiment as described above, a power down signal can be generated and outputted during HALT execution, and this can be used as a control signal for reducing power consumption.

In the above embodiment, the logic for canceling the PD mode is input 1.
, 2, 5, 6. Although this was done using the signal state, similar effects can be obtained by setting with other control signals.

The present invention also provides a complete CMO3 integrated circuit, an incomplete CMO3 integrated circuit, and an incomplete CMO3 integrated circuit.
The present invention can be similarly applied to reducing power consumption in other semiconductor integrated circuits rather than integrated circuits. However, in this case, it is of course necessary that this semiconductor integrated circuit has an input terminal for a power down signal and a power down function.

〔Effect of the invention〕

As described above, according to the present invention, when the external semiconductor integrated circuit is executing a specific command, a signal for setting the circuit to power down mode is created and output, thereby reducing power consumption. This has the advantage of being able to provide a circuit that generates control signals for this purpose.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing a timing chart for explaining the operation of the above device. 9... Power down signal generation circuit (first control signal generation circuit), 10... Power down release signal generation circuit (second control signal generation circuit), 11... Mode switching circuit (enable signal generation circuit) , 12...Latch circuit (launch circuit main body). Agent Masuo Oiwa Figure 1 Figure 2 (9) Amendment to output procedure (voluntary) October 9, 1980 To the Commissioner of the Japan Patent Office 0-1 1. Indication of the case Japanese Patent Application No. 112489-1982 2. Name of the invention: Semiconductor integrated circuit 3, Representative Ministry of the person making the amendment, Hitoshi Katayama Section 5, Detailed explanation of the invention in the specification subject to amendment 6, Contents of the amendment (1) Specification, page 4, Nos. 3 to 5 "Full CMOS conversion must be configured..." in the line "Full CMOS conversion must be configured..."
The configuration must be such that it is impossible to convert into 8. (2) On page 4, lines 13-14, [Not only complete CMO3 integrated circuits, but also incomplete...]
"It's incomplete like integrated circuits..."that's all

Claims (1)

[Scope of Claims] (11) A semiconductor integrated circuit that generates a signal for controlling an external semiconductor integrated circuit having a switch means capable of reducing power consumption, wherein the external semiconductor integrated circuit generates a signal for controlling the switch means, a first control signal generation circuit that generates a first control signal for setting the switch means to a power consumption reduction mode when the above operation is executed; and a first control signal generation circuit that releases the power consumption reduction mode of the switch means when an external signal is applied. a second control signal generation circuit that generates a second control signal for controlling the semiconductor device; and a latch circuit that holds the first control signal or the second control signal and supplies it to the switch means. Integrated circuit. (2) The launch circuit includes a launch circuit body that holds and outputs the first control signal or the second control signal, and an enable signal generation circuit that generates an enable signal that allows output to the latch circuit body. The semiconductor integrated circuit according to claim 1, characterized in that: (3) the launch circuit main body has the output of the first control signal generation circuit at its set terminal and the output of the first control signal generation circuit at its reset terminal; When the output of the second control signal generation circuit is connected, the output of the first control signal generation circuit is “H”, it is “L”, and when the output of the second control signal generation circuit is “H”, it is “H”. The output of the latch circuit main body and the output of the enable signal generation circuit are input to a NOR gate, and the output of the NOR gate is the output of the launch circuit. (4) The first control signal generating circuit includes a transfer gate to which a signal corresponding to the specific command is input and a clock is input to the gate, and an output of the transfer gate. A connected inverter, a transfer gate whose input is the output of the inverter, and a clock having a phase opposite to the above clock is input to the acceptance gate, and an AND operation in which the output of the transfer gate and the re-inverted signal of the above-mentioned human-powered signal are two-man-powered. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit comprises a circuit and generates a one-shot pulse having a pulse width of one clock.