JPS61289716A - Input synchronizing circuit - Google Patents

Abstract

PURPOSE:To avoid malfunction in a control circuit by setting a logic threshold value of a NAND circuit or a NOR circuit inputting a true output or an invert ed output of an input circuit higher or lower than the intermediate value appearing at the true output or the inverted output and introducing the true output or the inverted output of an R-S.FF to a set/reset terminal of the input circuit. CONSTITUTION:Outputs of AND circuits 3,4 are introduced to an input of NOR circuits 5, 6 respectively. The logic threshold value of the NOR circuit 7 is set higher than the level of the intermediate point having the possibility appearing at the NOR circuit 5. The logic threshold value of a NOR circuit 8 is set lower than the intermediate point having the possibility appearing at the NOR circuit 6. As soon as the input signal A changes from '1' to '0', when the signal phi changes from '1' to '0', each output of the NOR circuits 8, 7 goes respectively to '0', '1'. Since the output is introduced to the NOR circuits 5, 6, the output of the NOR circuit 5 changes from the intermediate value to '0' and the output of the NOR circuit 6 changes from the intermediate value to '1'. Thus, no intermediate level is caused to the output of an input synchronizing circuit and the internal circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an input synchronization circuit I/C, and in particular, a method for synchronizing a signal input to a control circuit such as a microcomputer with a basic clock signal of the control circuit. related to the circuit that causes

[Conventional technology]

Conventionally, as an input circuit VC for this purpose, a circuit shown in FIG. 4 has been used. Prior to explaining the present invention, the circuit operation of the iEA diagram will be explained. The signal person is a signal processed by the control circuit, and the signal φ is a basic clock signal.

A signal person is introduced into the input of the inverter 101, and the output of the inverter 1020 is introduced into the AND circuit 103vc whose other input is the signal φ. The output of 102 is introduced into an AND circuit 104 whose other input is a signal φ. N to each output of AND circuits 103 and 104, respectively.
Each output of the OR circuit 105°106 is 106.105
and is input to the control circuit.

As shown in FIG. 5, when the signal φ becomes "1" while the signal A has a logic value of 1 (hereinafter referred to as "1"), the AND circuit 104
The output IC "1" appears, and the output of the NOR circuit 106 becomes a logical value O (hereinafter referred to as "0").
The output is "0".

The output of NOR circuit) 05 becomes "1". The signal φ is “0”
'', the outputs of the AND circuits 103 and 104 are both ``0'', and the outputs of the NO8 circuits 105 and 106 continue to be in the rlJ and rOJ states, respectively. When the signal φ becomes "l" while the signal input is "0", the output of the AND circuit 103 becomes "1" and the output of the NOR circuit 105 becomes "0". All power of AND circuit 104 i rOJ o and N
The output of the OR circuit 106 becomes "1". Signal φ is rOJ
When it comes to that.

AND circuit 103.10417) Common Pc rOJ for output
te, and r to each output of NOR circuits 105 and 106, respectively.
Continue the OJ, l'-IJ state.

The above-described operation is such that the signal is read into the free lag flop constituted by the NOR circuits 105 and 106 at the time when the signal φ becomes "1". That is, the signal person is synchronized with the signal φ.

[Problem that the invention seeks to solve]

However, if the logic circuit of FIG. 4 is realized by combining transistors, a logic threshold value of each logic element (inverter, AND circuit, NOR circuit) &C occurs, and there is a problem caused by this logic threshold value. Taking an inverter as an example, the logic threshold referred to here means that if a signal with a value greater than this threshold is input, the output IC1rOJ will be output, and if a signal less than the value is input during this time,
The output is a value at which "1" appears, and when a logic threshold signal is input, a value intermediate between the output vcldrlJ and "O" appears.

When the signal A changes from "1" to "0" and the signal φ changes from "1" to "0" at the same time as shown in FIG. 6, the output of the AND circuit 103 rises to the logic threshold of the NOR circuit 105. However, after that, it may become rOJ. In this case, the output of the NOR circuit 105, which has been rotating from "1" to "0", remains at the aforementioned intermediate point. The NoRl circuit 106 which receives the output of the NOR circuit 105 has an intermediate point from "0" to "1". The output of the NOR circuit 105 is NOR
If the output of the NoRl circuit 106 becomes the logic threshold of the NOR circuit 105.

The outputs of the two NoRl circuits 105 and 106 both continue to output the midpoint. This always occurs when the logic circuit of FIG. 4 is realized using transistors in the combination of the signal person and the signal φ shown in the taG diagram. When the output of 105 and 106 that remains at this intermediate point is introduced into the control circuit, one circuit of the control circuit determines it to be "0" and another circuit determines it to be "1", causing the control circuit to malfunction.

As described above, the conventional input synchronization circuit has a drawback that a signal at an intermediate point appears in the output signal due to a combination of timing changes of an input signal and a signal that synchronizes the input signal.

[Means for solving problems]

In view of this, an object of the present invention is to provide an input synchronization circuit that does not generate an intermediate level no matter how an input signal and a signal for synchronizing the input signal change.

The input synchronization circuit of the present invention has a set/reset function, and has an input circuit that reads an input signal as a synchronization signal, and two NANDA circuits that use the true output and anti-output of this input circuit as inputs.
An ND circuit consisting of an R-S flip-flop consisting of two NOR circuits, and an NA whose input is the true output of the input circuit.
The logic threshold of an NDAND circuit or OR circuit is higher (or lower) than the intermediate value that appears at the true output, and the logic threshold of a NAND circuit or a NOR circuit that uses the inverse output as input is lower than the intermediate value that appears at the inverse output. (higher) and set the true output and negative output of the R-8 flip-flop to the input circuit.
This is the introduction to Reset Kameko.

[Metal practice]

Invention? : Detailed explanation based on the example of the ritual. FIG. 1 shows an embodiment of the present invention. An input signal is introduced into the input of inverter l, and the output of inverter l is connected to inverter 2 and -
The total input signal φ is input to an AND circuit 3. The output of inverter 2 is A with −1 input as signal φ
It is introduced into the input of the ND circuit 4. The outputs of AND circuits 3.4 are introduced into the inputs of NOR circuits 5 and 6, respectively. Also N
The output of OR circuit 5.6 is introduced into the input of NOR circuit 7.8. The output of NOR circuit 7 is introduced into the input of NOR circuit 5.8 and also introduced into the control circuit, and the output of NOR circuit 8 is introduced into the input of NOR circuit 6.7 and introduced into the control circuit.

Inverter 1, 2. AND circuit 3.4, NOR circuit 5,
6 is the same as the conventional input synchronization circuit shown in FIG. 4, but there is a possibility that an intermediate point will appear in the output of the NOR circuit 5.61C at the timing when the input signal and the signal φ change. The logic threshold of the NOR circuit 7 is set high even at the intermediate point where the NOR circuit 5vc may appear. NO
The logic threshold value of the circuit 8 is also set to a low value to avoid any intermediate artifacts that may appear in the NOR circuit 6.

As seen in Figure 2, the input signal is from "1" to rOJ
When the signal φ changes from "1" to "0" at the same time, a signal that rises only up to the logic threshold of the NOR circuit 5 may appear on the AND@ path 3. At this time, the output of the NOR circuit 5 changes from "1" to "0", but A
Since the ND circuit 3 becomes "0", it becomes an intermediate point. - 10,000, A
Since the ND circuit 4ural is used, when the output of the NOR circuit 5 remains at the midpoint, the output of the NOR circuit 6 also becomes the midpoint. As mentioned above, the logic threshold of the 1cNoa circuit 7 is set higher than the intermediate point appearing in the NOR circuit 5, and the ToD and NOR circuit 8
Since the logical quantity [ is set lower than the intermediate point appearing in the NOR circuit 6, each output of the NOR circuit 8.
It becomes lJ. In addition, those output dNOR circuits 5.61C
Since r is introduced from the intermediate value to the output of NOR circuit 5,
To OJ, the output of the NOR circuit 6 changes from the intermediate value to "1". Therefore, the output of the input synchronization circuit and the internal circuit V
No r-frame intermediate value levels occur.

As seen in Fig. 3, when the signal A changes from rOJ to "1" and at the same time the signal φ changes from rlJ to "0",
A signal that rises only up to the logic threshold of the NOR circuit 6 may appear in the AND circuit 4, resulting in rOJ. NO at this time
The output of R circuit 6 changes from "1" to rOJ, but the output of AND circuit 4 becomes "0", so NOR circuit 6
The output of will be an intermediate point. -10,000, the output of AND circuit 3 is "
0", the output of the NOR circuit 5 changes from "0" to "1", but since the output of the NOR circuit 5 becomes the midpoint, the output of the NOR circuit 6 also becomes the midpoint. The operation of the NOR circuit 7.8 in this state Ic is such that the input signal A is r.
This is similar to the case where the signal φ changes from lJ to rOJ and from rlJ to rOJ, and an intermediate point appears at the output of the NOR circuit 5.6. It is clear that the same effect can be obtained when the NOR circuit 7.8t-NANDAND circuit is replaced.

If the logic threshold of the NOR circuit 7 is set to an intermediate value that may be generated from the NOR circuit 5, then the logic threshold of the NOR circuit 8 is t-.
It can be easily inferred that the output vcU of the %NOR circuits 7 and 8 does not produce an intermediate value even if it is set lower than the intermediate value that may be generated from the NOR circuit 6.

C Effects of the Invention As described above, according to the present invention 1c, an input synchronization circuit can be realized in which no intermediate point occurs in the output or internal circuit even if the signal for synchronizing the input signal changes at the same time as the input signal changes. I can do it,
The control circuit that introduces the output of this input synchronization circuit does not malfunction, which is a great advantage of the present invention.

[Brief explanation of drawings]

Figure 1 ζ Circuit diagram of an embodiment of the present invention, Figures 2 and 3
The figure is the operating waveform diagram of Figure 1, and Figure 4 is the conventional circuit diagram.
Figure L and Figure 6 are diagrams of its operation. 1.2, 101.102... Inverter, 3.
4゜103.104...AND circuit, 5.6,
7.8°105.106...NOR circuit. Agent Patent Attorney Uchihara -1-1゛＼ゝ、-1
- ￥-2 life volume 3 parts

Claims (1)

[Claims] An input circuit that has a set/reset function and reads an input signal as a synchronous signal, and an R-S flip-flop that takes the true output and inverse output of this input circuit as input and consists of two NAND circuits or two NOR circuits. The logic threshold of the NAND circuit or NOR circuit which takes the true output of the input circuit as input is higher (or lower) than the intermediate value appearing in the true output, and the NAND circuit or NOR circuit which takes the inverse output as input.
Input synchronization characterized in that the logic threshold of the circuit is set lower (or higher) than the intermediate value appearing at the reverse output, and the true output and reverse output of the R-S flip-flop are connected to the set and reset terminals of the input circuit. circuit.