JPS60103426A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce the frequency with a low-speed processing program in order to realize small power consumption by switching the clock frequency with a prescribed instruction. CONSTITUTION:A computer logic circuit 5 writes 1 on a D-FF6 in a high-speed processing mode. As a result, the output of the 1st (standard) oscillating circuit 1 is prevented by an AND gate 18. Then the 2nd oscillating circuit 2 which has oscillations with a frequency higher than the circuit 1 starts its actuation. This oscillation output is supplied to a clock generator 4 through an OR gate 19. Therefore, a high clock is supplied to a computer logic circuit 6 to perform the high-speed processing. While 0 is written on the D-FF6 in a low-speed processing mode. Thus the actuation of the circuit 2 is discontinued, and the output of the circuit 1 is supplied to the generator 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This article relates to a system for generating a clock signal for a micro combinator (11), particularly for operating a microcomputer (al').

(b) Prior art 4 & C? (The Cro Combiator has ltOM, RAM,
This system consists of an ALtJ, a program color/receiver, an instruction decoder, and various registers. Operates by. Microcomputers were now constructed of C-MOS on a single-chip semicircular pellet, achieving low-level operation and low power consumption.

However, the object to be processed by a single microcomputer requires high-speed processing.

It is necessary to set the oscillation frequency of the oscillation circuit high to match the fastest processing speed of the microcomputer. be. Therefore, the number of high-speed processing is small (
Even in cases where low-speed processing is good, such as a, the launch frequency must be high, which has the disadvantage of increasing power consumption and deteriorating efficiency. By selectively switching the oscillation frequency, it is possible to support programs that require high-speed processing as well as programs that require low-speed processing, thereby providing a microprocessor that achieves low power consumption. The oscillation frequency of the above-mentioned standard @ East circuit was instantly determined by a 71-clock combination equipped with a clock generator to be created and a computer logic circuit which is generated by the clock signal and sequentially executes the programmed instructions. a second oscillation cycle that oscillates at a higher frequency, the oscillation output of the standard oscillation circuit, and rj.
a selection circuit that selectively switches the oscillation output of the second excavation circuit and applies it to the clock generator, and a flip-flop that is set or reset when a predetermined instruction is executed in the computer logic circuit. The output of the flip-flop controls the start and stop of oscillation of the second oscillation circuit, and also controls the switching operation of the selection circuit.

Standard oscillation circuit, (2) is second oscillation circuit, (3) is selection circuit, (4) is clock generator, (5) is computer logic circuit, (6) is D-FF (D type flip 70 tube) It is. The embodiment shown in the figure is probably an example of a watch microcomputer that constitutes the J#1 circuit (not shown) of a liquid crystal display device. In the figure, the standard oscillation circuit (1) is It has a C-MOS inverter (7) and a feedback resistor (8), and oscillates at a frequency of, for example, 32768'llz by a crystal loss element 4 connected to an external terminal (9). The source of the second oscillation circuit (2) is the power supply V.

, , P-channel MOS transistor (I
1), an inverter (121) to which the drain of the P-channel MOS transistor (11) is applied, a delay circuit (0) that delays the output of the inverter (14), and a delay circuit (131) to which the output is applied, and the output is P. Channel MO8
) consists of an N0fL gate 04) connected to the gate of the transistor (11), and an external terminal (
Oscillation 719 is performed by connecting a capacitor (1 (♀) and a resistor (17) to 151, and the oscillation frequency is
The oscillation frequency of the standard oscillation circuit (1) is sufficiently higher than that of the standard oscillation circuit (1), and one-cry is set to about 1M1lz by the capacitor (119) and the resistor Uη.Also, the second oscillation circuit (2)
The oscillation output 08C2 of the inverter 0 is taken out from the output of the inverter 0, and one input of the NOit gate (1a has a D-
The Q output of FFt6) is applied. That is, D −F F
When the Q output of +6) is 1'', the output of NOIt gate (141 is fixed to ``()'', and the P channel M
Since the transistor O8) remains on, the oscillation operation is stopped, and the output of the inverter (1 hot water, that is, the starting output 08C2 becomes ``()''. On the other hand, D - F F (
When the Q output of 6J becomes "0" from "61", the output of the NOR gate a becomes "1" due to the output "0" of the delay circuit (+3), and oscillation starts.
3, for example, is constructed by continuously connecting several stages of If14 inverters.

The selection circuit 13) is the oscillation output 08 of the standard oscillation circuit (1).
The output of the AND gate 081 to which C1 is applied, the output of the AND gate 0, and the oscillation output 0 of the second oscillation circuit (2)
1 consists of 011 gate ul to which 8C2 is applied, AN
By applying the Q output of D −F F (6) to the other input of the D gate (+8), the outputs of the four outputs 08CI and 03C2 are selected and output.The clock generator (4) is connected to the selection circuit ( 3) of the frequency output from (
Based on 4M, multiple clocks No. 6 to operate the microcomputer are created. The computer logic circuit (5) includes a flOM, a RAM, an ALU, a program counter, an instruction decoder, various registers, etc., and performs IF! by a clock signal applied from a clock generator (4). lIf)I
It operates as a computer.

This combination=-talosic circuit +51 has a function of solving ω℃ for an instruction for high-speed processing mode and an instruction for low-speed processing mode, and when the instruction for high-speed processing mode is executed, D-FF (6) is installed. On the other hand, when an instruction to set the low-speed processing mode is executed, D-FF (61 outputs 0")
Output.

Therefore, for example, if a program that is processed by requesting an interrupt fee requires high-speed processing, an instruction to set the high-speed processing mode is provided at the beginning of the program, and up to J4
A command to set JI to low-speed processing mode is provided. As a result, when the interrupt is accepted and the program is executed in the computer logic circuit (5), '1' is first applied to D-FF (6).D-F
l" (61 is Jl) which is applied to the D terminal by one of the clock signals applied to the clock terminal φ
'7, its output Q is "lII," and Q is "θ'°. Therefore, the AND gate 081 to which 0'' is applied cuts off the oscillation output 08CI, while the second oscillation circuit (2
) starts oscillation, and the output 4 output 03C2 is 011 game)
Therefore, the frequency of the clock signal output from the clock generator (4) will be significantly higher than the previous state, and the computer logic circuit (5) will operate at high speed. I will do it.

When the interrupt processing program is finished in the high-speed processing mode, the computer logic circuit (5) finally executes '
0" is applied to D-FF (G). D-FF (6)
By taking in 0"' and setting its output Q to θ" and output Q to l", the second oscillation circuit (2) stops oscillating, and the oscillation output 08C2 becomes "0". On the other hand, AND Game) (IIH) The oscillator output 0SC1 is passed through, and the oscillation output osci is applied to the clock generator (4) through the 011 gate (11).Therefore, the frequency of the clock signal is low, and the computer logic circuit The processing speed of (5) becomes slower.In this state, the oscillation circuit (2) in Figure 2 operates the high frequency oscillation circuit only when the operation is complete, and in the case of normal low-speed processing, By using a low frequency oscillation circuit, the power consumption can be minimized, and the efficiency can be reduced to 0. Therefore, it is effective in a battery-based system.

Explanation of main drawing numbers

Claims (1)

[Claims] 1. A standard oscillation circuit, a clock generator that creates a system clock signal based on the oscillation output of the standard oscillation circuit, and a clock generator that operates based on the clock signal and sequentially executes programmed instructions. a second oscillation circuit that oscillates at a higher frequency than the oscillation frequency of the standard oscillation circuit; an oscillation output of the standard oscillation circuit and oscillation of the second oscillation circuit; a selection circuit that selectively switches the output and applies the clock to the clock generator; and a flip-flop that is set or reset when a predetermined instruction is executed in the computer logic circuit; A micro combinator which controls the start and stop of oscillation of the second 9@prefecture circuit and is capable of selecting a processing speed by controlling switching of the selection circuit. invention