JPS6348203B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing signal generating device having an oscillation circuit for a crystal or ceramic resonator and thereby obtaining various control signals.

[Background of the invention]

Currently, due to advances in IC and LSI manufacturing technology, electronic devices are increasingly becoming CMOS. From this, CMOS
In order to take full advantage of this feature, devices are known that have a function of stopping the clock supply to the device during standby, or even stopping the source oscillation that generates the clock.

However, devices that use crystal or ceramic resonators for their oscillators have the disadvantage that oscillation does not stabilize immediately when the standby mode is released and operation is resumed. For this reason, conventional devices that use crystal or ceramic resonators usually do not have a standby function to stop oscillation, or even if they do have one, the standby function is very limited in that it is only possible to release standby under special conditions. It was hot. Specifically, since at least time is required for the oscillation to stabilize between the signal applied to the device to release the standby and the device actually restarting operation, the standby release signal should be a reset signal for the entire device. Only a limited number of signals were allowed that did not require a fast response.

[Purpose of the invention]

An object of the present invention is to provide a timing signal generator that has a standby mode with low power consumption and can respond quickly to a signal requesting restart of operation.

[Structure of the invention]

The timing signal generation device of the present invention includes: an oscillation circuit using a crystal or ceramic resonator; a timing signal generation circuit that generates various control timing signals based on output signals from the oscillation circuit;
a first control means that stops the operation of the oscillation circuit in response to a first signal; and a second control means that stops the operation of the timing signal generation circuit in response to a second signal.
a counter that counts output signals from the oscillation circuit and obtains a signal for a certain period of time;
the control means controls the operation of the timing signal generation circuit, the counter is initialized by the third signal when the oscillation circuit is in a stopped state, and the second control means and means for controlling the operation of the timing signal generation circuit.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 10 is an oscillation circuit, 20 is a timing signal generation circuit composed of a frequency divider and other logic circuits, and 21 is a timing signal generation circuit 20.
These are various control timing signals such as control clocks and state signals obtained by. 30 and 40 are an oscillation circuit 10 and a timing signal generation circuit 20, respectively.
This is a flip-flop used to obtain a signal to stop the operation of the flip-flop. Further, 60 is a counter that counts the signal from the oscillation circuit 10 and outputs an overflow signal after a certain period of time; 50 is a pulse generation circuit activated by the signal 80; This is a delay circuit that delays the signal 80 for a long time.

In the block diagram shown in FIG. 1, flip-flops 30 and 40 are set by signals 34 and 44 to put the device into standby. These signals 34, 44 may be supplied from outside the device or may be generated internally. At this time, both the timing generation circuit 20 and the oscillation circuit 10 stop their operations, and the power consumption of the device becomes the lowest. Further, if only the flip-flop 40 is set by the signal 44, only the generation of the timing signal is stopped, and the device stops its operation and enters a standby state, but the oscillation circuit 10 continues to operate. The power consumption at this time is necessary for the oscillation circuit operation, but since the oscillation circuit 10 continues to operate from the standby state to the operating state, there is no need to consider the time until the oscillation stabilizes, and the transition is easy. I am in a position to do so.

Now, of the two types of standby states mentioned above, the former will be called a stop state, and the latter will be called a halt state.

Next, the procedure for canceling the standby state and transitioning to the operating state will be explained with reference to FIGS. 2 and 3 showing operating signal waveforms. FIG. 2 is a diagram illustrating the procedure for canceling standby when the device is in a stop state using operation waveforms of various signals. In the stop state, flip-flop 30 is set and signal 32 is high. First, a request to cancel standby is given by signal 80.
This standby release request signal may be given from outside the device, or may be a specific signal inside the device, such as an overflow signal from a counter that operates independently of the timing signal of the device. signal 8
0, the pulse generating circuit 50 generates a one shot pulse. Also, the signal 80 is the delay circuit 31
The flip-flop 30 is reset via the . At this time, since the flip-flop 30 is reset after a certain time delay from the generation of the signal 80, the pulse signal generated by the pulse generation circuit 50 is inhibited by the inverter 33 and the AND gate 51, and has no effect on the flip-flop 40. do not have.

As the flip-flop 30 is reset, the oscillation operation of the oscillation circuit 10 is restarted. Since the oscillation circuit output signal 11 is input to the counter 60 and initialized by the pulse signal from the pulse generation circuit 50 described above, an overflow signal is output from the counter 60 after a preset period of time required for the oscillation to stabilize. Occur. As a result, the flip-flop 40 is reset via the OR gate 70, and the timing generation circuit also resumes its operation to begin normal operation.

Next, the procedure for canceling standby when the device is in the halt state will be explained. FIG. 3 is a diagram of various signal waveforms showing a procedure for releasing the device when it is in a halt state. For convenience of explanation, the same numbers as in FIG. 2 are used for the signal waveform diagrams. In the halt state, the flip-flop 30 is not set and the oscillation circuit 10 performs a steady oscillation operation. Here, when a request for canceling standby is given by signal 80, a pulse is generated by pulse generating circuit 50 in the same manner as explained for canceling the stop state. At this time, flip-flop 30 is in the reset state and the pulse passes through AND gate 51 and resets flip-flop 40 via gate 70. Therefore, the operation of the timing generation circuit 20 is immediately restarted without waiting for the time determined by the counter 60 by the standby release request by the signal 80.

〔Effect of the invention〕

As explained above, according to the present invention, when in the stop state due to the same standby release request signal, the device operation resumes after the oscillator operates stably, and when in the halt state, there is no waiting time. Since it is possible to restart the device operation quickly, power consumption can be sufficiently reduced depending on the device operation.
A timing signal generator can be obtained that can flexibly operate in response to signals at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are timing charts showing its operation. 10... Oscillation circuit, 20... Timing signal generation circuit, 21... Control timing signal, 30, 4
0...Flip-flop, 31...Delay circuit, 3
3... Inverter, 50... Pulse generation circuit, 5
1...and gate, 60...counter, 70...
…orgate.

Claims (1)

[Claims] 1. An oscillation circuit using a crystal or ceramic resonator, a timing signal generation circuit that generates various control timing signals based on the output signal from the oscillation circuit, and a timing signal generation circuit that stops the operation of the oscillation circuit in response to a first signal. a first control means, a second control means for stopping the operation of the timing signal generation circuit in response to a second signal, a counter that counts output signals from the oscillation circuit and obtains a signal for a certain period of time; When the oscillation circuit is in an operating state, a third signal causes the second control means to control the operation of the timing signal generation circuit, and when the oscillation circuit is in a stopped state, the third signal causes the counter to be controlled. A timing signal generating device comprising means for initializing the timing signal generating circuit and causing the second control means to control the operation of the timing signal generating circuit according to the predetermined time signal.