JPS6135565B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that operates using a clock signal from an oscillation circuit as a reference clock signal.

In recent years, with advances in LSI (Large-Scale Integrated Circuit) manufacturing technology, electronic devices are becoming smaller and have lower power consumption. Also, in data processing equipment, it has low power consumption as a component of electronic circuits.
CMOS (complementary field effect transistor) manufacturing technology has been used.

Generally, it is known that the power consumption of a CMOS circuit is proportional to ^fcV2 , where f is the operating frequency of the circuit, c is the stray capacitance, and V is the operating voltage. Therefore, by changing the oscillation operation of the reference clock and lowering the effective frequency, it is possible to reduce the power consumption of the entire device as much as possible.

Conventionally, attempts have been made to temporarily stop the oscillation of a clock signal in order to reduce the power consumption of a data processing device. However, in order to restart the clock oscillation operation, a start signal must always be input from outside the device. Moreover, in this case, the start signal is used as the same signal that sets the entire device to its initial state when the power is turned on, so whether the device operates from its initial state after clock oscillation starts or whether it is in a paused state. It was necessary to distinguish between what works and what works. Since this discrimination had to be performed by program processing such as checking the contents of RAM, a very long time was required for the discrimination.

Further, when a crystal oscillator or the like is used as the clock oscillation element, it takes several tens of milliseconds from the start of oscillation until stable oscillation is obtained due to the characteristics inherent to the oscillator. Therefore, there are drawbacks such as the data contents of the data processing section being destroyed or programmed instructions not being executed until the clock signal becomes stable.

Furthermore, when the oscillation is stopped, the power consumption of the circuit operated by the clock signal becomes almost zero, but no processing can be performed during the stop period.

An object of the present invention is to provide a data processing device that prevents device malfunction and reduces power consumption.

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Another object of the present invention is to provide a data processing device equipped with a control means that absorbs the unstable oscillation period from the restart of clock oscillation until the clock oscillation becomes stable and realizes stable oscillation operation.

Still another object of the present invention is to provide a data processing device that has both low power consumption and high speed processing functions.

The data processing device of the present invention includes a processing section that executes data processing based on a program, a clock generation section that generates a clock signal that controls the timing of processing operations in the processing section, and a clock generation section that supplies the clock signal to the processing section. a clock supply section that stops the generation of the clock signal in the clock generation section; and a prohibition section that prohibits the supply of the clock signal from the clock supply section to the processing section;
The invention is characterized in that the prohibition section controls the clock supply section for a predetermined period after the clock generation section starts generating the clock signal, thereby inhibiting the supply of the clock signal.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a data processing apparatus according to an embodiment of the present invention. Data processing section 1
includes ROM, RAM, ALU, etc., and stores processing procedures, that is, programs. The commands programmed here are decoded by the control section 2 and generated as control signals. Some of the generated control signals 3 and 4 control the clock signal generating section 5, and other control signals control the data processing section 1. The clock signal generating section 5 includes a clock oscillation circuit and a clock supply circuit, and supplies a reference clock signal 6 to the data processing section 1 via the clock supply circuit. In order to generate the clock signal 6, it is necessary to connect a crystal oscillator or the like to the clock oscillation circuit from outside the device. 7 is an input signal of the oscillator clock, and 8 is an output signal of the oscillator clock. 9
is an external input signal that sets the entire device to an initial state when power supply voltage is supplied. In some cases, a microcomputer etc. is set to an initial state at the same time as the power is turned on. 10 is an external input signal requesting restart of clock oscillation.

An embodiment of the clock signal generating section 5 will be shown below. FIG. 2 is a circuit diagram of the clock signal generating section 5 according to an embodiment of the present invention. Clock oscillation circuit 11 for generating a reference clock signal includes an inverter 26 and an AND gate 27. This oscillation circuit 11 includes a crystal resonator 12 outside the device.
and a resonant circuit consisting of capacitors 13 and 14 are connected. Reference numeral 15 denotes a control signal requesting to stop oscillation of the clock, which is output from the control section 2 in FIG.
Oscillation stop flip set by control signal 15
The flop 16 outputs a stop signal c to the oscillation circuit 11. Here, the stop signal c is connected to the AND gate 27 to control opening and closing of the oscillation loop. Furthermore, this stop signal c also controls the operation of the counter 17 (time circuit). The counter 17 is composed of, for example, a programmable counter, and generates an end signal e when it counts the reference clock signal a generated from the clock oscillation circuit 11 by a predetermined number as a count input signal. When the data processing apparatus operates normally, the reference clock signal is supplied to the data processing section 1 shown in FIG. 1 to control the timing of data processing. Clock signal a is AND gate 2
5 is open, it is supplied to the data processing section 1 as a timing signal b. The opening/closing control of this AND gate 25 is performed by an inverted signal of the output signal f of the clock inhibit flip-flop 22. Clocks prohibited flip/flop 22 is OR
It is set by the output of gate 24, and OR gate 21
It is reset by the output of A clock prohibition request signal 15 and a clock supply prohibition signal 23 from the control section (instruction decoding section) 2 shown in FIG. 1 are input to the OR gate 24. On the other hand, the OR gate 21 receives the output signal e of the counter 17 as a timer circuit and an inverted signal of the initial setting signal 19 input from the outside. Furthermore, the oscillation stop flip-flop 16 is
It is reset by the output of OR gate 20.
The OR gate 20 receives a clock restart request signal 18d applied from outside the device and an initial setting signal 19.
is input. Therefore, the oscillation stop flip-flop 16 set by the stop request signal 15
is reset by the restart instruction signal 18. As a result, an oscillation loop of the clock oscillation circuit 11 is formed and the oscillation operation starts. In addition, initial setting signal 1
9 to set the device to the initial state, the clock oscillation circuit 11 executes the oscillation restart operation. The supply stop flip-flop 22 is set by the oscillation stop request signal 15 and the supply prohibition signal 23.
The reference clock a generated from the clock oscillation circuit 11 is inhibited from being supplied to the data processing section. In this state, no reference clock is supplied to the data processing section and the control section, so no data processing is performed.

Now, when the clock oscillation stop command is read out from the data processing unit (1 in Figure 1), this command is decoded and the clock oscillation stop request signal 15 (3 in Figure 1) is sent from the control unit (2 in Figure 1). equivalent) will be generated. The oscillation stop flip-flop 16 is set by this signal 15, and the oscillation stop signal C is sent to the oscillation circuit 11. On the other hand, supply prohibited flip-flop 22
is also set, so the AND gate 25 is also closed. Next, when the oscillation restart instruction signal 18 is applied from outside, the oscillation stop flip-flop 16 is reset and the oscillation stop signal C disappears. As a result, an oscillation loop is formed in the oscillation circuit 11 and an oscillation output (clock signal) a is generated. However, this clock signal a is inhibited by the AND gate 25 and is not supplied to the data processing section. The inhibited state is canceled when the counter 17 completes a predetermined number of logarithms based on the clock signal a. Therefore, it is necessary to set a count value in the counter 17 before stopping clock oscillation.
It is desirable that the count value be equal to the period until the oscillation circuit 11 reaches a stable oscillation state.

Furthermore, in FIG. 2, the clock supply to the data processing section can be inhibited for a predetermined period without stopping clock oscillation. In this case, by executing the clock supply prohibition command and generating the clock prohibition request signal 23 from the control section, the counter 1
The AND gate 25 will be closed only for the period determined by 7. Therefore, the clock supply can be inhibited only for a desired period of time. This has the effect of enabling intermittent operation of the data processing section.

The above operation will be explained in more detail using the timing diagrams of FIGS. 3 and 4.

As is clear from FIG. 3, in the operation stop state (period t ₂ ) in which both the oscillation stop flip-flop 16 and the supply prohibition flip-flop 22 are set by the control signal 15, the clock oscillation circuit 1
1 stops oscillation. When a restart request signal 18 is input from the outside during this operation stop state, the oscillation stop flip-flop 16 is reset. As a result, the clock oscillation circuit 11 starts oscillating. However, as shown in period _t3 , the amplitude of the clock pulse is small and the oscillation is not stable. During this period _t3 , the reference clock signal is counted by a timer composed of a counter 17, and when it reaches a predetermined value, a high level (logic "1") output signal e is output. This resets the supply inhibit flip-flop 22, opens the AND gate 25, and supplies the timing signal b to the data processing section. Therefore, the inside of the device enters a normal operating state (period t ₄ ).

Next, the clock signal a is output from the clock oscillation circuit 11.
The intermittent operation state in which the supply of timing signal b to the data processing section is suppressed while oscillation is being oscillated will be described with reference to FIG. Fourth
In the figure, periods t ₁ , t ₃ , and t ₅ are in a data processing state, and periods t ₂ , t ₄ , and t ₆ are in a processing halt state. If processing abort is requested, only the inhibit signal 23 is generated. Therefore, oscillation stop flip-flop 1
Since clock 6 remains reset, clock signal a is always output. That is, the clock oscillation circuit 11 executes a clock oscillation operation.
Now, when the supply inhibit flip-flop 22 is set by the control signal 23, the timing signal b
is no longer supplied to the data processing unit. During this operation stop state (periods t ₂ , t ₄ , t ₆ ), the reference clock signal is counted by a timer consisting of a counter 17, and the supply of the clock is prohibited for the counting period. By setting the count value of the counter 17 to a desired value, the operation stop period can be arbitrarily set. When the contents of the counter 17 reach a predetermined value, a high level (logic "1") output signal e is output, and the supply inhibit flip-flop 2 is output.
2 is reset. As a result, AND gate 25
opens, timing signal b is supplied to the data processing section, and processing operation is started. When the clock supply control flip-flop 22 is set again by the control signal 23 generated by the control section 2, the above operation is repeated, and the data processing section repeats the intermittent operation.

According to the present invention, as explained above, an oscillator such as a crystal oscillator, which takes several tens of milliseconds from the start of oscillation to stabilization, is used as the reference clock signal generation source.
Since the data processing device has a control means for stopping the supply of the clock signal, a control means for restarting the supply of the clock signal, and a control means for stabilizing the restart of the clock, the effective frequency is lowered.
It is possible to further improve the efficiency of low power consumption, which is a feature of CMOS circuits. Further, according to the present invention, it is possible to control the data processing state of the data processing device such as normal operation, intermittent operation, and operation stop. In particular, the power consumption is several tenths of that of normal operation when the operation is stopped.
It will be a few hundredths of a percent. Furthermore, since the intermittent operation is determined by the ratio of the time of normal operation and the time of stopped operation, it is possible to easily reduce power consumption. Particularly, for example, when the main power supply is turned off, the oscillation operation is stopped for an operation where the contents of the memory are simply backed up by the auxiliary power supply, so that the power consumption of the auxiliary power supply can be suppressed as much as possible. On the other hand, when the display section is driven intermittently, such as when displaying a clock, power consumption during operation can be saved by prohibiting clock supply to the display section except for a predetermined period.

In this embodiment, the setting of the period from the start of oscillation to stable oscillation and the setting of the supply prohibition period for controlling intermittent operation are executed by the same counter, but they are different counters. Good too.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing an embodiment of the clock signal generator of the present invention, and FIGS. 3 and 4 are operation timing diagrams, respectively. . 1...Data processing unit, 2...Control unit, 3, 4...
...Control signal, 5...Clock signal generator, 6...
Clock signal, 7... Input signal of the oscillator clock, 8... Output signal of the oscillator clock, 9, 10
...External input signal, 11...Clock oscillation circuit,
12... Crystal oscillator, 13, 14... Capacitor, 15... Control signal, 16... Clock stop flip-flop, 17... Counter, 18...
...External input signal, 19...External input signal, 20,
21, 24...OR gate, 22...clock supply control flip-flop, 23...control signal,
25...AND gate. 〓〓〓〓

Claims (1)

[Claims] 1. In a data processing device having a processing section that processes a program under timing control by a clock signal, and a clock generation section that generates the clock signal, a gate circuit is provided between the clock generation section and the processing section. The gate circuit is configured to respond to a first signal for inhibiting the supply of a clock signal and a second signal for stopping the clock generation operation, and further configured to respond when a predetermined period of time has elapsed since the clock generation operation was stopped. A data processing device comprising: a control unit that closes the gate circuit until the gate circuit is closed.