JPS6240886B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillator, and more particularly to an oscillator that generates a clock signal.

Generally, information processing devices and the like are controlled by clock signals, and an oscillator is used to generate the clock signals. It is recognized that this oscillator, especially an oscillator that amplifies mechanical vibrations such as a crystal oscillator, oscillates at an unstable frequency at the start of oscillation. Therefore, in conventional information processing equipment having this type of oscillator, the clock signal supplied at the start of its operation was based on the above-mentioned unstable oscillation. There was a risk of malfunction. In addition, in order to prevent clock signals based on this unstable oscillation, it was necessary to add a very expensive clock generator, which made the overall configuration of the oscillator larger and more complex, and increased power consumption. It had the disadvantage of being

The present invention has been made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide an oscillator which easily and with a simple circuit configuration prevents the output of a clock signal during unstable oscillation.

In order to achieve the above object, the oscillation device of the present invention includes:
A clock generator that generates a clock signal by oscillating with a resonator having a predetermined natural frequency, a counter that has a function of counting the clock signal from this clock generator, and a gate circuit that outputs the clock signal. and is configured to output a control signal when the count value of the counter reaches a predetermined value, thereby closing the gate circuit and outputting the clock signal.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a rotating configuration when an oscillator according to an embodiment of the present invention is connected to a microprocessor. The oscillation source 1 is composed of a crystal resonator, a ceramic resonator, etc., and oscillates at a constant oscillation frequency by mechanical vibration. The clock generator 2 oscillates from the oscillation source 1 and uses its oscillation frequency output to generate a clock signal 8 having a predetermined frequency component necessary for the operation of the microprocessor 6. Further, when the clock generator 2 receives the clock stop signal 7 outputted from the microprocessor 6, it stops generating the clock signal 8. Further, the counter 3 inputs the clock signal 8 from the clock generator 1, counts the number of pulses thereof, and generates a carry signal 10 when the number of pulses exceeds a predetermined value. On the other hand, the flip-flop 4 is set by the carry signal 10 from the counter 3, and outputs a control signal 11 to the AND circuit 5 at the output stage. The AND circuit 5 supplies the clock signal 8 from the clock generator 2 to the microprocessor 6 as the operating clock signal 9 while the control signal 11 from the flip-flop 4 is being supplied. Microprocessor processing section 6
is set to an operable state by inputting an operating clock signal 9. Further, the microprocessor processing unit 6 outputs a clock stop signal 7 to the clock generator 2, counter 3, and flip-flop 4 at the end or break of program processing, respectively, to stop the operation of the clock generator 2, and to stop the operation of the counter 3 and flip-flop 4. is configured to reset the When this clock stop signal 7 is released, the clock generator 2 is again set to the clock generation start state.

Next, the specific operation of the embodiment shown in FIG. 1 will be explained.

When the oscillation source 1, clock generator 2, counter 3, flip-flop 4, AND circuit 5, and microprocessor 6 are in operation, the clock signal generated by the clock generator 2 is passed through the AND circuit 5. , are input to the microprocessor processing section 6, and the processor uses the clock signal 9 as a reference clock to create machine cycles and control signals for each section and executes predetermined program processing. Now, when the microprocessor 6 finishes program processing or interrupts it in the middle, the processor processing unit 6
outputs a clock stop signal 7 based on an instruction executed internally at the end of processing, and outputs a clock stop signal 7 to the clock generator 2.
to be inactive. As a result, generation of the clock signal is prohibited, and the microprocessor 6 also stops processing. At this point, the output of the flip-flop 4 and the output of the clock generator 2, which are input to the AND circuit 5, are both at low level "0". After this, when the microprocessor 6 executes a new program process or continues a previously interrupted process, the processor processing unit 6 is supplied with an operating power supply voltage or is controlled by other control means (external keys). operation, etc.). The control signals used at this time include various signals such as reset, start, and power on. When the clock stop signal is released by these signals, the clock generator 2 outputs the clock signal 8.
begins to occur. This clock signal 8 is transmitted to the counter 3 and the AND circuit 5. From this point on, the counter 3 starts counting the clock signal 8. The necessity of this counter 3 is due to the fact that the crystal oscillator 1
Since the crystal oscillator 1 is extremely unstable at the start of its oscillation, it is necessary to prevent undesired clock pulses based on unstable oscillation from being supplied to the microprocessor processing unit 6 until the crystal oscillator 1 starts stable oscillation. This is to avoid it. Therefore, for example, when using an oscillation source 1 that generates 10,000 unstable clock signals until the frequency of the clock signal 8 becomes stable, the counter 3 will be reset at the 10,000th input pulse after being reset. The carry signal 10 is configured to generate a carry signal 10. In this way, the clock signal 8
Since the carry signal 10 is not output when the clock signal is less than 10,000 times, the output signal of the flip-flop 4 becomes a low level "0" while an unstable clock signal is generated. Therefore, the AND circuit 5 is closed, the operating clock signal 9 is not supplied to the microprocessor 6, and when a sufficient and minimum time has elapsed for the crystal oscillation source 1 to perform stable oscillation, For the first time, the AND circuit 5 is opened and a stable clock signal 9 having the desired period is supplied to the microprocessor processing unit 6.

As described above, according to this embodiment, when the microprocessor processing section 6 is in the non-operating state, generation of the clock signal and supply to the processing section are prohibited to save power consumption, and it is also possible to prevent the clock signal from starting its operation. Input of a stable clock signal is prohibited, and malfunctions of the processor processing section 6 can be prevented.

Although this embodiment uses a counter 3 that counts the pulse signal 8 of the pulse generator 2 having a predetermined frequency component from the oscillation signal from the crystal oscillation source 1 for a predetermined period, the present invention is not limited to this. Instead, a timer circuit may be used that sets the flip-flop 4 at the start of oscillation of the oscillator or after a predetermined period from an operation start instruction signal (reset, start, etc.) to the processor.
It is obvious that this counter 3 can be used as long as it is possible to delay the output signal for a predetermined period, such as the above-mentioned timer circuit shift register.

Furthermore, since all of the oscillation circuits shown in FIG. 1 can be configured as digital circuits, they can be integrated into an integrated circuit. A processing device that is inexpensive and has good operability can be obtained. Furthermore, if a program counter whose calculated value can be freely changed by external control or control (command) within the device is used as the counter 3, a more versatile information processing device can be obtained.

Furthermore, according to the present invention, if a control signal from an external processing device is used as a signal for canceling a clock stop signal that is input to a clock generator, this processor can be used not only to start oscillation but also to arbitrarily cancel the clock stop signal in the middle of normal processing. The processing unit 6 can be set to a non-operating state. This means that it can be applied, for example, as a means for determining priorities in a multiprocessor configuration. The present invention, which can temporarily stop the supply of clock signals in this way,
It also has many applications in terms of processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention when connected to a microprocessor. 1...Oscillation source, 2...Clock generator, 3...
Counter, 4...Flip-flop, 5...
AND circuit, 6... microprocessor processing section,
7... Clock stop signal, 8... Clock signal,
9...Operating clock signal, 10...Carry signal, 11...Flip-flop output signal.

Claims (1)

[Claims] 1. An oscillator having a vibrator, a counting circuit that counts the number of oscillations of a signal generated from the oscillator, and a gate that controls transmission of the oscillation signal from the oscillator to an output terminal according to the counting result of the counting circuit. 1. An oscillation device comprising: a circuit, wherein after the counting circuit counts a predetermined number of oscillation signals from the oscillator, the oscillation signal from the oscillator is obtained from the output terminal.