JP2959223B2 - Clock oscillator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock oscillator mounted on a semiconductor integrated circuit and generating a clock signal, and more particularly to a clock oscillator connected to a crystal oscillator to form an oscillation circuit.

[0002]

2. Description of the Related Art Generally, a semiconductor integrated circuit, particularly a microcomputer (hereinafter referred to as "microcomputer") performs command processing and various operations by using a reference clock signal. Especially when it is necessary to perform processing or operation at a high speed, the clock signal has high accuracy and stability, that is,
A crystal oscillator is used. However, a crystal oscillator has high accuracy and stability as an oscillation frequency, but requires about 20 to 30 msec from the start of oscillation to stabilization.

[0003] Therefore, the instruction processing after the standby mode is released is executed after the oscillation is stabilized after 20 to 30 msec elapses after the crystal oscillator starts oscillating.

FIG. 7 is a block diagram showing an example of a conventional oscillator used in a microcomputer. Crystal oscillator 1, oscillation circuit 2, counter 3, RS flip-flop (hereinafter referred to as
F / F) 4 and an AND gate 5. The oscillation circuit 2 oscillates when the crystal oscillator 1 is connected to the terminals A and B, and outputs a clock signal 11. Oscillation circuit 2
Oscillation and stop are controlled by a STOP signal, and the oscillator oscillates at a low level of the STOP signal and stops at a high level.

[0005] The counter 3 counts the clock signal,
An overflow signal 12 is output. Overflow time is, for example, 30 msec (time until oscillation stabilizes)
Is set to The counter 3 is cleared when the clock signal at which the STOP signal becomes high stops. F
/ F4 is set by the overflow signal 12 of the counter 3 and reset by the high level of the STOP signal. The output signal 13 of the F / F 4 is input to the AND gate 5. The AND gate 5 outputs the clock signal 11 to the inside of the microcomputer in response to the input of the signal 13.

Next, the operation at the time of standby will be described with reference to the timing chart of FIG. Upon entering standby, the STOP signal goes high, the oscillation circuit 2 stops oscillating, the counter 3 is cleared, and the F / F
4 is reset. Therefore, the output signal 1 of the F / F 4
3 becomes low level, and the clock signal 11 is not transmitted to the inside of the microcomputer by the AND gate 5. That is, a standby state is set.

Next, when the standby mode is released, the STOP signal goes low, and the oscillation circuit 2 starts oscillating. However, if the oscillation stabilization time of the connected crystal oscillator 1 has not elapsed, the overflow signal 12 is not output, so that the F / F 4 is not set. Therefore, output signal 1
3 remains at the low level, so that the clock signal 11
It is not transmitted as the output of D gate 5.

The counter 3 counts the clock signal 11 and sets the oscillation stabilization time (20 to 3).
0 ms), the signal 12 goes high, and F /
F4 is set, the signal 13 goes high, and the clock signal 11 is output through the AND gate 5.

As described above, in the conventional microcomputer, the oscillation stabilization time is obtained by using the counter 3, and the clock signal 11 can be output in a stable state.

[0010]

However, in the above-mentioned conventional microcomputer, a clock signal cannot be obtained immediately after the standby mode is released until the oscillation of the crystal oscillator is stabilized.
For this reason, there is a disadvantage that it is not possible to execute an urgent instruction process after the release of the standby mode, and it is not possible to cope with such an application.

Note that the oscillation stabilization time varies depending on the oscillation frequency, and is about 30 msec at several MHz, but it is known that the oscillation stabilization time becomes longer when the oscillation frequency is low. The above-mentioned problem becomes more remarkable.

The present invention has been made in view of the above problems, and has as its object to provide a clock oscillator that can obtain a clock signal without waiting for the time until the crystal oscillator stabilizes.

[0013]

According to the clock oscillator of the present invention, the first STOP signal is changed from the first logical level to the second logical level.
When the logic level changes to 2, the first clock signal
A crystal oscillation circuit for starting oscillation to output,
The STOP signal is changed from the second logic level to the first logic level.
Reset when the level changes to the
RS type free set by the released signal
Flip-flop and output signal of the RS flip-flop
And the first STOP signal are input and the second STOP signal
And an OR gate for outputting a second STOP signal.
Changing from the first logic level to the second logic level
Immediately, stable oscillation occurs and the second clock signal
An RC oscillation circuit for outputting a first clock signal;
And the second clock signal are input, and the RS type
The output signal of the flip-flop is at the first logic level.
Select the first clock signal,
When the output signal of the flip-flop is at the second logic level
In some cases, the second clock signal is selected and the
And a selector that outputs the internal clock signal of the
For example, it characterized the Rukoto. Other clock oscillation according to the present invention
The first STOP signal changes from the first logical level to the second
Output the first clock signal when the logic level changes to
A crystal oscillation circuit for starting oscillation to apply
The TOP signal changes from the first logic level to the second logic level.
Reset when the level changes to the first
When the number of counted clock signals reaches a predetermined number,
A counter for outputting a bar flow signal;
When the TOP signal changes from the second logic level to the first logic level,
Reset when the level changes
RS flip-flop set by low signal
And an output signal of the RS flip-flop and the first
A STOP signal is input and a second STOP signal is output
An OR gate and the second STOP signal are the first logic
From the logical level to the second logical level.
Output a second clock signal with stable oscillation
An RC oscillation circuit, the first clock signal and the second
Is input, and the RS flip-flop is
If the output signal of the loop is at the first logic level,
Selecting the first clock signal, and selecting the RS type flip-flop;
If the output signal of the flip-flop is at the second logic level,
Select the second clock signal and select the internal clock of the microcomputer.
And a selector for outputting as a clock signal.
I do.

[0014]

In the present invention, the second oscillation circuit generates a clock signal by charging and discharging the electric charge. Therefore, immediately after the standby mode is released, the selecting means selects the clock signal of the second oscillation circuit to thereby generate the clock signal. Can output a clock signal immediately after the standby mode is released.
On the other hand, after the lapse of a certain time, the oscillation of the oscillator is stabilized, and the selecting means selects the clock signal of the first oscillation circuit. Thereby, a highly accurate clock signal can be obtained.

[0015]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, the present embodiment employs a crystal oscillator 1,
It comprises an oscillation circuit 2, an RC oscillation circuit 6 using resistors and capacitors, a selector 7, an F / F 4, and an OR gate 8. The oscillation circuit 2 oscillates when the crystal oscillator 1 is connected to the terminals A and B, and outputs a clock signal 11.
The oscillation and stop of the oscillation circuit 2 are controlled by a STOP1 signal, and the STOP1 signal oscillates at a low level,
Stop at high level.

The clock signal 15 is output by the oscillation of the RC oscillation circuit 6. Oscillation and stop of the RC oscillation circuit 6 are controlled by a STOP2 signal.
Oscillates at a low level of the STOP2 signal and stops at a high level. The selector 7 selects one of the clock signal 11 and the clock signal 15 and outputs the selected signal to the inside of the microcomputer.

The F / F 4 is set by a release signal 16 and reset by a STOP 1 signal. The release signal 16 is a signal which becomes high level by the execution of the instruction of the microcomputer after the oscillation stabilization time of the crystal oscillator 1 has elapsed. The output signal 13 of the F / F 4 is input to the selector 7 and selects a clock signal. OR gate 8 is F / F4
A STOP2 signal is output according to the output signal 13 and the STOP1 signal.

Next, the RC oscillation circuit 6 will be further described with reference to FIG. FIG. 3 is a circuit diagram showing an example of the RC oscillation circuit 6. As shown in FIG. 3, the RC oscillation circuit 6 includes a resistor 20, a capacitor 21, inverters 22 to 24, and N
It is composed of an AND gate 25, and oscillation and stop are STOP.
Controlled by signals. That is, the RC oscillation circuit 6 stops the oscillation when the STOP signal is at a low level and starts the oscillation when the STOP signal is at a high level.

FIG. 4 is a timing chart of the circuit shown in FIG. Since the points C and D have the waveforms shown in FIG. 4 due to the charge and discharge of the capacitor, it can be seen that the clock signal (point D) can be obtained immediately after the standby mode is released.

Next, the operation of the clock oscillator of the present embodiment will be described with reference to the timing chart of FIG. Upon entering standby, the STOP1 signal goes high, the oscillation circuit 2 stops oscillating, and the F / F 4 is reset. Therefore, the output signal 13 of the F / F 4 becomes low level, the selector 7 is switched, and the clock signal 15 is selected, so that the clock signal 11 is not transmitted to the inside. Further, since the STOP2 signal becomes high level, the RC oscillator 6 is stopped, and the clock signal 15 is not transmitted to the inside even if selected by the selector 7. That is, a standby state is set.

Next, when the standby mode is released, the STOP
Since the signal 1 goes low and the STOP2 signal output from the OR gate 8 also goes low, both the oscillation circuit 2 and the RC oscillation circuit 6 start oscillating. However,
Even when the STOP1 signal goes low, the selector 7 does not switch because the output signal 13 of the F / F 4 remains low. Therefore, the clock signal 15 passes through the selector 7 and is transmitted to the inside of the microcomputer as the clock signal 14 from the time of releasing the standby mode.

Thereafter, the oscillation stabilization time of the crystal oscillator (about 3
0msec), and after a command from the microcomputer,
By setting the release signal 16 to high level,
The F / F 4 is set, and the signal 13 goes high.
The time count of about 30 msec can be calculated from the frequency of the clock signal 15 and the number of instruction execution steps in the microcomputer.
As a result, the selector 7 switches, and the clock signal 1
1 is selected and transmitted to the inside of the microcomputer. Also,
Since the STOP2 signal becomes high level, the RC oscillation circuit 6 is stopped. In this way, the clock signal 14 can be obtained immediately after the release of the standby mode.

As a method of counting the oscillation stabilization time of the crystal oscillator, in the first embodiment described above, a microcomputer instruction is executed, that is, a software counting method is used. In the second embodiment described below, a counter is used. The counting is performed by a hardware counting method. In this case, there is an advantage that the microcomputer does not need to count about 30 msec and can execute other processing.

FIG. 5 is a block diagram showing a clock oscillator according to a second embodiment of the present invention. In this embodiment, a crystal oscillator 1, an oscillation circuit 2, a counter 3, an RC oscillation circuit 6,
It comprises a selector 7, an F / F 4 and an OR gate 8. The oscillation circuit 2 oscillates when the crystal oscillator 1 is connected to the terminals A and B, and outputs a clock signal 11. The oscillation and stop of the oscillation circuit 2 are controlled by the STOP1 signal. The STOP1 signal oscillates at a low level and stops at a high level.

The counter 3 counts the clock signal 11 and outputs an overflow signal 12. The overflow time is set to, for example, 30 msec (the time until oscillation stabilizes). When the clock signal is stopped by the STOP1 signal, the counter 3 is cleared. R
The clock signal 15 output from the C oscillation circuit 6 is input to the selector 7, and its oscillation and stop are controlled by the STOP2 signal. The STOP2 signal oscillates at a low level and stops at a high level.

The selector 7 selects one of the clock signal 11 and the clock signal 15 and outputs the selected signal as a clock signal 14 to the inside of a microcomputer which is a semiconductor integrated circuit. F / F 4 is an overflow signal 12 of counter 3
And reset by the STOP1 signal. The output signal 13 of the F / F 4 is input to the selector 7 and switches the clock signal 11 or 15. The OR gate 8 outputs a STOP2 signal according to the output signal 13 of the F / F4 and the STOP1 signal.

Next, the operation at the time of standby of this embodiment will be described with reference to the timing chart of FIG.

When the standby mode is entered, the STOP1 signal goes high, the oscillation circuit 2 stops oscillating, and the F / F4
Is reset. Therefore, the output signal 13 of the F / F 4
Becomes low level, the selector 7 switches, and the clock signal 15 is selected. Therefore, the clock signal 11 is not transmitted as the output of the selector 7.

Since STOP2 is also at a high level, R
The C oscillating circuit 6 is stopped, and the clock signal 15 is not transmitted to the inside even if selected by the selector 7. That is, a standby state is set.

Next, when the standby mode is released, the STOP
When the signal 1 is at the low level, the STOP2 signal is also at the low level, the oscillation circuit 2 and the RC oscillation circuit 6 both start oscillating, and the clock signals 11 and 15 are output. However, even if the STOP1 signal goes low, the F / F4
Since the output signal 13 of FIG.
Does not switch. Therefore, the clock signal 15 is transmitted to the inside of the microcomputer as the clock signal 14 which is the output of the selector 7 from the time of releasing the standby mode.

Thereafter, the counter 3 counts the clock signal 11 and sets the oscillation stabilization time (30 mse
When the signal reaches c), the signal 12 becomes high level and the F / F4
Is set, the signal 13 goes high, and the selector 7 switches. Therefore, the clock signal 15 is selected and transmitted to the inside of the microcomputer. Also, STOP
Since 2 goes to a high level, the RC oscillation circuit 6 stops.

It should be noted that the present invention is not limited to the above-described embodiment, but includes a case where a frequency dividing circuit or a multiplying circuit is inserted between the oscillation circuit 2 and the selector 7 of the second embodiment, and a case where the RC oscillation circuit 6 and the selector 7 The present invention can be similarly applied to a case where a frequency dividing circuit is inserted between the two.

In particular, when the output clock signal of the oscillation circuit 2 is converted into a clock signal of a higher frequency by the multiplying circuit, the oscillation stabilization time is further required, so that the present invention is extremely useful.

[0035]

As described above, the present invention relates to a semiconductor integrated circuit having a standby function.
By selecting the clock signal of the C oscillator and selecting the crystal oscillator after the oscillation stabilization time of the crystal oscillator has elapsed, the clock signal can be obtained immediately after the standby mode is released. Processing can be performed, and versatile functions can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a clock oscillator according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the same.

FIG. 3 is a circuit diagram showing an example of the RC oscillation circuit.

FIG. 4 is a timing chart of the RC oscillation circuit.

FIG. 5 is a block diagram showing a clock oscillator according to a second embodiment of the present invention.

FIG. 6 is a timing chart of the same.

FIG. 7 is a block diagram showing a conventional clock oscillator.

FIG. 8 is a timing chart of the same.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1: Crystal oscillator 2; Oscillation circuit which drives a crystal oscillator 3: Counter 4: RS-type flip-flop 5; AND gate 6; RC oscillation circuit 7; Selector 8; OR gate 11; Overflow signal of counter 3 13; output signal of RS flip-flop 4 14; internal clock signal 15; clock signal 16 of RC oscillation circuit 6; release signal 20; resistor 21; capacitor 22 to 24; inverter gate 25;

Claims (2)

(57) [Claims] A first STOP signal having a first logic level;
From the first clock to the second logic level
A crystal oscillation circuit for starting oscillation to output a signal;
When a first STOP signal changes from the second logic level to the second
Reset when the logic level changes to 1
RS set by release signal issued from
Type flip-flop and the output of the RS type flip-flop.
A second ST signal is input when the first stop signal and the first stop signal are input.
An OR gate for outputting an OP signal, and the second STOP
A signal from said first logic level to said second logic level
When the state changes to a stable oscillation,
An RC oscillation circuit that outputs a clock signal;
The clock signal and the second clock signal are input and the R signal
The output signal of the S-type flip-flop is the first logic level.
If the first clock signal is selected, the first clock signal is selected.
The output signal of the RS flip-flop is the second logic level.
If it is a bell, select the second clock signal and
Selector that outputs as internal clock signal of microcomputer
A clock oscillator, characterized in Rukoto with and. 2. The method according to claim 1, wherein the first STOP signal has a first logic level.
From the first clock to the second logic level
A crystal oscillation circuit for starting oscillation to output a signal;
A first STOP signal changes from the first logic level to the second
Reset when the logic level changes to 2,
When the number of counted one clock signal reaches a predetermined number
A counter that outputs an overflow signal when the
When a first STOP signal changes from the second logic level to the second
Reset when the logic level changes to 1.
RS flip set by bar flow signal
Flop and the output signal of the RS flip-flop and
The first STOP signal is input and the second STOP signal is
An output OR gate and the second STOP signal are
Changed from a first logic level to the second logic level
Occasionally, stable oscillation occurs and the second clock signal
An output RC oscillation circuit, the first clock signal,
The second clock signal is input and the RS type flip signal is input.
When the output signal of the flop is at the first logic level,
In this case, the first clock signal is selected, and the RS type free signal is selected.
The output signal of the flip-flop is at the second logic level
In this case , select the second clock signal and
Wherein the benzalkonium a selector for outputting as part clock signal and to torque-locked oscillator.