JPS6024432B2 - Electronic clock frequency adjustment device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a frequency adjustment device in an electronic timepiece.

Conventionally, the frequency adjustment of electronic watches that use a crystal oscillator as a time standard has been done by adjusting the constant of the feedback system of the oscillation circuit including the crystal oscillator as follows:
The oscillation frequency of the oscillation circuit was continuously adjusted by varying it with a trimmer capacitor.

However, the frequency adjustment using the trimmer capacitor has the following drawbacks.

'11 The frequency adjustment range cannot be widened because it is limited by the natural frequency f of the crystal resonator and the resonance sharpness Q.

'21 The trimmer capacitor is large in size and expensive, so it is not preferable as a wristwatch component in terms of space and cost.

'3' Using variable components with low stability as constants of the oscillation circuit may deteriorate the temperature characteristics and aging characteristics of the oscillation circuit.

Because of the above-mentioned drawbacks, so-called digital frequency adjustment has begun to be implemented in which the frequency division ratio of a frequency divider is varied by combining it with the conventional frequency adjustment using a trimmer capacitor or by combining it alone with an integrated circuit.

However, the currently used digital frequency adjustment method is
The frequency divider is equipped with either an addition circuit or a subtraction circuit as a frequency adjustment circuit, and the frequency of the crystal oscillator circuit is set to a value lower than a standard value (in the case of an addition circuit) in correspondence with the frequency adjustment circuit. This is a so-called unidirectional adjustment method in which the frequency of the crystal resonator is controlled to a high value (in the case of a subtraction circuit).In this method, the degree of freedom during the frequency adjustment process of the crystal resonator is reduced, and the change in the crystal resonator circuit over time is There was a drawback that accompanying frequency changes could not be adjusted. In view of the above, it is an object of the present invention to provide a frequency adjustment device for an electronic watch that can perform so-called bidirectional adjustment in which a predetermined frequency amount is increased or decreased in a frequency divider using a simple setting means. It is a further object of the present invention to provide a simple-structured and low-cost fin in which three types of adjustment states, ie, frequency increase, decrease, and no adjustment, can be set using a single frequency setting terminal. An object of the present invention is to provide a frequency adjustment device for a clock.

In order to achieve the above object, the present invention provides a frequency divider for an electronic timepiece that includes both a pulse addition circuit and a pulse subtraction circuit for varying the frequency division ratio, and each of the pulse addition circuit and pulse subtraction circuit is independent of the other. The device is characterized in that three operating states, operating and alternating, can be selected and set using a single frequency setting terminal.

Next, details of the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of the present invention.

1 is a standard oscillation circuit that uses a crystal oscillator as the time reference,
Oscillation is performed at a frequency of 215Hz.

2 is a waveform shaping inverter, which is connected to the standard oscillation circuit 1.
Perform waveform shaping on the oscillation waveform from.

3 is an addition gate.

4 is a subtraction gate.

5 is a frequency dividing circuit to which flip-flops (hereinafter referred to as FF) are connected in one stage.

6 and 7 are gates that determine the addition and subtraction cycles and timing, and the first output of the FF of the frequency dividing signal 5 is Q, 5.
and the output Q of the 1st building class. 6, a signal having a repetition period of 2 seconds and a pulse of 0.5 seconds is generated at the outputs of gates 6 and 7 at timings shifted by 1 second from each other.

8.1 is a data flip-flop (hereinafter referred to as DFF), and a gate 6 determines the cycle of addition and subtraction.
, 7 is input to the data terminal, and DFF8 uses cL in the output of the waveform shaping inverter 2 as a clock signal.
The data input signal of the FF 8 is delayed, and the gate 9 generates a one-shot signal using the delay time.

This one shot signal? By returning xB to the input of the subtraction gate 4, subtraction is performed by masking one cycle of the 215 day 2 signal. DFFIO is F of frequency divider circuit 5
The output Q, 3 of the 1st stage of F is used as the clock, and the DFFIO
A one-shot signal is generated at the gate 11, and this one-shot signal 0x^ is returned to the input of the addition gate 3, and one cycle of the 215Hz signal is added. That is, gates 6 and 11 and DFFIO constitute an addition control circuit that controls addition gate 3,
Alternatively, the gates 7 and 9 and OFF8 constitute a subtraction control circuit that controls the subtraction gate 4. m2 is a resistor, one end of which is connected to the outputs Q and 6 of the first stage of the FF of the frequency dividing circuit 5, and the other end of which is connected to the frequency setting terminal 13, and the setting signal of the setting terminal 13 is connected to the terminal. s is connected to one end of the input terminal of the gates 9 and 11. 14 is the frequency dividing circuit 5
The pulse motor drive circuit 15 is a time display device driven by a pulse motor.

The frequency setting terminal 13 is in an electrically open state (hereinafter referred to as "OP").
When the setting signal ◇s passes through the resistor 12 and becomes the output signal of the FFI signal 6 of the frequency divider circuit 5, this setting signal ? The waveform of s has a rounded rise and fall due to a time constant due to gate capacitance and wiring capacitance. Therefore, the one-shot signal described above must be created by removing the distorted portion of this waveform. Gates 6 and 7 receive signals Q and 5 with a period of 1 second, respectively.
This is why a 0.9 pulse signal is generated in the latter half of the period. Setting signal ◇s is at logic “1” level (′
H' level), one-shot signal is sent from gate 9◇
xB, and the setting signal s is at logic “0” level ('L
' level), one-shot signal is sent from gate 11.
Pass through ^. Therefore, the output Q of FF16 of frequency dividing circuit 5
, 6 is added and subtracted once each during one cycle, that is, 2 seconds, and the result is the same as without adjustment. Further, when the frequency setting terminal 13 is set to the ``H'' level, the setting signal ◇s is fixed to the ``H'' level, and therefore only the gate 9 is opened, so that only subtraction is performed. Furthermore, when frequency setting terminals 1 to 3 are set to 'L' level, the setting signal? Since s is fixed at the 'L' level and only gate 11 is opened, only addition is performed. As described above, depending on the state of the frequency setting terminal 13, three states can be set: addition, subtraction, and no adjustment. In this example, the overall operation was performed at a 2-second period, and addition and subtraction were performed alternately at a 1-second period, but addition and subtraction were performed alternately at a frequency of 2NHZ (n is an integer excluding negative integers). and subtraction. Although it is possible to perform the measurement with a cycle of 2 seconds or more, it is ideal to set the cycle to 2 seconds or less in relation to the rate measuring device. (Generally, rate measuring devices measure at a 2 second cycle.
) FIG. 2 is a time chart showing the waveforms of each part in FIG. 1, and shows each one-shot signal GxB and
Figure A shows the relationship between the input signal OB of the frequency divider and shows a state in which the frequency setting terminal 13 is "OPEN", and addition and subtraction are performed alternately.

Also, Figure B shows a state where the setting is at the day level, and only subtraction is performed.

Furthermore, diagram C shows the state set to 'L' level,
Only addition is performed. As described above, according to the present invention, the division ratio of the frequency divider can be set to three types of states, so the crystal resonator is selected in three stages according to its natural frequency, and the crystal resonator at each stage is By roughly matching the set dividing ratio of the frequency divider, it becomes possible to mass-produce electronic watches with averaged accuracy.

Further, the integrated circuit is provided with settings for the three types of frequency division ratios,
Since this can be done using only one frequency setting terminal, the number of external terminals of the integrated circuit can be reduced, thereby reducing the cost and improving the reliability of the integrated circuit.

Further, by increasing the number of frequency setting terminals shown in this embodiment and varying the calculation repetition period for each terminal, even finer frequency adjustment becomes possible.

[Brief explanation of drawings]

FIG. 1 is a wiring diagram of an electronic timepiece according to the present invention. FIG. 2 is a time chart showing waveforms at various parts in FIG. 1
...Standard oscillator, 3 ... Addition gate, 4 ... Subtraction gate, 5 ... Frequency divider circuit, 12 ... Resistor 13... Frequency setting terminal, 15... Time display device. Figure 1 Figure 2

Claims (1)

[Claims] 1. In an electronic watch having a standard oscillator, a frequency divider, and a time display device, a pulse addition circuit, a pulse subtraction circuit, and the addition circuit and subtraction circuit for varying the frequency division ratio of the frequency divider. Two control circuits each operating at different logic levels for controlling the respective circuits, and one frequency setting terminal commonly connected to these two control circuits are provided, and the frequency setting terminal is connected to an impedance element. A frequency adjustment device for an electronic timepiece, which is connected to a signal source whose logic level changes periodically through a power supply terminal, and is configured to be selectively connectable to two logic levels of a power supply terminal.