JPS5972233A - Oscillation frequency adjusting circuit - Google Patents

Abstract

PURPOSE:To utilize a time-casting signal for the automatic setting of data on the amount of adjustment by counting a reference oscillation frequency by a gate signal, and setting the frequency division ratio of a frequency dividing circuit on the basis of the counted value. CONSTITUTION:When the time-casting signal by the time casting of a radio, etc., is inputted as a reference signal to an input terminal 16, an input detecting circuit 15 outputs a gate signal with accurate time width on the basis of the time- casting signal. When the gate signal is supplied to the input detecting circuit 15, a counting circuit 14 counts a signal from an oscillation circuit 11. The sampling signal 17 obtained by dividing the oscillation frequency of the oscillation circuit 11 by a frequency dividing circuit 12 is inputted to a frequency adjusting circuit 13. The frequency adjusting circuit 13 samples the count data of the counting circuit by the sampling signal 17 and controls the frequency division ratio of the frequency dividing circuit according to the data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital frequency adjustment circuit for an electronic timepiece.

Conventionally, the oscillation circuit of an integrated circuit for an electronic watch uses a parallel resonant oscillation circuit consisting of one CMOS inverter as an amplifier, two external capacitors, and a π-type crystal oscillator circuit. The oscillation frequency of this circuit is adjusted by varying one of the capacitors. In recent years, external parts (
In order to reduce the number of capacitors (capacitors), a configuration is used in which the fixed capacitance of the two capacitors is built into the integrated circuit, but a configuration in which the variable capacitor is also built in as a fixed capacitance is now being used. It's here.

If these two capacitors are built-in, the oscillation frequency itself cannot be adjusted, so the frequency adjustment is done every certain period (for example, 10 seconds) using some 1/2 of the frequency dividing circuit.
Digital frequency adjustment is used to digitally adjust the period of the signal obtained by the frequency divider circuit by setting or resetting the frequency divider circuit.

FIG. 1 is a main block diagram of an example of a conventional digital frequency adjustment circuit. The 32768 Hz output signal of the clock oscillator circuit 1 is connected to the clock input of the 1/2 frequency divider circuit 2, and the output of this 1/2 frequency divider circuit 2 is sequentially connected to the 1/2 frequency divider circuit 3.
+ 4 + 5.6, the output of the 1/2 frequency divider 6 is connected to the clock input of the 1/2 frequency divider 7 through the entire gate circuit 8, and the output of the 1/2 frequency divider 7 is Connected to the next stage clock input. The frequency adjustment circuit 9 inputs data inputs and sampling signals from input terminals T and -T5, and takes out five outputs corresponding to these five data inputs. The outputs corresponding to the data inputs connected to the input terminals T1 to T4 are connected to the set inputs of the 1/2 frequency divider circuits 3 to 6, and the outputs corresponding to the data inputs connected to the input terminal T5 are connected to the set inputs of the gate circuit 8. connected to the control input. The 1/2 frequency divider circuit in this configuration changes its output at the falling edge of the clock input. Further, the sampling signal 10 is formed at the falling edge of the 10 second signal, and this 10 second signal is output from the oscillation circuit 1 by the 1/2 frequency divider circuits 2 to 7 and the subsequent frequency divider circuits.
It is obtained by dividing the frequency by /327680.

The frequency adjustment circuit 9 is a gate circuit controlled by the sampling signal 10, and when the sampling signal 10 is input, it samples the data of the input terminals Tl~]゛5,
When input terminals T1 to T4 are at high level, input terminal Tl
-Output a set signal to the output corresponding to the connected input of T4, and set each output of 172 frequency divider circuits 3 to 6 to High.
Set to h level, but input terminal T! When T4 is at low level, no set signal is output. 1/2 of these
When the frequency divider circuits 3 to 6 are set, the period of the 10 second signal that is equivalent to counting 2, 4, 8, and 16 output pulses of the oscillation circuit 1 is set by the frequency divider circuit. (3,1°12.2,
24.4, 48.8 ppm shorter, oscillation circuit 1
This is equivalent to adjusting the oscillation frequency to the higher side. Further, when the input terminal T5 is at a high level, a gate control signal is outputted to the output corresponding to the connected input of the input terminal T5, but when it is at a low level, this signal is not outputted. When this gate control signal is output, the gate circuit 8 outputs the output pulse ' of the 1/2 frequency divider circuit 6.
The second and subsequent pulses are input to the clock input of the 172 frequency divider circuit 7 without outputting one pulse. As a result, in order to obtain a 10-second signal, an additional 32 output pulses from the oscillation circuit 1 must be counted, and the resulting 10-second signal is 97.
It will be delayed by 6 pI)m.

In this way, the frequency finally obtained can be adjusted by combining the data of the input terminals T1 to T5, but in this case, the input terminal T! for setting the frequency adjustment amount data! - T8 is required, which has the drawback of increasing the number of terminals of the integrated circuit, and it is also inconvenient to set the adjustment amount data.

SUMMARY OF THE INVENTION An object of the present invention is to provide an oscillation frequency adjustment circuit which is easy to use and which eliminates the conventional drawback of increasing the number of terminals, and also allows automatic setting of adjustment amount data simply by using a time signal. be.

The configuration of the oscillation frequency adjustment circuit of the present invention includes an oscillation circuit that oscillates a reference frequency, a division circuit that divides the reference frequency r of this oscillation circuit according to a specified frequency division ratio, and a predetermined reference time signal that is inputted to accurately adjust the frequency. a gate signal generating circuit that generates a gate signal having a time width; a counting circuit that counts the reference oscillation frequency using the gate signal and holds the counted value; and a circuit for controlling the divided frequency by specifying a frequency division ratio, and the output frequency of the frequency division circuit is adjusted to a reference value by controlling the frequency division ratio.

The present invention will be explained in detail below with reference to the drawings.

FIG. 2 is a block diagram of a main suction circuit according to an embodiment of the present invention.

This embodiment includes an oscillation circuit 11, a frequency division circuit 12 that divides the frequency of a signal from this oscillation circuit 11, and this frequency division circuit 12.
Frequency adjustment circuit 1 that controls and adjusts the entire output frequency
3, F of this frequency adjustment circuit 13, 14 a 5-bit counting circuit that counts the signal from the oscillation circuit 11 in order to set the rectified data, and a counting circuit that detects the time signal input from the input terminal 16. The input detection circuit (gate signal generation circuit) 15 outputs 14 gate signals.

The operation of this embodiment will be explained below.

The excavation frequency of the oscillation circuit 11 is approximately 32768 Hz, and the frequency is divided by 1/98304 in the frequency dividing circuit 12 to obtain a 3 second signal, which is inputted to the frequency adjustment circuit 13 as the sampling signal 17. Note that an output of a predetermined frequency division ratio is outputted from the terminal 18 as a clock divisor signal. This frequency adjustment circuit 13 controls the counting circuit 1 by the sampling signal 17.
4 count data is sampled and the frequency dividing circuit 12 is controlled according to this data. The operations of the frequency adjustment circuit 13 and the frequency dividing circuit 12 are the same when the argument data of the counting circuit 14 is replaced with the input terminal data of the conventional example, so the explanation will be omitted. However, in this embodiment, a 3-second signal is used as the sampling signal, and since the 1z2 frequency divider circuit for adjustment is a total of four stages, the accuracy of the frequency adjustment amount is 10.1 ppm. Note that in the conventional example, since the frequency dividing circuits of 2 to 5 stages are adjusted using a sampling signal of 10 seconds, the adjustment accuracy is aippm.

When a reference time signal from a radio (TV) or the like is input to the input terminal 16, the input detection circuit 15 outputs an accurate three-second gate signal based on this time signal. This circuit operates to open the gate 14 at the rising edge of the input sound of the time signal, and reset the gate at the fourth rising edge of the time signal. This 3-second gate signal is based on a time signal as a signal with accurate 1-second intervals, so it is an accurate 3-second gate signal. This gate signal is the input detection circuit 1
5, the counting circuit 14 counts the Gj signal from the oscillation circuit 11. If the oscillation frequency of the oscillation circuit 11 is exactly 32768)-1z, the count value of the counting circuit 14 will be 0, but if the oscillation frequency is advanced, the count value of the argument circuit 14 will be an advanced value. becomes. For example, if the oscillation frequency is 32769Hz, the count value is 3 (oo
In order to make the frequency of the signal obtained by the 15 frequency divider circuit 12 which is ott ) accurate, the frequency divider circuit 12 may be corrected to the delayed side by the frequency adjustment circuit 13 by a number equal to this count value. Further, when the oscillation frequency is delayed, the count value of the counting circuit 14 becomes a delayed value. For example, if the oscillation frequency is 32767 Hz, the count value is 29 (11101). In this case, the frequency dividing circuit 12 may be corrected to the leading side by the amount of this delay.

In this way, since there is a one-to-one correspondence between the adjustment amount and the count value,
As the adjustment amount data, it is sufficient to simply use an inverted signal of each bit of the count value. However, if the initial value of the counting circuit 14 is O, the frequency adjustment amount will always be one count ahead of the count value when the inverted signal is used as adjustment amount data as described above. Before starting counting, all pits must be set to 1.

If all bits are set to 1 in advance like this, it is equivalent to subtracting 1 count from the count value,
Accurate adjustment amount data can be obtained. Further, when the output of the 3-second gate signal stops, the counting circuit 14 stops counting and holds the value for that day, and thereafter, the inverted signal of the counted value is sampled as the adjustment amount data of the frequency adjustment circuit 13 by the sampling signal 17, and this Based on the data, normal frequency adjustment operations are performed.

In this embodiment, a 3-second signal having the same period as the gate signal was used as the sampling signal 17, but a 6-second signal obtained by frequency-dividing the signal of the oscillation circuit 11 by 1/196008 was used as the sampling signal 17, and the counting circuit By setting the signal counted in step 14 to be one obtained by multiplying the frequency of the signal from the oscillation circuit 11 by #y'c2, the frequency adjustment accuracy can be increased to 5. lpp
m. .

In this case as well, the method of setting the frequency adjustment amount data is the same.

Also, the frequency f obtained by the oscillation circuit is approximately 32768H
z, but it is possible to select this oscillation frequency to a higher frequency, and the counting time of the L number circuit 14 (that is, the period of the gate signal) and the sampling signal 17
As long as the period (the period obtained in minutes when the oscillation frequency is accurate) is in an equal relationship, the adjustment amount setting operation will be the same.

As explained above, according to the present invention, setting of digital frequency adjustment amount data is automatically performed by simply inputting a time signal, and is therefore very easy. In contrast, only one terminal for inputting the time signal is required, making it possible to realize an easy-to-use integrated circuit with a small number of terminals. Furthermore, since the conventional frequency adjustment amount was fixed, it was not possible to compensate for changes caused by differences in the usage environment (temperature), but according to the present invention, the adjustment amount data can be changed freely. There is also the advantage that an appropriate amount of adjustment can always be obtained.

[Brief explanation of drawings]

FIG. 1 is a main circuit block diagram of a conventional digital frequency adjustment circuit, and FIG. 2 is a main circuit block diagram of an embodiment of the present invention. In the figure

Claims (1)

[Claims] An oscillation circuit that oscillates a reference frequency, a frequency divider circuit that divides the reference frequency of this oscillation circuit according to a specified frequency division ratio, and a gate signal that inputs a predetermined reference time signal and creates a gate signal with an accurate time width. a generator circuit, a counting circuit that counts the reference oscillation frequency according to the gate signal and holds its argument value, and controls the divided frequency by specifying a division ratio of the frequency dividing circuit based on the counting output of the counting circuit. An oscillation frequency adjustment circuit, comprising: a frequency adjustment circuit, the output frequency of the frequency division circuit being adjusted to a reference value by controlling the frequency division ratio.