JPS58156879A - Integrated circuit - Google Patents

Abstract

PURPOSE:To adjust the frequency of an LSI for electronic timepieces easily without increasing the number of terminals, by storing the frequency adjusting quantity on the basis of the counting of the reference signals wherein the output of a frequency dividing circuit dividing down the oscillated output is used as a gate period and controlling the frequency dividing circuit. CONSTITUTION:The output of a frequency dividing circuit 12 acts as a gate signal, and the external reference signals applied from a terminal 16 are counted with a counter circuit 15. The frequency adjusting quantity corresponding to the advance and delay is set and stored in a storage circuit 14 according to the difference between the external reference signal and the frequency of the signal oscillated by an oscillating circuit 11. The circuit 12 is controlled with a frequency adjusting circuit 13 on the basis of the stored contents, and the frequency of an LSI for electronic timepieces is adjusted. The frequency of the LSI for electronic timepieces is adjusted easily without increasing the number of terminals by the constitution of applying only the reference frequency signal from the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit, particularly a digital frequency adjustment circuit for an oscillation circuit for an electronic watch.

Conventionally, the oscillation circuit of an integrated circuit for electronic watches is a parallel circuit consisting of one CMOS inverter 50°, two external capacitors 51 and 52, and a π-type crystal oscillator 53, as shown in FIG. A resonant oscillation circuit is used. The oscillation frequency can be adjusted using one of the two capacitors 51 and 52.
This is done by making it variable.

In recent years, in order to reduce the number of external components, it has become common practice to incorporate the fixed capacitor 52 of the capacitors into the output circuit, but in addition, the variable capacitor 51 is also incorporated as a fixed capacitor. This method has come to be used. When two capacitors 51 and 52 are both built-in,
Since it is impossible to adjust the oscillation frequency itself, the frequency adjustment is done by setting several 1/2 frequency divider circuits of the frequency divider circuit at certain intervals (for example, 10 seconds) or resetting them. By doing this, a digital frequency adjustment method is used in which the period of the signal obtained by the frequency dividing circuit is digitally adjusted.

FIG. 2 is a main circuit block diagram of an example of a conventional digital frequency adjustment circuit. The output of the oscillation circuit 1 (all components except the crystal oscillator 53 in the first part are integrated circuits) is 32
, 768Hz (D signal, connected to the clock input of 1/2 frequency divider 2, and the outputs of 1/2 frequency divider 2, 3, 4.5 are 1/2 frequency divider 3゜4.5, respectively. The output of the 172 frequency divider circuit 6 is connected to the clock input of the 1/2 frequency divider circuit 7 through the gate circuit 8, and the output of the 1/2 frequency divider circuit 7 is connected to the clock input of the 1/2 frequency divider circuit 7. The frequency-alignment node 9 is configured with five data inputs, a sampling input, and five outputs corresponding to the five data inputs in a one-to-l ratio; The five data inputs are respectively connected to the input terminals 1'1 to T5, and the outputs corresponding to the data inputs connected to the input terminals T1 to T4 are connected to the set inputs of the 1/2 frequency divider circuits 3 to 6. , the output corresponding to the data input connected to the input terminal T5 is connected to the control input of the gate circuit 8.The l/2 frequency divider circuits 2 to 7 in this example The output changes.Also, the 10 second signal changes to 1/2
The output from the oscillation circuit 1 is divided by 1/32768 by the frequency dividing circuits 2 to 7 and subsequent frequency dividing circuits, and at the falling edge of this 10 seconds signal, the sampling signal 10 is sent to the frequency adjustment circuit 9. is input. When the sampling signal 10 is inputted, the frequency adjustment circuit 9 samples the data of the input terminals 1'1 to T5, and when the input terminals T1 to T4 are at the 7.
Output a node signal to the output corresponding to the connected input of 4, and tune the outputs of 1/2 frequency divider circuits 3 to 6.
g Set to h level. Input terminal 'i' 1,
When 'r4 is low level, no set signal is output. In this way, when the 1/2 frequency divider circuits 3 to 6 are set, it is equivalent to canting the output pulses of the oscillation circuit 1 by 2, 4.8, and 16, respectively, and the resulting 10-second signal is: 6 and 1, respectively, compared to when the frequency divider circuit is set.
, 12°2.24.4.48.8 ppm. When input terminal T5 is at high level, input terminal T5
A gate control signal is output to the output corresponding to the connected input, but this signal is not output when it is at low level. When the gate control signal is output, the gate circuit 8 drops one output pulse of the 1/2 frequency divider circuit 6 and inputs the second and subsequent pulses to the clock input of the 1/2 frequency divider circuit 7. As a result, in order to obtain a 10-second signal, it is necessary to count the output pulses of the oscillation circuit 1 into 32 parts, and the obtained 10-second signal is 97.6
I'm disappointed in the delay by only ppm.

In this way, the finally obtained frequency can be adjusted by combining the data of the input terminals 'I' and -T5. However, in this case, input terminals Tl to T5 for setting the frequency adjustment amount data are required, which has the disadvantage of increasing the number of terminals of the integrated circuit.

Furthermore, setting the PL adjustment data was also inconvenient.

The present invention provides an easy-to-use integrated circuit for an electronic timepiece using a technical frequency adjustment method, which eliminates the drawback of an increase in the number of terminals described above and also facilitates the setting of adjustment amount data.

, FIG. 3 is a schematic diagram of the main circuit of the embodiment according to the present invention. This embodiment includes an oscillation circuit 11 (incorporating capacitors 51 and 52 in FIG. 1 as an integrated circuit),
A frequency dividing circuit 12 that divides the signal from this oscillation circuit 11;
A frequency adjustment circuit 13 that controls the frequency dividing circuit 12 to adjust the frequency of the signal obtained by the dividing circuit 12;
A storage circuit 14 that stores adjustment amount data of the frequency adjustment circuit 13, a counting circuit 15 that counts reference signals input from the outside, and control that controls the operations of the frequency adjustment circuit 13, storage circuit 14, and counting circuit 5. The circuit 17 is configured to include a circuit 17. 113 control circuit 17 includes frequency dividing circuit 1
2 and a control signal 19 for the purpose of setting the frequency adjustment g- are input.

The operation will be explained below using FIG.

Oscillation times j! ? The oscillation frequency of ill is tl 32.76
It is 8Hz, and it is 1/327680 with frequency divider circuit 12.
The frequency is divided and the timing signal 1B (10 second signal) is replaced. Normally, the control circuit 17 outputs the sampling signal 6-- to the frequency adjustment circuit 13 in response to the timing signal 18. The frequency adjustment circuit 13 samples the data in the memory circuit 1814 using the sampling signal, and controls the frequency dividing circuit 12 according to this data.

The operations of the frequency adjustment circuit 13 and the frequency division circuit 12 are the same if the data in the storage circuit 14 is replaced with the input terminal data in the conventional example, so a description thereof will be omitted.

Next, the frequency adjustment amount setting operation will be explained.

A calibrated reference signal (in this example, 327
68Hz) and frequency adjustment i# setting control signal 19
Input one candy into one circuit. This reference signal is generated using the trigger source in the row section. 17 control circuits 1 control circuit
9 is being input, the sampling signal output to the frequency adjustment circuit 13 is stopped, a gate signal synchronized with the timing signal 1B is output to the argument circuit 15, and a compliment signal is output to the memory circuit 14. During this time, frequency! IA
Since the I adjustment circuit 13 does not operate, the timing signal 18 becomes an iiMI adjustment signal. The counting circuit 5 counts the reference signal from the outside using a gate signal synchronized with the timing signal 18. If the oscillation frequency is the same as the external quasi-signal (Z), and the count value of the counting circuit is O, the 42 oscillation frequency number is ahead of the reference signal, then the timing signal 18 is short, and the count value of the counting circuit 15 becomes a delayed value.

In order to make the timing signal @18 accurate, it is better to correct the frequency divider circuit 12 to the delay side by the delay of the counting circuit 15. Conversely, if the oscillation frequency is delayed compared to the reference signal, the timing signal 18 will be longer and the timing signal 18 will be longer.
The argument value of 5 is the advanced value. In this case, it is sufficient to correct the frequency dividing circuit 12 to the lead value by this lead force. Now, if we use the external reference signal counted by the argument circuit 15 using the gate signal synchronized with the timing signal 18 as the adjustment f data of the frequency adjustment circuit 13, we can obtain a single frequency-divided signal. Become. When the division is completed, the count value is stored in the memory circuit 14, and if the input of the edge control signal 19 and the reference signal is stopped, the normal operation is performed based on the data in the memory circuit 14 as described above. Performs frequency adjustment operation.

As explained above, according to the present invention, setting of frequency adjustment amount data when using the digital frequency adjustment method is as follows:
It is very easy to just input the calibrated reference frequency, and unlike conventional methods that required several input terminals, there is only one terminal for inputting the reference frequency (control signal 9 is connected to the terminal). However, if it is controlled externally, only one more wire is required, making it possible to realize an easy-to-use integrated circuit with a small number of terminals.

In the above description, the reference signal is the same as the oscillation frequency, but it is also possible to set the timing signal at the time of setting the adjustment amount as a signal obtained by dividing the oscillation frequency by 17163840, so that the reference signal is 65536 Hz. In this case, the frequency adjustment amount setting time can be shortened. In addition, although the timing signal was explained as a signal obtained by dividing the oscillation frequency by 1/327680, this is a signal obtained by dividing the oscillation frequency by 1/327680.
It is possible to arbitrarily select one in consideration of adjustment accuracy and the like.

If the memory circuit of the present invention is configured with RAM, flip-flops, etc., the data will not be retained when the power is turned off (when replacing the battery), and it will be necessary to set the frequency adjustment amount again. This drawback can easily be overcome by temporarily backing up the power supply with a capacitor or the like, or by using a writable ROM as the storage circuit. Furthermore, apart from the frequency adjustment amount setting operation, it is also possible to change the data in the memory circuit by external operation, and in this case, it is possible to finely correct changes in frequency due to differences in usage environment. .

[Brief explanation of the drawing]

FIG. 1 is a main circuit block diagram of a crystal oscillation circuit, FIG. 2 is a main circuit block diagram of a conventional digital frequency adjustment circuit, and FIG. 3 is a main circuit block diagram of an embodiment of the present invention. 1...Oscillation circuit, 2, 3, 4, 5, 6.7...
Song/1/2 frequency divider circuit, 8...D~flip-flop, 9...frequency tAl adjustment circuit, 10...
...sampling signal, T1. T2. T3. T4,
'I'! 5... Input terminal, 11... Oscillation circuit, 12... Frequency dividing circuit, 13...
Frequency adjustment circuit, 14... Memory circuit, 15...
...Counting circuit, 16...Input terminal, 17.
... Control circuit, 18 ... Timing signal, 19 ... Control signal. -11- T'y/ Closed Figure 2

Claims (1)

[Claims] An oscillation circuit for obtaining a reference frequency signal, a frequency division circuit for dividing the frequency of the reference frequency signal, and a frequency adjustment circuit for adjusting the frequency obtained by the frequency division circuit according to input frequency adjustment amount data. a frequency adjustment circuit that controls a frequency dividing circuit; a counting circuit that counts an external reference signal using the signal obtained by the frequency dividing circuit as a gate signal; 1. An integrated circuit comprising a memory circuit for holding data.