JPH0352590B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention aims at increasing the precision of electronic timepieces, and relates to improvements to timepieces that maintain their accuracy over a long period of time.

Conventionally, electronic clocks using crystal oscillators have relatively high accuracy, with a monthly error of a few seconds and an annual error of several tens of seconds.
Approximately seconds are available.

However, it has been difficult to improve the accuracy to within 1 second for annual errors in electronic clocks with limited space.

The reason for this is that the XY type crystal resonator, which is popular for watches, is used as a bent tuning fork resonator, and the XY type crystal resonator, which is popular for watches, is used as a bent tuning fork resonator.
The following factors can be cited when using thickness shear vibration of an AT cut crystal resonator.

XY type 32kHz crystal resonators have quadratic frequency-temperature characteristics with very little variation, so by adding a temperature compensation function, the temperature characteristics can be made good over a relatively wide temperature range. However, it has been difficult to improve the long-term aging characteristics of the vibrator from the standpoint of achieving ultra-high precision due to its vibration mode, support, etc.

AT cut's MHz band crystal resonator has extremely high stability due to its vibration mode and high oscillation frequency, but its frequency-temperature characteristics are expressed almost as a cubic curve. There is a large variation due to cut angle errors, etc., and it is difficult to make the cut flat over the operating temperature range. Also, temperature compensation is difficult because it is a cubic curve.

As mentioned above, the AT crystal oscillator and the XY crystal oscillator each have their own advantages and disadvantages, so if you choose one of the above crystal oscillators, the AT crystal oscillator will determine the accuracy that the clock can achieve. Even when the best ones were selected, the annual error was limited to a few seconds.

The present invention eliminates the above drawbacks and maintains high accuracy over a long period of time by using an XY crystal oscillator with temperature compensation capacity as the time reference oscillation source and an AT crystal oscillator as the aging error correction reference oscillation source. The purpose is to provide electronic clocks.

Specifically, we use an XY crystal oscillator to perform temperature compensation for temperature fluctuations in the clock, absorbing clock errors caused by temperature, and reducing the aging of the XY crystal oscillator, which changes over time. Regarding the error, the above XY is calculated using the value only in a specific temperature range (24 to 25℃ as an example) in the flat region of the cubic curve that shows the temperature characteristics of the AT crystal resonator, which has excellent long-term stability. By calibrating the crystal oscillator, we aim to eliminate most of the factors that cause errors in clocks.

Next, the outline of the operation of the electronic timepiece according to the present invention will be explained with reference to the block diagram of the electronic timepiece shown in FIG.

In the figure, 1 is a low frequency oscillation circuit that has an XY crystal oscillator and generates a reference signal, 2 is a correction device that corrects the output frequency of the low frequency oscillation circuit 1, and 3 is a frequency dividing circuit 31 and a display drive circuit. 32, etc., 4 is a temperature detection device including a temperature sensor, 5 is a time display block, 6 is a high frequency oscillation circuit that has an AT crystal oscillator and generates a calibration signal, 7 is the high frequency An oscillation control circuit 8 controls the oscillation operation of the oscillation circuit 6, and a comparison circuit 8 compares the output frequencies of the low frequency oscillation circuit 1 and the high frequency oscillation circuit 6.

The operation of the electronic timepiece with the above configuration will be explained by dividing it into three operations.

The first operation is the normal operation of the electronic watch, in which the signal from the low frequency oscillation circuit 1 is applied to the clock circuit block 3 including the frequency divider circuit 31 and the display drive circuit 32 through the correction device 2, and the time display block is It is designed to drive 5.

The second operation is an aging correction operation, in which the temperature detection device 4 sends a signal to the oscillation control circuit 7 and the comparison circuit 8 when it detects a specific temperature, for example, 24°C to 25°C. The comparator circuit 8 measures the frequency difference between the high frequency oscillation circuit 6 and the low frequency oscillation circuit 1 to create aging error information, and the correction device 2 uses this aging error information. The signal of the low frequency oscillation circuit 1 is corrected by receiving the signal.

The third operation is a temperature correction operation, in which temperature information is directly sent from the temperature detection device 4 to the correction device 2, and the correction device 2 uses this temperature information to correct the temperature of the low frequency oscillation circuit 1. There is.

Due to the above three operations, the correction device 2 has two functions. That is, there is a function that receives aging error information and performs the same amount of correction over the entire temperature range, and a function that receives temperature information and adjusts the temperature to flatten the quadratic frequency-temperature characteristic of the low frequency oscillation circuit 1. This is a function that performs different corrections for each. In the following, the former will be referred to as an aging correction function, and the latter will be referred to as a temperature correction function.

FIG. 2 is a characteristic diagram showing the temperature characteristics due to the above-mentioned operation. The horizontal axis represents the temperature θ (°C), and the vertical axis represents the frequency deviation ppm.

f ₁ indicates the temperature characteristic of the high frequency oscillation circuit 6, and has an undulation that can be called a substantially cubic curve.
As mentioned above, this temperature-related waviness cannot be easily removed, making it difficult to use even an AT crystal resonator as an absolute reference oscillation source. Therefore, the present invention provides a temperature range of 24° C. to 25° C. that is preset in a flat region of a cubic curve f ₁ showing the temperature characteristics of the high frequency oscillation circuit 6 as shown in the figure.
By referring only to degrees Celsius, we were able to ignore this undulation. Note that, since the high frequency oscillation circuit 6 operates only at the specific temperature, frequencies at other temperatures are shown for reference.

f ₄ indicates the frequency temperature characteristic of the low frequency oscillation circuit 1, and is a quadratic curve having an apex near room temperature.

f ₂ is the temperature characteristic curve that has been corrected by the temperature correction function and has a small error over a wide temperature range, and f ₃ is the frequency temperature when the aging error occurs and a delay occurs. The characteristic curve is shown, and the difference f ₂ −f ₃ between f ₂ and f ₃ is the aging error to be corrected. Therefore, the aging information sent from the comparison circuit 8 to the correction device 2 of the present invention is nothing but this f ₂ −f ₃ .

Therefore, the comparison circuit 8 has two functions. That is, there is a function to store f ₁ - _{f 2} as initial data with zero aging error in advance, and a function to store f 1 − f 2 as initial data with zero aging error, and when an operation command for the temperature detection device 4 is received.
The aging error f ₂ to be corrected by measuring f ₁ − f ₃
-f This function calculates ₃ . In the following, the former will be referred to as the initial data storage function and the latter as the modified data determining function.

In this way, since the comparator circuit 8 is equipped with an initial data storage function and a correction data determining function, the aging error correction, which could not be achieved with the low frequency oscillation circuit 1 alone, can be performed using the oscillation frequency of the high frequency oscillation circuit 6 at a specific temperature as an absolute reference. This became possible by doing this.

Before entering into a description of a specific example, an explanation will be added regarding the correction device 2 in FIG. 1.

In FIG. 1, the oscillation signal of the low frequency oscillation circuit 1 is frequency-divided by the frequency divider circuit 31, and a time reference signal f _S for a clock is generated.
A correction device 2 for correcting the time reference signal f _S is inserted in the oscillation/frequency division/display system of a standard electronic watch that displays the time based on this signal. When viewed as an electronic timepiece, the correction device 2 only needs to correct the time reference signal f _S for the timepiece, and in practice, the correction means is selected from this point of view. The main types of correction means include means that directly control the oscillation frequency, such as using a voltage-controlled oscillation circuit, and means that control the oscillation capacitance, and methods that make the frequency division ratio variable, such as pulse interrupt means for the frequency divider circuit. and so on.

The embodiment described next adopts as a correction means a means for switching the oscillation capacitor, which is one of the oscillation capacitor control means for directly controlling the oscillation frequency, in a time division manner and controlling the average oscillation frequency using this time division ratio. ing.

FIG. 3 is a circuit diagram showing a specific configuration of the electronic timepiece shown in FIG. 1, and FIGS. 4 and 8 are circuit diagrams of main parts of the electronic timepiece shown in FIG. The first operation, second operation, and third operation will be explained with reference to FIG. 4 and FIG. 8, respectively.

FIG. 3 is a circuit diagram of an electronic timepiece specifically showing the low frequency oscillation circuit 1 and correction device 2 in FIG. 1. In the figure, a low frequency oscillation circuit 1 and a correction device 2 together constitute a reference signal generation device 9. In the reference signal generator 9, the low frequency oscillation circuit 1 is a basic CMOS oscillation circuit, and is composed of a feedback resistor 11, an oscillation inverter 12, a crystal oscillator 13, an input side capacitor 14, and an output side capacitor 15. Outputs an oscillation signal _fL .

Note that the output signal obtained only from this basic configuration is referred to as a reference signal _fB . The correction device 2 includes an aging correction circuit 21 which is supplied with the aging information signal _S8 from the comparator circuit 8 and outputs an aging correction signal _SA ;
A temperature correction circuit 22 which is supplied with the temperature information signal S ₄ from the temperature detection device 4 and outputs a temperature correction signal _ST ; and an oscillation frequency control circuit 23 which uses the aging correction signal S _A and the temperature correction signal _ST as control input signals. ,24
Consisted of.

Note that the oscillation frequency control circuits 23 and 24 and the correction circuits 21 and 22 constitute first and second correction means. The oscillation frequency control circuits 23 and 24 have switching capacitors 232 and 242 arranged in parallel with the input side capacitor 14 and the output side capacitor 15, respectively, which are the oscillation capacitors of the low frequency oscillation circuit 1, and provide aging correction signals S _A and 242, respectively. Temperature correction signal S _T
is a control input signal, and when the logic of this signal is "0", a switching capacitance is added to the oscillation capacitance to lower the frequency of the low frequency oscillation signal f _L , respectively.

The first operation in the above configuration will be explained. Now, let us calculate the percentage of time when the aging correction signal S _A and the temperature correction signal S _T take logic “1”, respectively.
Let _A and _T be the aging correction factor and temperature correction factor, and let the difference between the low frequency oscillation frequency f _L of =1 and =0 for both correction factors be f _SWA and f _SWT , respectively. In the CMOS crystal oscillator circuit of this example, f _SWA and
The frequency shift due to _A and the frequency shift due to f _SWT and _T work independently, and since _A , _T and the frequency shift due to _A , _T can be considered linear, the low frequency oscillation frequency f _L is the average frequency and is calculated using the following formula: It is expressed as

f _L = f _B - f _SWA × (1- _A ) - f _SWT × (1- _T ) ...(1) In other words, the aging correction term - f _SWA × (1- _A ) is added to the reference low-frequency oscillation frequency f _B. Temperature correction term −f _SWT ×
A low frequency oscillation frequency f _L obtained by adding (1- _T ) will be realized.

FIG. 4 is a circuit diagram of main parts showing specific configurations of the temperature detection device 4, high frequency oscillation circuit 6, oscillation control circuit 7, comparison circuit 8, and aging correction circuit 21 in FIG.

FIG. 4 will be explained with reference to the voltage waveform diagrams of FIGS. 5, 6, and 7.

In the temperature detection device 4, 41 is a temperature information signal
It is a temperature detection circuit equipped with a temperature register 40 that outputs _S4 , and this temperature information signal _S4 is _T0 , _T1 ,...
... Consists of 9 bits of _T8 and represents the temperature information value T shown by the following equation.

T=T ₀ ×2 ⁰ +T ₁ ×2 ¹ +……T ₈ ×2 ⁸ …(2) The contents of the temperature detection circuit 41 will be described later, but this temperature information value T is proportional to the temperature. be.

42 denotes T ₃ , _{T 4 ,}
Exclusive- which inputs T ₅ , T ₆ and ₇ and outputs logic “1” only when all input signals have the same logic value.
NOR (hereinafter abbreviated as EXNOR) circuit 421 and this
The output signal of the EXNOR circuit 421 and a signal obtained by inverting _T8 of the temperature information signal _S4 by an inverter 422 are inputted, and a specific temperature condition signal _S42 is output.
This is a specific temperature detection circuit consisting of an AND circuit 423.

43 is a well-known set-reset type flip-flop (hereinafter abbreviated as RSFF) consisting of two NOR circuits, the set input terminal S is supplied with a synchronous 4-hour signal _φ4h , and the reset input terminal R is supplied with an oscillation timing signal, which will be described later. _S45 is supplied, and the comparison time condition signal _S43 is output from the output terminal Q.

In this application, when a signal obtained by frequency-dividing the low-frequency oscillation signal f _L is used as a synchronization signal, the symbol φ is expressed with an approximate value of its frequency or period (s is added for seconds, and h is added for hours).

44 is an AND circuit which inputs the specific temperature condition signal S ₄₂ from the specific temperature detection circuit 42, and
Input the comparison time condition signal _S43 from RSFF43,
A comparison condition signal _S44 is output.

45 is RSFF, the set input terminal S is supplied with the comparison condition signal _S44 , the reset input terminal R is supplied with the synchronous 64 second signal _φ645 , and the output terminal Q
The oscillation timing signal _S45 is output.

46 is an AND circuit which inputs this oscillation timing signal S ₄₅ and a synchronous 32 second signal φ _32S and outputs a comparison timing signal S ₄₆ . The operation of the temperature detection device 4 having the above configuration will be explained with reference to FIG. In FIG. 5, A is the synchronous 64-second signal φ _64S , B is the synchronous 32-second signal φ _32S , C is the synchronous 4-hour signal φ _4h ,
D represents the specific temperature condition signal S ₄₂ , E represents the comparison time condition signal S ₄₃ , F represents the comparison condition signal S ₄₄ , G represents the oscillation timing signal S ₄₅ , and H represents the comparison timing signal S ₄₆ . The temperature register 40 of the temperature detection circuit 41 sets the temperature information value T at the falling timing of the synchronous 64-second signal _φ64S shown in FIG. At this time, the specific temperature detection circuit 42 sets the specific temperature condition signal S ₄₂ to logic when T ₃ , T ₄ , T ₅ , T ₆ , _{and 7} are the same value and T ₈ is logic “0”, that is, when 120≦T<136. Set to “1”. now t ₁
At time point C, when the synchronous 4-hour signal _φ4h rises, RSFF43 is set and the comparison time condition signal
_S43 becomes logic "1" as shown in E. While this comparison condition signal _S43 is at logic "1", at time _t2 , the specific temperature condition signal _S42 becomes logic "1" as shown in D.
When this happens, the AND circuit 44 causes the comparison condition signal S ₄₄ to rise as shown in F, and the RSFF 45 causes the oscillation timing signal S ₄₅ to rise as shown in G. The logic "1" of this oscillation timing signal _S45 resets the comparison time condition signal _S43 shown in E, and thereby the comparison condition signal _S44 shown in F also becomes logic "0". t ₄
At this point, the RSFF 45 is reset by the synchronous 64-second signal _φ64S shown in A, and the oscillation timing signal _S45 becomes logic "0" as shown in G. Of the logic “1” between t ₂ and _{t 4} of the oscillation timing signal S ₄₅ shown in this figure,
The AND circuit 46 generates the synchronous 32 second signal _φ32S shown in B.
As shown in FIG. 1, the comparison timing signal _S46 becomes logic "1" at the time from _t3 to _t4 in the second half. As shown in E, the comparison time condition signal _S43 which became logic "0" at time _t2 remains logic "0 _" until the synchronous 4-hour signal _φ4h shown in C rises at time t3, _four hours after t1. will be maintained. That is, when the temperature information value is 120T<136, the temperature detection device 4 outputs the oscillation timing signal _S45 which becomes logic "1" for 32 seconds every four hours at the minimum time interval, and also outputs the second half of this oscillation timing signal _S45 . The comparison timing signal _S46 is output as a logic "1" for 16 seconds.

The high frequency oscillation circuit 6 includes an oscillation inverter 61, a feedback resistor 62, a crystal oscillator 63, an input capacitor 64,
It consists of an output side capacitor 65 and a waveform shaping inverter 66, and outputs a high frequency oscillation signal _fH .
Consists of a CMOS crystal oscillator circuit.

The oscillation control circuit 7 supplies a positive power supply 71 to the positive power terminal of the oscillation inverter 61 of the high-frequency oscillation circuit 6, inverts the oscillation timing signal S45 from the temperature detection device 4 using the inverter 72, and inverts the oscillation timing signal _S45 from the oscillation inverter 61. Supply to power terminal.

In the oscillation control circuit 7 and the high frequency oscillation circuit 6 having the above configuration, when the oscillation timing signal _S45 of logic "0" is now supplied from the temperature detection circuit 4, this signal is inverted by the inverter 72 and the oscillation inverter is inverted. It is supplied to the negative power terminal of 61. As a result, both the positive power supply terminal and the negative power supply terminal of the oscillation inverter 61 are set to logic "1".
As a result, power is not supplied and the high frequency oscillation circuit 6
oscillation operation stops. Conversely, when the oscillation timing signal _S45 of logic "1" is supplied, the inverter 7
2, logic "0" is supplied to the negative power supply terminal of the oscillation inverter 61, so power is supplied to the oscillation inverter 61, and the high frequency oscillation circuit 6 oscillates and outputs the high frequency oscillation signal _fH .
That is, the high frequency oscillation circuit 6 is an oscillation circuit that performs an intermittent oscillation operation that oscillates when the oscillation timing signal _S45 is logic "1".

The comparison circuit 8 will be explained.

81 is a phase comparator circuit consisting of a D type FF, which constitutes a phase detection means, and a clock input terminal.
C _L is a low frequency oscillation signal from the reference signal generator 9.
F _L is supplied, a high frequency oscillation signal f _H is supplied from the high frequency oscillation circuit 6 to the data input terminal D, and a phase signal f _P is output from the output terminal Q. 82 is AND
This circuit inputs this phase signal _fP and the comparison timing signal _S46 from the temperature detection device 4, and outputs a phase difference pulse train signal _S82 . 83 is a NOR circuit which inputs the synchronous 64-second signal φ _64S and the synchronous 32-second signal φ _32S and outputs a phase difference clear signal S ₈₃ . 84 is 10
This is a phase difference counter consisting of a digit counter.The clock input terminal φ is supplied with the phase difference pulse train signal _S82 , the reset input terminal R is supplied with the phase difference clear signal _S83 , and the 10th digit is supplied with the phase difference pulse train signal S82. A correction code signal _S84 is outputted from the output terminal Q9 _of . 8
Reference numeral 5 denotes a correction signal generating circuit, which inputs a signal obtained by inverting the comparison timing signal _S46 by an inverter 850 through an input terminal _L1 , inputs an inverted signal ₂₃ of a synchronous 2-second signal _φ23 through an input terminal L2, and outputs the signal from an input terminal _L2 . Latch circuit 8 that outputs 1-pulse correction signal S ₈₅₁ from Q
51, this 1-pulse correction signal S ₈₅₁ and synchronized 8Hz signal φ8 are input, and an 8-pulse correction signal S ₈₅₂ is output.
AND circuit 852 and an EXNOR circuit 853 which inputs the signals of the output terminals Q ₃ , Q ₄ , . . . Q ₇ , ₈ of the phase difference counter 83 and outputs a specific phase difference signal S ₈₅₃
This specific phase difference signal S ₈₅₃ is input from input terminal C, and the one-pulse correction signal S ₈₅₁ is input from input terminal A.
and input the above 8-pulse correction signal from input terminal B.
Input S ₈₅₂ and output pulse correction signal from output terminal Q.
AB selector 854 that outputs _S85 . In addition, the latch circuit 851 and AB selector 85
4 is a well-known circuit, and the latch circuit 851 is composed of one AND circuit and two NAND circuits as shown in the figure, and from the rise of the input signal from the input terminal _L1 ,
A pulse signal that is logic "1" until the fall of the input signal at input terminal _L2 is output from output terminal Q, and AB selector 854 is input when the input signal at control input terminal C is logic "1". The input signal from the terminal A is passed through the output terminal Q, and the input signal from the input terminal B is passed through the output terminal Q when the logic is "0". The operation of the comparator circuit 8 having the above configuration will be explained with reference to FIG. In FIG. 6, A is the synchronous 64-second signal φ _64S , B is the synchronous 32-second signal φ _32S , C is the phase difference clear signal S ₈₃ , D is the comparison timing signal S ₄₆ , E is the correction code signal S ₈₄ , and F is the 1-pulse correction signal S ₈₅₁ , 8-pulse correction signal S ₈₅₂ ,
H is the specific phase difference signal S ₈₅₃ , R is the pulse correction signal
Represents S ₈₅ . Note that the period between t ₁ and t ₃ is 32 seconds, and the period between t ₃ and _{t 4} is 1 second.

In response to the synchronization signals shown in A and B, the NOR circuit 83 generates a phase difference clear signal _S83 which becomes logic "1" from _t1 to _t2 as shown in C, and the phase difference counter 84 is reset. Signal S ₈₄ becomes logic "0". Next, when the comparison timing signal S ₄₆ supplied from the temperature detection device 4 becomes logic "1" from time t 2 to t ₃ as shown in d, as already explained, when the comparison timing signal _S 46 supplied from the temperature detection device 4 becomes logic "1" from time t ₁ to t ₃ . , the oscillation timing signal S ₄₅ is set to logic "1", and as a result, the high frequency oscillation circuit 6 is in oscillation operation, so the phase comparator circuit 81 detects the phase of the high frequency oscillation signal f _H using the low low frequency oscillation signal f _L as a sampling signal. The AND circuit 82 outputs the phase difference pulse train signal S ₈₂ through this phase signal f _P , and the phase counter 84 outputs the phase _difference pulse train signal S 82 for 16 seconds from t ₂ to t ₃ . Count _S82 , ie the phase signal _fP . Since the phase code signal S ₈₄ shown in E is the output signal of the most significant digit of the phase difference counter 84, it starts at logic "0" when the count number of the phase difference counter 84 is zero at time t ₂ , and starts at logic "0" at time t ₂₀ . When the count number reaches 512 at the time, it is reversed to logic “1”,
At t ₂₁ , an overflow occurs and the count decreases.
When it becomes zero from 1023, it becomes logic "0". From _t2 to _t3 , the correction code signal _S84 repeats the operation from _t2 to _t21 . At this time EXNOR
Specific phase difference signal S ₈₅₃ which is the output signal of circuit 853
The count number of the phase difference counter 84 is 504 or more and 520
When the value is less than 1, the logic becomes "1", as shown in FIG. When the contents of the phase difference counter 84 at time _t3 are denoted by the phase difference count number C _P , it is expressed by the following equation.

C _P = [f _P ×16] −2 ¹⁰ × n _P ...(3) Here, n _P is the phase difference counter 84 between t ₂ and t ₃
is the number of overflows, and "[ ]" represents digitization. The correction code signal S ₈₄ shown in E at time t ₃ and the specific phase difference signal S ₈₅₃ shown in H are uniquely determined by this phase difference count number C _P , and the logic of the phase difference clear signal S ₈₃ shown in C at time t ₅ is 1'' until the phase difference counter 84 is reset. E and H are examples of C _P = 515 and n _P = 1, and at time t ₃ , the correction code signal S ₈₄ is logic “1” due to 512 C _P ,
The specific phase difference signal S ₈₅₃ is logic “1” because 504C _P <520. From the next time t ₃ to t ₄ , the latch circuit 851 generates a one-pulse correction signal shown in F.
One pulse is output to S ₈₅₁ , and AND circuit 852
Accordingly, 8 pulses are output as the 8-pulse correction signal S ₈₅₂ shown in FIG. When the specific phase difference signal S ₈₅₃ is logic "1" as shown in H, the AB selector 854 converts the 1-pulse correction signal S ₈₅₁ shown in F to the pulse correction signal S ₈₅ as shown in R. On the contrary, the specific phase difference signal
When S ₈₅₃ is logic "0", the 8-pulse correction signal S ₈₅₁ shown in G is used as the pulse correction signal S ₈₅ .

That is, the comparison circuit 8 receives the comparison timing signal
The phase of the high frequency oscillation signal f _H and the low frequency oscillation signal f _L is compared with the logic "1" of S ₄₆ , and the aging information signal S ₈ is output according to the phase difference count number C _P which is the counted value. A correction code signal _S84 , which is a signal corresponding to the correction direction, is determined, and a pulse correction signal _S85 , which is a signal corresponding to the correction amount as the aging information signal _S8 , is also output.
Specifically, the correction code signal S ₈₄ becomes logic “1” when 512C _P and logic “0” when C _P < 512, and the pulse correction signal S ₈₅ becomes 1 pulse when 504C _P < 520, and 8 pulses in other cases. It becomes a pulse signal consisting of pulses.

The aging correction circuit 21 will be explained.

Reference numeral 211 is the latch circuit explained in connection with the comparison circuit 8, the input terminal L ₁ is supplied with the inverted signal ₂₃ of the synchronous 2-second signal, the input terminal L ₂ is supplied with the inverted signal ₅₁₂ of the synchronous 512 Hz signal, and the output is Aging correction synchronization signal φ _A is output from terminal Q.

212 is a switching ratio memory circuit consisting of a 10-digit up-down counter, and a pulse correction signal _S85 is supplied from the comparator circuit 8 to the clock input terminal φ.
A correction code signal _S84 is supplied from the comparator circuit 8 to the up-down mode input terminal UD.

This up-down counter 212 is a known counter that functions as an up-counter when the input signal from the up-down mode input terminal UD is logic "1" and as a down counter when it is logic "0". 213 is an AND circuit which inputs an output signal from an output terminal of a switching circuit 215 to be described later and a synchronous 512Hz signal _φ512 , and outputs a count-up signal _S213 .

214 is a 10-digit presettable counter, and data input terminals D ₀ , D ₁ , . . . D ₉ are connected to output terminals Q ₀ , Q ₁ , . . . Q ₉ of the switching ratio storage circuit 212
The aging correction synchronizing signal φ _A is supplied to the preset enable terminal PE, the count up signal S ₂₁₃ is supplied to the clock input terminal φ, and the overflow signal S ₂₁₄ is supplied from the output terminal Q ₉ . Output. This presettable counter 214 inputs data input terminals D ₀ , D ¹ ,
...This is a known counter preset to the input signal of _D9 . 215 is a switching circuit consisting of a trigger type FF, the clock input terminal φ is supplied with the above-mentioned overflow signal S ₂₁₄ , and the reset input terminal R is supplied with the above-mentioned aging correction synchronization signal φ _A
is supplied, and the aging correction signal is output from output terminal Q.
Output S _A. This trigger type FF is a known FF used in a counter that inverts an output signal at the falling edge of an input signal from a clock input terminal φ. The operation of the aging correction circuit 21 having the above configuration will be explained using FIG. 7.

In FIG. 7, A is a synchronous 512Hz signal φ ₅₁₂ ,
B is the aging correction synchronization signal φ _A , C is the count up signal S ₂₁₃ , D is the overflow signal S ₂₁₄ ,
E represents the aging correction signal S _A. t ₁ to t ₃
The interval is 2 seconds.

In response to the synchronous 512 Hz signal φ ₅₁₂ shown in (a), the latch circuit 211 outputs the aging correction synchronization signal φ _A , which is a pulse signal with a 2-second cycle, as shown in (b). t ₁
When the aging correction signal φ _A becomes logic "1" as shown in FIG.
4 is preset with the value of the switching ratio storage circuit 212. In addition, the switching FF 215 is reset, the aging correction signal S _A becomes logic "0" as shown in E, and the AND circuit 213 thereafter performs the synchronization 51 shown in A.
The count up signal S ₂₁₃ as shown in C shows the 2Hz signal.
shall be. Next, at time t ₂ , presettable counter 2
14 overflows and the overflow signal S ₂₁₄ falls as shown in D, the switching FF 215 inverts the aging correction signal S _A to logic "1" as shown in E. As a result, the AND circuit 213 no longer passes the synchronous 512 Hz signal, and the count-up signal _S213 becomes logic "0" as shown in C. The operation for 2 seconds from t ₁ to t ₃ is repeated after t ₃ . Here, the count number of the up-down counter, that is, the storage content of the switching ratio storage circuit 212 is assumed to be C _C. In this case, the time from t ₁ to t ₂ is (1024−C _C )/512. As defined earlier, the aging correction factor _A is the time proportion of the aging correction signal S _A at logic "1", t ₁ to t ₃ are 2 seconds, t ₂
Since the aging correction signal S _A becomes logic "1" at t ₃ as shown in E, the following equation holds true.

_A = C _C /1024 ...(4) It was already shown in equation (1) above that the frequency of the low-frequency oscillation signal f _L is corrected by the aging correction factor _A , but equation (4) It is shown that the aging correction factor _A is changed by changing the memory content C _C of the circuit 212, and as a result, the low frequency oscillation frequency F _L can be corrected. This switching ratio storage circuit 212
The stored content C _C is changed by adding or subtracting the logic "1" or logic "0" of the correction code signal S ₈₄ by the number of pulses of the pulse correction signal S ₈₅ .

That is, the aging correction circuit 21 corrects the storage content C _C of the switching ratio storage circuit 212 using the correction code signal S ₈₄ which is the aging information signal S ₈ outputted from the comparison circuit 8 and the pulse correction signal S ₈₅ , and also ) The low frequency oscillation signal f _L is corrected using the aging correction factor _A based on the equation (1).

The aging correction operation, which is the second operation of the electronic timepiece having the above configuration, will be explained.

Now, the temperature detection device 4 has a temperature information value T of 120T.
When detecting a specific temperature <136, the oscillation timing signal _S45 is set to logic "1" for 32 seconds at intervals of at least 4 hours. As a result, the oscillation control circuit 7 puts the high frequency oscillation circuit 6 into an oscillation operating state. Also, the temperature detection device 4 sets the comparison timing signal _S46 to logic "1" for the latter 16 seconds of this 32 seconds. Thereby, the comparator circuit 8 compares the low frequency oscillation signal f _L with the high frequency oscillation signal f _H of the high frequency oscillation circuit 6 which is already oscillating.

Here, the high frequency oscillation frequency f _H and the low frequency oscillation frequency f _L will be explained.

The standard value of high frequency oscillation frequency f _H is f _HS = 4194304
(Hz), the standard value of low frequency oscillation frequency f _L is f _LS = 32768
(Hz), the following relationship holds true between f _HS and f _LS .

f _HS = f _LS ×m (5) m is a positive integer, and is 128 in this embodiment. this
Since f _HS is an integral multiple of f _LS , the low frequency oscillation frequency f _L and the high frequency oscillation frequency f _H are compared by phase comparison.

The phase comparison circuit 81 of the comparison circuit 8 is a circuit that performs this phase comparison, and the frequency of the phase signal f _P that is its output signal is expressed by the following equation.

f _P = |f _H −f _L ×m| ...(6) Here, "| |" is an absolute value symbol.

The frequency deviation d _H of the oscillation frequency f _H of the high frequency oscillation circuit 6 from the standard high frequency oscillation frequency f _HS is set by the following equation.

d _H =f _H −f _HS /f _HS =32/f _HS +64/f _HS ×n _P …(7) n _P is the number of overflows of the phase difference counter 84 explained in the comparison circuit 8, In the example, the high-frequency oscillation frequency f _H takes an appropriate positive integer value within a range that does not deviate greatly from its standard value f _HS . In this case, under the condition that f _L ≒ f _LS , the absolute value symbol in equation (6) is unnecessary, and when using equations (6), (7), and the above-mentioned equation (3), the phase difference count number C _P is It is expressed by the following formula.

C _P = [(f _HS - _{f L} × m) × 16] + 512 ... (8) The case where f _L > f _LS will be explained. At this time, from equation (8), C _P <512, and the comparison circuit 8 sets the correction code signal S ₈₄ to logic “0”. If C _P ≧504, the 1-pulse signal becomes the pulse correction signal, and if C _P <504, the 8-pulse signal becomes the pulse correction signal. This pulse is output to _S85 , and the aging correction circuit 21 subtracts the switching ratio storage content C _C by this pulse. As a result, the aging correction factor is determined by equation (4) above.
_A decreases, and according to equation (1) above, the low frequency oscillation frequency f _L
is corrected so that it eventually decreases. That is, a positive deviation of the low frequency oscillation frequency f _L from the standard frequency f _LS is corrected in a negative direction by the aging correction operation.

Conversely, when f _L < f _LS , C _P ≧512 and the correction code signal S ₈₄ becomes logic “1” and the switching ratio memory contents
C _C is increased by +1 if C _P <520, and +8 if C _P ≧520, _A is increased by equation (4), and f _L is corrected by equation (1). That is, the negative deviation of the low frequency oscillation frequency f _L from the standard frequency f _LS is corrected in the positive direction by the aging correction operation.

Therefore, the low frequency oscillation frequency f _L is corrected to the standard low frequency oscillation frequency f _LS by the aging correction operation.
That is, since the low frequency oscillation frequency f _L is corrected to the standard high frequency oscillation frequency f _HS from equation (5), the accuracy becomes the high frequency oscillation frequency f _H from equation (7).

In addition, in one aging correction operation, the number of pulses of the pulse correction signal is determined depending on whether the phase difference count number C _P falls within the range of ±8 with respect to the standard value 512 when f _L = f _LS . Limited to 1 and 8. The amount of change in the switching ratio memory content C _C is determined by this number of pulses, and the low frequency oscillation frequency f _L
The amount of correction is determined. Therefore, the aging correction operation limits and limits the amount of correction in one correction operation.

This correction amount limit is due to aging correction malfunction,
For example, since the amount of correction due to one malfunction is limited for malfunctions due to a difference between the temperature detected by the temperature detection device 4 and the outside temperature due to a sudden change in the outside temperature, the effect of this is minimized.
In addition, the amount of correction is limited so that the normal aging of the low frequency oscillation circuit 1 can be dealt with with the minimum amount of correction, and a relatively large frequency shift caused by an impact can be quickly corrected by several times of correction with a large amount of correction. This has the effect of realizing the corresponding aging correction operation with a simple circuit that does not use an arithmetic circuit.

Next, the resolution and correction width of the aging correction operation will be explained.

Comparison timing signal in temperature detection device 4
The time when _S46 takes logic “1” is the phase comparison time T _P
(16 seconds in this embodiment), and the number of digits of the phase difference counter 84 in the comparator circuit 8 is set to the number of digits of the phase difference counter 84.
K _P (10 in this example). Using this, the frequency deviation d _H of the high frequency oscillation signal f _H with respect to f _HS is set by the following formula.

d _H = 2 ^Kp-1 /t _P ×f _HS +2 ^Kp /t _P ×f _HS ×n _P (9) In this case, the phase difference count number C _P is given by the following formula.

C _P = [(f _HS −f _L × m) × t _P ] + 2 ^Kp-1 ...(10) These formulas (9) and (10) are replaced by formulas (7) and (8) in this example. becomes. As a result, if the resolution of the comparator circuit 8 is d _P and the correction width is h _P , then d _P =1/t _P ×f _HS ·h _P =2 ^Kp /t _P ×f _HS (11). In this example, approximately d _P =0.0149 (ppm) and h _P =15.26 (ppm).
Next, the switching ratio memory circuit 2 of the aging correction circuit 21
The number of digits of 12 is set as W _A (10 in this embodiment), and the period of the aging correction synchronization signal φ _A is set as the aging correction period t _A (2 seconds in this embodiment). The frequency of the clock input and the input of the input terminal _L2 of the latch circuit 211 is K _A /t _A. At this time, aging correction circuit 2
If the theoretical resolution according to 1 is d _A and the correction width is h _A , using the above equation (1), D _A = f _SWA / f _LS × 1/2 ^KA , h _A = f _SWA / f _LS …( 12) becomes. The resolution achieved at the low oscillation frequency f _L is the larger of d _P and d _A , and the correction width is the narrower of h _P and h _A. Then d _P and d _A ,
It is desirable to set h _P and h _A to match.
Using equations (11), (12), and (5), this condition becomes K _A = K _P , f _SWA = 2 ^{K A} /(t _p ×m) (13). In this example, K _A = K _P = 10, and t _P =
16. From m=128, set f _SWA = 0.5 (Hz). However, even if this f _SWA has a slight variation, it will affect the resolution and correction width of the aging correction, but it will not cause any problem to the aging correction operation itself.

FIG. 8 is a main circuit diagram showing a specific configuration of the temperature detection device 4 and temperature correction circuit 22 in FIG. 3.

Conventionally, small electronic devices such as electronic watches are equipped with temperature sensors to detect the temperature of the mobile phone and generate time reference signals.
Many methods have been proposed for temperature compensation of _fS . It goes without saying that any of these methods may be used for temperature correction in the present application. In this embodiment, the temperature information is captured as a digital value, and furthermore, this digital temperature information is transferred to a monolithic IC without using external components such as a temperature sensing element, such as a thermistor, or another crystal resonator.
This is achieved by using a standardized temperature detection circuit.

That is, FIG. 8 will be explained with reference to the temperature characteristic diagram of FIG. 9.

In the temperature detection device 4, the temperature detection circuit 41 supplies the temperature information signal _S4 consisting of T ₀ , T ₁ , . . . T ₈ from the temperature register 40 to the temperature correction circuit 22 . The temperature correction circuit 22 creates a temperature correction signal _ST from this temperature information signal S ₄ and supplies it to the frequency control circuit 24 .

In the temperature detection circuit 41, 47 is a temperature-sensitive oscillation circuit, 481 is a gate signal counter that counts the output signals of this temperature-sensitive oscillation circuit 47 by a predetermined number, and 482
is a comparison counter that is set in advance to a predetermined value and then counts for the same period as the gate signal counter 481 to count the output signal f _L of the reference signal generator 9 or its frequency divided signal; 40 is this comparison counter 482; 483 is a control circuit for time-series control of the components; 491 is a numerical value A storage circuit that provides the gate signal counter 481 with the numerical value A to be counted; 4
Reference numeral 92 denotes a numerical value B storage circuit which provides a numerical value B to be set in advance to the comparison counter 482. Note that in this embodiment, the numerical storage circuit 4
91 and 492 are constructed of memory circuits within the same IC, but selective connection patterns provided outside the IC chip may also be used. The operation of the temperature detection circuit 41 having the above configuration will be explained.

As mentioned above, the temperature detection circuit 41 is a circuit that sets the temperature information value T in the temperature register 40 at the falling edge of the synchronous 64 second signal, and the control circuit 483 synchronizes with this and sets the temperature at fixed time intervals, that is, every 64 seconds. It controls the detection operation.

When the time for this temperature detection comes, first, numerical values A and B are set in the gate signal counter 481 and the comparison counter 482, respectively, and then the gate signal counter 481 is set with a period τ using the temperature-sensitive oscillation circuit 47 as a signal source. The comparison counter 482 receives a synchronous C signal φ _C of frequency f _C whose signal source is the reference signal generator 9 .

Further, the comparison counter 482 starts counting operation from the state where the count content is the numerical value B, and is controlled by the control circuit 483 so that it operates for exactly the same period as the gate signal counter 481, and the gate signal counter 481 receives the signal P with period τ. When it finishes counting A pieces, that is, after A x τ seconds, it stops. During this time, the comparison counter 482 overflows several times,
The last remaining value becomes the temperature information value T, which is transferred to and stored in the temperature register 40 by the control circuit 483 at the falling timing of the synchronous 64-second signal _φ64S . The temperature information value T obtained as a result can be expressed by the following equation.

T=[A×τ×f _C ]+B−2 ^Kt × _nt (14) Here, _Kt represents the number of bits in the temperature register 40, and _nt represents the number of overflows.

Next, the temperature-sensitive oscillation circuit 47, which is a temperature sensor of the temperature detection circuit 41, will be explained.

471 is a temperature-sensitive constant voltage circuit whose output voltage V _R changes linearly according to the ambient temperature; 472 is a voltage-current conversion circuit that converts the output voltage into a current;
473 is a ring oscillation circuit connected in series to the voltage-current conversion circuit 472, 474 is an oscillation signal waveform shaping circuit, 475 is a frequency dividing circuit for adjusting the oscillation period to an appropriate length, and 476 is a power source for each of the circuits. This is an inverter for switching. The operation of the temperature-sensitive oscillation circuit 47 having the above configuration will be explained.

Now, the switch inverter 476 is at logic “1”
When inputted, the operating current of the temperature-sensitive constant voltage circuit 471, the voltage-current conversion circuit 472, and the waveform shaping circuit 474 flows through it. Ring oscillation circuit 473
The oscillation period of depends on the current, and the current depends on the relationship between the threshold voltage _VTH of the n-channel FET used in the voltage-current conversion circuit 472 and the output voltage _VR of the temperature-sensitive constant voltage circuit 471. That is, the higher the temperature, the smaller the difference between V _TH and _VR , the smaller the current, and the longer the oscillation period τ.
The temperature characteristic of this oscillation period τ is a straight line with a substantially constant slope, and can be expressed by the following equation.

τ=α×θ+τ ₀ (15) where θ represents the temperature, τ ₀ represents the period τ at 0° C., and α represents the temperature coefficient.

Therefore, from equations (14) and (15), the temperature information value T is expressed by the following equation.

T=[A×f _C ×(α×θ+τ ₀ )]+B−2 ^Kt ×n _t
...(16) In equation (16), if the overflow term 2 ^Kt ×n _t is excluded, the temperature information value T is a linear function of the temperature θ,
It also shows that this linear function can be freely adjusted using numerical values A and B.

Next, the temperature correction circuit 22 will be explained.

As shown in the figure, the temperature correction circuit 22 uses the output signal of the frequency dividing circuit 31 as a synchronization signal. The frequency dividing circuit 31 is a continuous frequency dividing circuit 311, 312, 31
Of these, 312 is a first frequency dividing circuit and 313 is a second frequency dividing circuit, each having a 7-bit configuration. The 7-bit output signal of the frequency dividing circuit 312 is used as the first synchronizing signal φ _1st , and the frequency dividing circuit 31
The 7-bit output signal of 3 is assumed to be the second synchronization signal φ _2od .

In the temperature correction circuit 22, 221 compares the lower 7 bits _T0 to _T6 of the temperature information signal _S4 from the temperature register 40 with the first synchronization signal _φ1st , and calculates the first synchronization signal φ1st. The _first comparator circuit 222 outputs a pulse signal _P1 that becomes logic "1" until the 7 bits of φ1st match all zero bits with the 7 bits of _T0 to _T6 .
The 7 bits from T ₀ to T ₆ from zero are compared with the second synchronization signal φ _2od , and the logic “1” is maintained until the second synchronization signal φ _2od matches the 7 bits from T ₀ to T ₆ from zero. A second comparator circuit 223 outputs a pulse signal P ₂ that is ``223'', which outputs a pulse signal P 2 that is equal to ``223'', which outputs a pulse signal P 2 that outputs a pulse signal P _{2 that is ``223'} '.
Temperature correction signal from _T7 and _T8 , which are the upper two bits of
This is a pulse synthesis circuit that synthesizes _ST . The operation of the temperature correction circuit 22 having the above configuration will be explained.

When the value indicated by the lower 7 bits T ₀ to T ₆ of the temperature register 40 is n, and the period of the input signal of the first frequency dividing circuit 312 is 1, both comparison circuits 221,
The periods of the 222 output pulses P ₁ and P ₂ are respectively
128 and 16384, and the duty of the signal waveform, that is, the time ratio of logic "1" to the period, is both n/128. When the most significant bit _T8 of the temperature information signal _S4 is logic "1", the pulse synthesis circuit 223
Temperature correction signal _ST is set to logic “1”. In other words, the temperature correction factor _T is expressed by the following formula.

_T = 1 (256≦T<512) ... (17) Also, when T ₈ is logic "0" and T ₇ is logic "1", the AND signal of P ₁ and P _{2 is 2} as the temperature correction signal S _T. At this time, the temperature correction signal S _T
The time to take logic “1” during the 16384 period of n ²
The temperature correction factor _T is as follows.

_T = n ² / 16384 On the other hand, when T ₈ is logic “0” and T ₇ is also logic “0”, the inverted signal ₁ of P ₁ and the inverted signal ₂ of _P 2
AND signals ₁ and ₂ are output as the temperature correction signal S _T. The time period during which the temperature correction signal _ST takes logic "1" during the period of 16384 is (128-n) ² .
However, the above n is the temperature information value T of the temperature register 10.
The relationship is as follows.

n=T (0≦T<128) n=T−128 (128≦T<256) Therefore, the temperature correction factor _T is as follows.

_T = (T-128) ² /16384 (0≦T<256)……(18
) That is, the temperature correction circuit 22
For temperature information value T from 0, equation (17) and (18)
This is a circuit that outputs a temperature correction signal S _T having a temperature correction factor _T shown by the equation.

The temperature correction operation, which is the third operation of the electronic timepiece having the above configuration, will be explained using FIG. 9.

FIG. 9 is a temperature characteristic diagram with temperature θ (°C) plotted on the horizontal axis, and a is a temperature characteristic diagram of the reference signal generator 9;
b is a temperature characteristic diagram of the temperature correction factor _T , and c is a temperature characteristic diagram of the temperature information value T. The output frequency f _L of the reference signal generator 9 is expressed by the above equation (1).
In equation (1), let f _L0 and f _L1 be the frequencies when the temperature correction factor _T is 0 and 1, respectively, then f _L0 = f _B − f _SWA × (1 − _A ) − f _SWT ……( 19) It is expressed as f _L1 = f _L0 + f _SWT ... (20). Equation (1) above shows that the temperature correction factor _T and the aging correction factor _A act independently on the low frequency oscillation frequency f _L . Here, in order to further discuss temperature correction, the aging correction factor _A is assumed to be constant.

Further, the reference low frequency oscillation frequency f _B exhibits a quadratic characteristic that is upwardly convex with respect to temperature, and f _SWA and f _SWT can be considered to be constant with respect to temperature. From this, the apex temperature of the quadratic curve of f _B is θ _ZT , the quadratic temperature coefficient is a,
When f _L0 at θ _ZT is set to the standard low frequency oscillation frequency f _LS , that is, 32768 Hz, and the frequency deviations of f _L0 and f _L1 with respect to this f _LS are taken as d ₀ and d ₁ , it is expressed by the following equation.

d ₀ = f _L0 − f _LS / f _LS = a (θ−θ _ZT ) ² … (21) d ₁ = f _L1 − f _LS / f _LS = a (θ − θ _ZT ) ² + d _SWT … ( twenty two
) Here, a is the quadratic temperature coefficient, and d _SWT is a constant value of f _SWT /f _LS . The specific example shown in the figure is θ _ZT = 25°C, a =
-0.033ppm/℃ ² , _dSWT =30ppm.

Figure 9a shows the frequency deviation for this f _LS on the vertical axis.
It is in ppm. The curve d ₀ and the curve d ₁ correspond to the equations (21) and (22) above. Here, if the temperature at which d ₁ becomes zero is θ ₁ and θ ₂ and d ₁ =0 in equation (22), the following equation is obtained.

In a specific example, θ ₁ =−5.15° and θ ₂ =55.15°.

As shown in FIG. 9c, the temperature information value _{T is}
are adjusted so that they become 0 and 256, respectively. That is, the temperature information value T is adjusted according to the following equation.

In the specific example, T=4.2453×θ+21.87.

Adjusting the temperature information value T to the linear function of θ in equation (24) is to adjust the values A and B in equation (16) above.
This is done by At this time, since the temperature information value T is 9 bits, if digital errors are ignored, the result will be as shown in FIG. 9c. At this time, the temperature correction factor _T becomes as shown in FIG. 9b from equations (17) and (18).
On the other hand, the low-frequency oscillation frequency f _L is calculated by substituting the equation (19) into the above equation (1) to obtain the following equation.

f _L = f _L0 + f _SWT × _T When formulas (21) and (22) are applied to the above formula, the frequency deviation d _L of the low frequency oscillation signal f _L is given by the following formula.

d _L = d ₀ + d _SWT × _T ... (25) Substituting equation (17) into this equation, the following equation is obtained.

d _L = d ₀ + d _SWT (256≦T<512) In the end, the following equation holds true.

d _L = d ₁ (256≦T<512) ... (26) Also, by substituting equation (18) into equation (25), the following equation is obtained.

d _L = d ₀ + d _SWT × (T-128) ² /16384 (0≦T<256) By substituting the temperature information value T of equation (24) into this equation, the following equation is obtained.

d _L = d ₀ −a (θ−θ _Z ) ² (0≦T<256) As a result, the following equation holds true from equation (21).

d _L =0 (0≦T<256) (27) Therefore, from the equations (26) and (27), the low frequency oscillation frequency deviation d _L is as shown in FIG. 9a. Therefore, temperature correction is achieved at a temperature between θ ₁ and θ ₂ according to equation (23), that is, 0≦T<256.

The operation of the electronic timepiece according to this embodiment will be explained using FIG. 10 based on the three operations described above.

Figure 10 shows the temperature θ (°C) on the horizontal axis.
a is the temperature characteristic of the frequency deviation of both oscillation circuits 1 and 6,
b indicates the temperature characteristic of the temperature information value T.

In FIG. 10a, the curves d ₀ , d ₁ , and d _L correspond to the aforementioned equations (21), (22), and (26) and (27). The curve d _H represents the high frequency oscillation frequency deviation set to be the frequency deviation when n _P =4 in the above equation (7) in the specific temperature range θ ₃ to θ ₄ . This curve d _H is a cubic curve as shown in the figure, and therefore, when θ ₄ is narrow from θ ₃ , the deviation of d _H is very small and can be ignored. Here, n _P =4 and the specific temperature range θ ₃ to θ ₄ will be explained.

In addition to the conditions explained in equation (7) above, n _P = 4 requires that d _H and d _L be separated to some extent in order to stabilize the phase comparison operation of f _H and f _L in the comparator circuit 8, that is, d _H and d _L. , and since d _L is time-divided between d ₀ and d ₁ , n _P ≧2 is an absolute condition in the specific example, and this value was chosen with even greater safety in mind. The specific temperature range is the first
This will be explained with reference to Figure 0 b.

As mentioned above, 120≦T<136 is a specific temperature range, and by calculating backwards from the above equation (24), it is approximately θ ₃ = 23.1, θ ₄
= 26.9, resulting in a narrow temperature range of approximately 25° ± 2°.

As explained above, the high frequency oscillation frequency deviation d _H is set, and the low frequency oscillation frequency deviation d _L is zero as shown in Figure 10a, that is, the low frequency oscillation frequency
When setting f _L to the standard low frequency oscillation frequency f _LS , if the low frequency oscillation frequency deviation deviates as shown in the curve d _L ′ shown in the figure, it is quickly corrected to d _L by the aging correction operation described above. become.

In this embodiment, regarding the setting of the high frequency oscillation frequency _fH and the low frequency oscillation frequency _fL , a trimmer capacitor is used for the oscillation capacitance of the high frequency oscillation circuit 6, that is, the input side capacitor 64 or the output side capacitor 65, and both Both crystal oscillators of the oscillation circuit and this trimmer capacitor are the only external components of the integrated circuit. For this reason, after a glass-sealed crystal resonator is attached to the low frequency oscillation circuit 1, the frequency of this crystal resonator is adjusted using a laser. At this time, it is generally said that the aging of the low frequency oscillation circuit 1 becomes a little worse, but in the present application, aging is caused by the high frequency oscillation circuit 6, so there is no problem. In addition, the high frequency oscillation circuit 6 adjusts the frequency using a trimmer capacitor, but the amount of adjustment should theoretically be 1/2 of the aging correction width h _P (7.63 ppm in the specific example).
You can also use a fairly small amount if you have some extra time.

The fact that this adjustment range is small is a good condition for realizing a highly stable high frequency oscillation circuit.

Here, another method of omitting the trimmer capacitor in the low frequency oscillation circuit 1 will be described. By using a frequency-selected crystal oscillator, or in combination with this, by increasing the number of digits k _A of the switching ratio memory circuit 212 and increasing the aging correction width h _A , a margin for aging can be provided within the aging correction width. , this is possible by incorporating a low-frequency oscillation frequency f _L .

FIG. 11 is a main circuit diagram showing another specific example of the comparator circuit 8 shown in FIG. 4.

In FIG. 11, the comparator circuit 88 is exactly the same as the comparator circuit 8 in FIG. 4 except for the addition of an initial phase difference storage circuit 86 and some accompanying changes, so only the differences due to this change will be explained. .

In the figure, in the comparison circuit 8, 56 is a 10-bit initial phase difference storage circuit, and the output terminals Q ₀ , Q ₁ ,
...The initial phase difference signal _S86 is output from _Q9 . This initial phase difference storage circuit 86 also has the numerical value storage circuit 49.
Similar to No. 1,492, it may be set by a selective connection pattern provided outside the IC chip. 87 is a phase difference counter consisting of a 10-bit presettable counter, and 10 bits of the initial phase difference signal S ₈₆ are supplied from data input terminals D ₀ , D ₁ , . . . D ₉ .
Note that this phase difference counter 87 is supplied with the phase difference clear signal _S83 in the previous example as a phase difference preset signal from the preset enable input terminal PE.

Except for the above points, the comparator circuit 88 has the same configuration as the previous specific example.

In the above configuration, the initial phase difference storage circuit 86
When the stored content of is denoted by C _S , the phase difference count number C _P in the above equation (3) is expressed by the following equation.

C _P = [f _P ×16 + C _S ] −2 ¹⁰ × n _P (28) The high frequency oscillation frequency f _H expressed in the above formula (7) is set here by the following formula.

f _H = f _HS +32×512−C _S /512+64×n _P ……(29) Here, if C _S is a real number with OC _S <1024, the phase difference count number C _P is the same as equation (8). . Actually, this C _S is a digital value, so when the digital error caused by this is ignored, the aging correction operation exactly the same as in the previous embodiment is realized in this embodiment as well.

Looking at this from a different perspective, a high frequency oscillation signal
f _H can be used as it is as an aging correction signal when an appropriate initial phase difference C _S is stored in the initial phase difference storage circuit 86 . This makes it possible to design the high frequency oscillation circuit 6 under optimal conditions for highly stable oscillation.

Further, in this specific example, it is possible to use only both crystal oscillators as external components of the integrated circuit.

Both of the above examples have the following advantageous features.

: The low frequency oscillation signal f _L that has undergone aging correction using the aging correction factor _A is converted into the high frequency oscillation signal f _H
Since the aging correction is performed by increasing or decreasing the aging correction factor _A based on the comparison result, the aging correction can be realized without using an arithmetic circuit as described above.

: Since the temperature-corrected low-frequency oscillation signal f _L and high-frequency oscillation signal f _H are compared, when obtaining a high-frequency resonator whose frequency is almost constant over a wide temperature range by screening etc., the difference between f _L and f _H is Since it is constant over a wide temperature range, the temperature range of the specific temperature in aging correction can be designed to be wider, and the reliability of the aging correction operation can be improved.

: Comparison of both oscillation signals _fH and _fL is performed by a counter that counts the phase difference between both signals. This counter repeatedly overflows when the aging correction width is exceeded. As a result, the high-frequency oscillation frequency f _H only needs to be an appropriate value within a range that does not adversely affect the phase comparison operation, thereby reducing the adjustment process of the resonance frequency of the high-frequency vibrator, which results in highly stable vibration. This is a great advantage in child manufacturing.

: Both temperature correction and aging correction can be completed in 2 seconds by means of capacitance switching means that directly controls the oscillation frequency of the low frequency oscillation circuit. Therefore, it has the advantage that the average rate can be measured in a short period of time using a generally popular rate measuring device for electronic watches. In particular, the aging correction is characterized in that the high resolution _dP in the phase comparison of equation (11) can be easily realized by the correction resolution _dA in capacitance switching shown in equation (12).

The electronic timepiece according to the present invention has major ripple effects as described below.

: We can provide clocks with an annual error of less than 1 second.

: Since the standard AT resonator does not require characteristics outside a limited temperature range, highly accurate resonators can be manufactured at low cost.

: The AT resonator only needs to be operated within a limited temperature range, and it does not need to be operated very frequently, so the overall power consumption is very small, compared to conventional low-frequency oscillation circuits. The power consumption is almost the same as that of a watch.

Thus, according to the electronic timepiece of the present invention, it is possible to improve the accuracy of the annual error to within 1 second with a slight increase in power consumption compared to the conventional timepiece, which has a great effect on improving the product appeal of the electronic timepiece. has.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an electronic timepiece according to the present invention. Second
The figure is a frequency-temperature characteristic diagram of FIG. 1, and FIG. 3 is a circuit diagram of an electronic timepiece showing a specific example of the present invention. Figures 4 and 8
The figure is a circuit diagram of the main parts in Figure 3. Figure 5, Figure 6,
FIG. 7 is a voltage waveform diagram in FIG. 4. FIG. 9 is a temperature characteristic diagram of FIG. 8. Figure 10 is Figure 3, Figure 4,
The temperature characteristic diagram of FIG. 8. FIG. 11 is a circuit diagram of a main part showing another specific example of the comparison circuit shown in FIG. 4. 1...Low frequency oscillation circuit, 2...Correction device, 4...
...Temperature detection device, 6...High frequency oscillation circuit, 7...
Oscillation control circuit, 8, 88...comparison circuit.

Claims (1)

[Claims] 1. In an electronic watch equipped with a low frequency oscillation circuit that generates a reference signal, a frequency dividing circuit that divides the frequency of the reference signal to create a time reference signal, and a time display means that displays the time using the time reference signal, A first correction means for correcting the temperature characteristics by controlling the time reference signal, a second correction means for correcting the aging characteristics, a high frequency oscillation circuit for generating a calibration signal, the low frequency oscillation circuit and the high frequency a comparison circuit for comparing an output signal with an oscillation circuit; a temperature detection means for detecting ambient temperature; and a flat part of a cubic curve that receives the output signal of the temperature detection means and indicates a predetermined temperature characteristic of the high frequency oscillation circuit. By providing a specific temperature detection means for outputting a specific temperature condition signal by detecting a specific temperature corresponding to the temperature, and by configuring the operation of the comparison circuit to be controlled by the specific temperature condition signal, the temperature detection An electronic timepiece characterized in that the first correction means is controlled by the output signal of the means, and the second correction means is controlled by the output signal of the comparison circuit.