JPS5883296A - Electronic time piece - Google Patents

Abstract

PURPOSE:To obtain an electronic time piece maintaining high accuracy for a long time, by using an XY crystal resonator which compensates temp. easily as a time reference oscillating source, and by using an AT crystal resonator as a correction reference oscillating source for an aging error. CONSTITUTION:A signal from a low frequency oscillating circuit 1 is applied to a time circuit block 3 including a dividing circuit 31 and a display driving circuit 32 after passing through a correcting device 2 to drive a time display block 5. As for aging correction, when a temp. detecting device 4 detected a specific temp., a signal of aging correction is sent to an oscillation controlling circuit 7 and a comparating circuit 8, and the circuit 7 receives this signal and operates a high frequency oscillating circuit 6, and the circuit 8 measures the deviation of frequency between the high frequency oscillating circuit 6 and the low frequency oscillating circuit 1 and prepares aging error information, and the correcting device 2 corrects a signal of the circuit 1. With regard to a temp. correction, temp. information is directly sent to the device 2 from the temp. detector 4 and the device 2 performs the temp. correction of the circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention aims at increasing the precision of electronic timepieces, and relates to an improvement of the timepiece that maintains its accuracy over a long period of time.

Conventionally, electronic clocks using crystal oscillators have relatively high accuracy, with a monthly error of several seconds and an annual error of several tens of seconds.

However, it has been considered difficult to improve the accuracy to within 1 second within one year for electronic clocks with limited space.

The reason for this is that when an XY type crystal oscillator, which is popular for watches, is used as a bent tuning fork oscillator,
The following factors can be cited when using the thickness shear vibration of an AT-cut crystal resonator, which is popular for clocks.

■ XY type crystal resonators in the 32kHz range have frequency-temperature characteristics that are quadratic curve-like with very little variation, so by adding a temperature compensation function, the temperature characteristics can be made good over a relatively wide temperature range. Although it is possible to improve the long-term aging characteristics of a resonator, its vibration modes.

It was difficult to achieve ultra-high precision due to support and other factors.

■ AT-cut MHz band crystal resonators have extremely high stability, supported by advantages such as their vibration mode and high oscillation frequency.

The frequency-temperature characteristics are expressed by a cubic curve.

Due to cut angle errors, etc., there is a great deal of variation, making it difficult to make it flat over the operating temperature range, and temperature compensation is also difficult because it is a cubic curve.

As mentioned below, the AT crystal oscillator and the XY crystal oscillator each have their advantages and disadvantages, so when one of the above crystal oscillators is selected, the attainable accuracy of one clock is AT.
Even when the best crystal units were selected, the annual error was limited to a few seconds.

The present invention eliminates the above drawbacks (1) by using an XY crystal oscillator with a temperature-compensated capacitance as the time reference oscillation source, and using an AT crystal oscillator as the aging error correction reference oscillation source, high precision can be maintained over a long period of time. The aim is to provide electronic watches that maintain

Specifically, in response to temperature fluctuations in the clock, an XY crystal oscillator is used to perform temperature compensation to absorb clock errors caused by temperature, and to reduce the aging error of the XY crystal oscillator that changes over time. AT crystal oscillators have excellent long-term stability over a specific temperature range (as an example,
By calibrating the XY crystal oscillator using only the values (4 to 25 degrees Celsius) as reference values, the aim is to eliminate most of the factors that cause errors in the clock.

Next, I will explain the outline of the operation of the electronic timepiece according to the present invention.
This will be explained with reference to a block diagram of the electronic timepiece shown in the figure.

In the figure, 1 is a low frequency oscillation circuit that has an XY crystal resonator and generates a reference signal, 2 is a correction device that corrects the output frequency of the low frequency oscillation circuit 1, and 6 is a frequency dividing circuit 31 and a display drive. A clock circuit block constituted by a circuit 62 and the like, 4 a temperature detection device including a temperature sensor, 5 a time display block, 6 a high frequency oscillation circuit having an AT crystal oscillator and generating a calibration signal, 7 the above-mentioned An oscillation control circuit 8 controls the oscillation operation of the high frequency oscillation circuit 6, and a comparison circuit 8 compares the output frequencies of the low frequency oscillation circuit 1 and the high frequency oscillation circuit 6.

The operation of the electronic timepiece with the above configuration will be explained by dividing it into three operations.

The first operation is the normal operation of the electronic watch, in which the signal from the low frequency oscillation circuit 1 passes through the correction device 2 and is applied to the clock circuit block B including the dividing path 61 and the display drive circuit 32.
It is adapted to drive the time display block 5.

The second operation is an aging correction operation, in which the temperature detection device 4 sends a signal to the oscillation control circuit 7 and the comparison circuit 8 when it detects a specific temperature 1, for example, 24°C to 25°C. The comparator circuit 8 measures the frequency difference between the high frequency oscillation circuit 6 and the low frequency oscillation circuit 1 to create aging error information, and the correction device 2 uses this aging error information. The signal of the low frequency oscillation circuit 1 is corrected by taking this information.

The third operation is a temperature correction operation, in which temperature information is directly sent from the temperature detection device 4 to the correction device 2, and the temperature information is sent directly to the correction device 2.
uses this temperature information to correct the temperature of the low frequency oscillation circuit 1.

Due to the above three operations, the correction device 2 has two functions. That is, upon receiving the aging error information,
A function that performs the same amount of correction over the entire temperature range, and a function that receives temperature information and performs different corrections for each temperature in order to flatten the quadratic frequency temperature characteristic of the low frequency oscillation circuit 1. It is a function.

In the following, the former will be referred to as an aging correction function, and the latter will be referred to as a temperature correction function.

FIG. 2 is a characteristic diagram showing the temperature characteristics due to the above-mentioned operation. The horizontal axis is temperature θ (℃), and the vertical axis is frequency deviation p
- Hail.

f indicates the temperature characteristic of the high frequency oscillation circuit 6, which has an undulation that can be called a cubic curve.

As described above, this temperature-related waviness cannot be easily removed, and therefore it has been difficult to use an AT crystal resonator as an absolute reference oscillation source. Therefore, the present invention makes it possible to ignore this waviness by referring only to a specific temperature, for example, as shown in the figure (24° C. to 25° C.).

Note that, since the high frequency oscillation circuit 6 operates only at the specific temperature, frequencies at other temperatures are shown for reference.

f indicates the frequency temperature characteristic of the low frequency oscillation circuit 1, which is a quadratic curve having an apex near room temperature.

f2 is a temperature characteristic curve that has been temperature-corrected by the temperature correction function and has a small error over a wide temperature range, and s'3 is a frequency-temperature characteristic curve when a delay occurs due to aging error. It is shown
'Difference between 2 and f3 f2-f.

is the aging error that should be corrected.

Therefore, the aging information sent from the comparison circuit 8 to the correction device 2 of the present invention is nothing but this f2-f3.

Therefore, the comparison circuit 8 has two functions. That is, there is a function to store f and -f as initial data with zero aging error in advance, and to measure f and -f3 when an operation command for the temperature detection device 4 is received.
This function determines the aging error f2-f to be corrected. In the following, the former will be referred to as the initial data storage function and the latter as the modified data determining function.

In this way, since the comparator circuit 8 is equipped with an initial data storage function and a correction data determining function, the low frequency oscillation circuit 1
Correction of the aging error, which could not be achieved only by using the Z+ excavation frequency at a specific temperature of the high frequency oscillation circuit 6, has become possible by using the Z+excavation frequency as an absolute reference.

Before going into the description of specific examples, we will add a description of the correction device 2 in FIG. 1 (.

In FIG. 1, the oscillation signal of the low frequency oscillation circuit 1 is divided into the frequency dividing circuit 3
A correction device 2 corrects the time reference signal f in a standard electronic clock oscillation/frequency division/display system that divides the frequency by 1 to obtain a time reference signal fll for timekeeping and displays the time. It has been inserted. When viewed as an electronic watch, this correction device 2 results in a time reference signal f for timekeeping,
(Actually, a correction means is selected from this point of view.The main correction means include means using a voltage-controlled oscillation circuit to directly control the oscillation frequency, and means for controlling the oscillation capacitance. There is also a means for making the frequency division ratio variable, such as means for interrupting pulses to the frequency dividing circuit.

The embodiment described next adopts as a correction means a means for switching the oscillation capacitor, which is one of the oscillation capacitor control means for directly controlling the oscillation frequency, in a time division manner and controlling the average oscillation frequency using this time division ratio. ing.

FIG. 3 is a circuit diagram showing a specific configuration of the electronic timepiece shown in FIG. 1, and FIGS. 4 and 8 are circuit diagrams of main parts of the electronic timepiece shown in FIG. The first operation, second operation, and third operation will be explained with reference to FIG. 4 and FIG. 8, respectively.

Figure 3 shows the low frequency oscillation circuit 1 and correction device 2 in Figure 1.
FIG. 2 is a circuit diagram of an electronic timepiece specifically illustrating.

In the figure, a low frequency oscillation circuit 1 and a correction device 2 together constitute a reference signal generation device 9. In the reference signal generator 9, the low frequency oscillation circuit 1 is a basic CMO8 oscillation circuit, and includes a feedback resistor 11, an oscillation inverter 12. Crystal oscillator 16% input side capacity.

14, low frequency oscillation signal f configured by output side capacitor 15
Output L.

Note that the output signal from only this basic configuration is referred to as the reference signal f,
Hail. The correction device 2 includes an aging correction circuit 21 that is supplied with an aging information signal Ss from a comparator circuit 8 and outputs an aging correction signal SA, and a temperature correction circuit that is supplied with a temperature information signal S from the temperature detection device 4 and outputs a temperature correction signal Sr. It is composed of a circuit 22 and oscillation frequency control circuits 26 and 24 which use the aging correction signal 5ATh and temperature correction signal Sr as control input signals.

Note that the oscillation frequency control circuits 26 and 24 and the correction circuit 21
and 22 constitute first and second correction means. The oscillation frequency control circuits 23 and 24 have an input side capacitor 14 and an output side capacitor 1, which are the oscillation capacitors of the low frequency oscillation circuit 1, respectively.
Similarly to 5, switching capacitors 232 and 242 are arranged respectively, and the aging correction signal SAm and the temperature correction signal Sr are respectively used as control input signals, and at the logic O of this signal, the switching capacitance is added to the oscillation capacitance to generate a low frequency oscillation signal f.
Switch elements 231 for lowering the frequency of L
．． 232.

The first operation in the above configuration will be explained. Now, the aging correction signal "A% temperature correction signal Sr is logic l
ψ, respectively.

Let ψ7 be an aging correction factor and a temperature correction factor, and for both correction factors ψ, let the difference between the low frequency oscillation frequency fL of ψGi1 and ψ−〇 be flllFAThfllWT, respectively. In the CMO8 crystal oscillator circuit of this embodiment, the frequency shift by f□ and ψ and the frequency shift by fllW7 and 97 work independently, and ψ6, ψ7,
Since the frequency shift due to can be regarded as linear, the low frequency oscillation frequency fL can be expressed as the average frequency by the following equation.

fL=f, -f□, × (to 1-) ' gw X (1-
ψ)...(1) That is, the reference low frequency oscillation frequency f1
A low-frequency oscillation frequency fL is realized by adding the aging correction term -f□,×(1-ψA) and the temperature correction term -'gwyX(1-ψ).

FIG. 4 shows the temperature detection device 4, high frequency rooting circuit 6, and oscillation control circuit 7 in FIG. Comparison circuit 8. 2 is a main circuit diagram showing a specific configuration of an aging correction circuit 21. FIG.

FIG. 4 will be explained with reference to the voltage waveform diagrams of FIGS. 5, 6, and 7.

In the temperature detection device 4, 41 is a temperature detection circuit equipped with a temperature register 40 that outputs a temperature information signal S4,
This temperature information signal S4 is T. ,T.

The temperature information value T is made up of 9 bits of . . .

T=ToX2' +T, x2'+...-T, X2
'...-...Q) Although the contents of the temperature detection circuit 41 will be described later, this temperature information value T is proportional to the temperature.

42 is 18% T4sT of the temperature information signal S4
, , T, and 〒 are input, and all input signals are the same logic -NOR
(abbreviated as FEXNOR) circuit 421.

AND which inputs the output signal of this EXNOR circuit 421 and the signal T of the temperature information signal S4, which is inverted by the inverter 422, and outputs the specific temperature i external signal sit.
This is a specific temperature detection circuit consisting of a circuit 426.

46 is a well-known set-reset flip-flop (hereinafter abbreviated as R8FF) consisting of two NOR circuits, and the cent input terminal S receives a synchronous 4-hour signal φ4. is supplied,
The reset input terminal R receives an oscillation timing signal 84, which will be described later.
5 is supplied, and the comparison time condition signal S43 is supplied from the output terminal Q.
Output.

In this application, when a signal obtained by frequency-dividing the low-frequency oscillation signal fL is used as a synchronization signal, the symbol φ indicates its frequency or period (seconds are S
, time is marked with h).

44 is an AND circuit which inputs the specific temperature condition signal 842 from the specific temperature detection circuit 42, inputs the comparison time condition signal 843 from the R8FF 43, and receives the comparison condition signal 84.
Outputs 4.

45 is R8FF, the set input terminal S is supplied with the comparison condition signal 844, and the reset input terminal R is supplied with the synchronous 64 second signal φ61. is supplied, and an oscillation timing signal 845 is output from the output terminal Q.

46 is an AND circuit, and this oscillation timing signal 54
11 and the synchronous 32 second signal φ3□ are input, and a comparison timing signal 84+1 is output. The operation of the temperature detection device 4 having the above configuration will be explained with reference to FIG.

In Fig. 5, (c) is the synchronous 64 second signal φ646,
(b) The synchronous 32-second signal φs2mhfl is the synchronous 4-hour signal (1'4 h.

) is the specific temperature condition signal S47, ... is the comparison time condition signal S43, (f) is the comparison condition signal 8441)) is the oscillation timing signal S43. (a) is the comparison timing signal S46
Hail. The temperature register 40 of the temperature detection circuit 41 is (
Synchronous 64 second signal φ64. shown in b). The temperature information value T is set at the timing of the fall of . At this time, the specific temperature detection circuit 42 detects T3, T4. T,,T,,120≦T(13
6, the specific temperature condition signal S42 is set to logic 1. Now t
As shown in f3 at time point 1 (when the synchronous 4-hour signal φ4. rises, R8FF43 is set and the comparison time condition signal 843
In the logic as shown in (e), when the specific temperature condition external signal N 842 becomes logic 1 as shown in (e), the comparison condition signal 844 rises as shown in (e). R8FF45
As a result, the oscillation timing signal 846 rises as shown in (g). The logic 1 of this oscillation timing signal 54fi resets the comparison time condition signal 843 shown in (1), and as a result, the comparison condition signal s44 shown in (1) also becomes logic 1o.
At time point 4, R8FF45 receives the synchronized 64 second signal m shown in (a).
5ss, and the oscillation timing signal 845 becomes logic 0 as shown in (g). Among the logic 1s between 12 and 14 of the oscillation timing signal 845 shown in (g), the AND circuit 46 generates a synchronous 32 second signal 96 shown in (b).
32 j is ANDed, as shown in (7) (the comparison timing signal 846 takes logic 1 at the time of t3 to t4 in the second half. (e) As shown in K<12, the comparison timing signal 846 becomes logic 0) The time condition signal 843 is t.

The logic 0 is maintained until the synchronous 4-hour signal yJ4h shown in (c) rises at time 15, 4 hours after the start.

That is, the temperature detection device 4 has a temperature information value of] 2 o4
When T<+36, the oscillation timing signal °S4. becomes logic 1 for 32 seconds at the minimum time interval of 4 hours. At the same time, the latter 16 of this oscillation timing signal S45 is outputted.
A comparison timing signal 846 that becomes logic 1 for a second is output.

The high frequency oscillation circuit 6 includes an oscillation inverter 61 and a feedback resistor 6.
2. Crystal oscillator 63, input side capacitor 64, output side capacitor 65
and a waveform shaping inverter 66, and a basic CMO8 crystal oscillation circuit that outputs a high frequency oscillation signal f.

The oscillation control circuit 7 supplies a positive power supply 71 to the positive power terminal of the oscillation inverter 61 of the high frequency oscillation circuit 6,
The inverter 72 inverts the oscillation timing signal 845 from the temperature detection device 4 and supplies it to the negative power terminal of the oscillation inverter 61.

In the oscillation control circuit 7 and the high frequency oscillation circuit 6 having the above configuration, when the oscillation timing signal 845 of logic O is now supplied from the temperature detection circuit 4, this signal is inverted by the inverter 72 and the negative Supplied to the power terminal.

As a result, both the positive power terminal and the negative power terminal of the oscillation inverter 61 become logic 1, so no power is supplied, and the oscillation operation of the high frequency oscillation circuit 6 is stopped. Conversely, when the oscillation timing signal 84111□ of logic 1 is supplied, the inverter 72 supplies logic 0 to the negative power supply terminal of the oscillation inverter 61.
As a result, power is supplied to the rooting inverter 61, and the high frequency oscillation circuit 6 oscillates and outputs the high frequency oscillation signal fII. That is, the high frequency oscillation circuit 6 is an oscillation circuit that performs an intermittent oscillation operation in which the oscillation timing signal 845 oscillates at logic 1.

The comparison circuit 8 will be explained.

Reference numeral 81 denotes a phase comparator circuit consisting of D-type F, F and constituting the phase detection means, and a low frequency oscillation signal fL is supplied from the reference signal generator 9 to the clock input terminal CL.
A high frequency oscillation signal fII is supplied from the high frequency oscillation circuit 6 to the data input terminal, and a phase signal f is output from the output terminal Q. 82 is an AND circuit, and this phase signal f,
and a comparison timing signal 846 between the temperature detection devices 4 and 4.
and outputs a phase difference pulse train signal Sat. 83
is a NOR circuit and has a synchronous 64 second signal. 48 and synchronized 32
It inputs the second signal z, 28 and outputs the phase difference clear signal 883. 84 is a phase difference counter composed of a 10-digit counter, the clock input terminal R is supplied with the phase difference pulse train signal 8B2, the reset input terminal R is supplied with the phase difference clear signal 883, and the 10-digit counter is supplied with the phase difference pulse train signal 8B2. The second output terminal Q outputs a correction code signal S84. 85
is a correction signal generation circuit, which generates the comparison timing signal 8.
A signal obtained by inverting 46 by an inverter 850 is input to the input terminal.

Input synchronous 2 signal number 2. Input the inverted signal right from the input terminal L2, and output the 1-pulse correction signal S from the output terminal Q.
82. a latch circuit 851 that outputs the 1-pulse correction signal S8,1, and an AND circuit 852 that receives the 1-pulse correction signal S8,1 and the synchronous 8 Hz signal 08 and outputs the 8-pulse correction signal S8,2;
Output terminals Q8, Q4, . . . of the phase difference counter 86
...Q7. Q, the specific phase difference signal S8,
EXNOR circuit 853 that outputs S83.3 and this specific phase difference signal S83. is input from input terminal C, the 1-pulse correction signal S8,1 is input from input terminal A, the 8-pulse correction signal S8,2 is input from input terminal B, and the output terminal Q
AB selector 8 outputs a pulse correction signal S85 from
54. Note that the latch circuit 851 and AB
The selector 854 is a well-known circuit, and the launch circuit 851
As shown in the figure, it is composed of one AND circuit and two NAND circuits, and outputs a pulse signal that becomes logic 1 from the rise of the input signal at input terminal L1 to the fall of the input signal at input terminal L2. AB selector 854 passes the input signal from input terminal A to output terminal Q when the input signal at control input terminal C is logic 1, and outputs the input signal from input terminal B when it is logic 0. It is passed through terminal Q. The operation of the comparator circuit 8 having the above configuration will be explained with reference to FIG. In FIG. 6, (a) is a synchronous 64-second signal. 4 (b) is the synchronous 32 second signal 532I
I, P'l are the phase difference clear signal 883, (E) is the comparison timing signal S40, (E) is the correction code signal S B 4,
(to) is the 1-pulse correction signal Sg++, ()l is the 8-pulse correction signal 8852, (7) is the specific phase difference signal S, 51,
(One sword has a pulse correction signal 885.
The time between t5 is 32 seconds, and the time between t3 and t4 is 1 second.

With respect to the synchronization signals shown in (a) and (b), the phase difference clear signal SSS is generated by the NOR circuit 86 as shown in ←9<1. ~t
2, the phase difference counter 84 is set and the correction code signal 884 becomes logic 0, as shown in (e).Next, from time 12 to 18, the temperature detection device 4 When the supplied comparison timing signal 846 becomes logic 1, as already explained (temperature detection device 4
The oscillation timing signal 845 is set to logic 1 at the time point 18, and as a result, the high frequency oscillation circuit 6 is in oscillation operation, so the phase comparator circuit 81 detects the phase of the high frequency oscillation signals f and I using the low and low frequency oscillation signal fL as a sampling signal. The AND circuit 82 passes this phase signal f to output a phase difference pulse train signal 882, and the phase counter 84 outputs this phase difference pulse train signal 8g2, that is, the phase, for 16 seconds from time t2 to time 18. Count the signal f. Since the phase code signal SA4 shown in (E) is the output signal of the most significant digit of the phase difference counter 84, 1
When the count number of the phase difference counter 84 is zero at time 2, it starts at logic O, when the count number reaches 512 at time '20, it is reversed to logic 1, and at time '21, an overflow occurs and the count changes from 1023 to zero. becomes logic 0.

From time t2 to time 13, the correction code signal 884 repeats the operation from t2 to time 121.

At this time, the specific phase difference signal S85. which is the output signal of the BXNOR circuit 853. becomes logic 1 when the count number of the phase difference counter 84 is 504 or more and less than 520, as shown in FIG. When the content of the phase difference counter 84 at time point 13 is defined as the phase difference count number CP, it is expressed by the following equation.

C,=[fPx 16 ]-2”Xn,...
...131 Here, n is the number of overflows of the phase difference counter 84 between t2 and t13, and "[]" indicates the number of overflows of the phase difference counter 84, and "[]" indicates the digitization.The correction code signal 884 shown in (E) at time 18 and the specific phase difference signal S6,3 shown in (a)
is determined to be unique by this phase difference count number CP, and 1,
The logic 1 of the phase difference clear signal SSS shown at time ←J is maintained until the phase difference counter 84 is reset. (E) and (2) are examples of CP=515, n,=1, and 13
At this point, the correction code signal 884 is a logic 1 due to 5124Cp.
, the specific phase difference signal s ass becomes logic "1" because 504≦CP<520.

Next 1. At the time point from to 14, the launch circuit 851 outputs one pulse to the one-pulse correction signal 81151 shown in (f), and the AND circuit 852 outputs eight pulses to the eight-pulse correction signal S8,2 shown in (g). Ru.

The AB selector 854 selects the specific phase difference signal 5a as shown in the example.
When aa is logic 1, the 1-pulse correction code s shown in (to)
g5+ is shown as a concave (pulse correction signal 885).Conversely, when the specific phase difference signal S8,3 is logic O, (g)
The 8-pulse correction signal SaS 1 shown in
85.

That is, the comparator circuit 8 compares the phases of the high frequency oscillation signal fl and the low frequency oscillation signal fL with the logic 1 of the comparison timing signal 846, and outputs the aging information signal S8 according to the phase difference count number C2, which is the counted value. A correction code signal 884, which is a signal corresponding to the correction direction as the aging information signal S8, is determined, and a pulse correction signal SaS, which is a signal corresponding to the correction amount as the aging information signal S8, is also output. Specifically, the correction code signal 884 is 5124C
.

The pulse correction signal 885 is a pulse signal consisting of one pulse when 504≦C and <520, and eight pulses in other cases.

The aging correction circuit 21 will be explained.

211 is the latch circuit explained in the comparison circuit 8,
An inverted signal 23 of the synchronous 2-second signal is supplied to the input terminal L2, an inverted signal 1□ of the synchronous 512 Hz signal is supplied to the input terminal L2, and an aging correction synchronous signal generator is output from the output terminal Q. do.

212 is a switching storage circuit consisting of a 10-digit up-down counter, and the clock input terminal is connected to the comparison circuit 8.
A pulse correction signal 886 is supplied from the comparator circuit 8, and a correction code signal 884 is supplied from the comparator circuit 8 to the up-down mode input terminal Up.

This amplifier down counter 212 functions as a logic 1 counter (this is a well-known counter) in which the input signal from the up/down mode input terminal UD and the output signal from the output terminal Q of the switching circuit 215, which will be described later. Synchronization 5
12Hz signal, input 12 and count up signal S2
1. Output.

214 is a 10-digit presettable counter and serves as a data input terminal. , DI, . . . D9 is the output terminal Q of the switching storage circuit 212. ,Ql,...
The output signal of the aging correction synchronization signal G is supplied to the preset enable terminal PE.

is supplied, the count amplifier signal 5213 is supplied to the clock input terminal Q, and an overflow signal S, 14 is outputted from the output terminal Q. This presettable counter 214 is activated by data input terminals Do, DI, . . .
This counter is preset to 9 input signals. 215 is a switching circuit consisting of a trigger type FF, and the clock input terminal 2 receives the overflow signal S2.
, 4 are supplied, and the aging correction synchronization signal G is supplied to the input terminal R of the reset circuit 7). This trigger type P
F is a known FP used in a counter that inverts an output signal at the fall of an input signal from a clock input terminal. The operation of the aging correction circuit 21 having the above configuration will be explained using FIG. 7.

In Figure 7, (a) is a synchronous 512Hz signal, 1□
, (b) is the aging correction synchronous signal reactor, , ti is the count up signal "'213%" is the overflow signal 821 (power is the aging correction signal S,

The period from tl to 13 is 2 seconds.

In response to the synchronous 512 Hz signal 1512 shown in (A), the launch circuit 211 outputs an aging correction synchronization signal G which is a pulse signal with a 2 second period as shown in (B).

At time 11, as shown in (b) (aging correction signal door).

When becomes logic 1, the value of the switching storage circuit 212 is preset in the presettable counter 214. Also, the switching FF 215 is reset, the aging correction signal S becomes logic 0 as shown in (e), and the AND circuit 213 thereafter converts the synchronous 512 Hz signal shown in (a) into the count amplifier signal 82.3 as shown in eJ. . The brisetta pull counter 214 will overflow at the next Kt2)
When the overflow signal 5214 falls as shown in (E), the switching FF 215 outputs the aging correction signal S as shown in (E).
Invert A to logic 1. As a result, from now on, AND circuit 2
13 does not pass the synchronous 512Hz signal (the count amplifier signal 8213 becomes logic 0, as shown in (c)).t.

The two second operation from t to 13 is repeated from t onwards. Here, the count number of the amplifier down counter, that is, the storage content of the switching storage circuit 212 is assumed to be Cc. At this time, the time from t to t is (1024-Cc) 1512
becomes. As defined previously, the aging correction factor ψ is the time proportion of the aging correction signal SA at logic 1, tl to t3 is 2 seconds, and t2 to t.

Since the aging correction signal SA becomes logic 1 (as shown in the figure), the following equation holds true.

91+, =cc/1024'...
...(4) The frequency of the low frequency oscillation signal fL is corrected by the aging correction factor ψ, as already mentioned in (1) above.
As shown in the equation, equation (4) shows that the aging correction factor ψ is changed by changing the storage content Cc of the switching storage circuit 212, and as a result, the low frequency oscillation frequency fL can be corrected. Memory content C of this switching memory circuit 212
The change in c is performed by adding or subtracting the logic 1 or logic 0 of the correction code signal SS+ by the number of pulses of the pulse correction signal 885.

That is, the aging correction circuit 21 receives the correction code signal 8 which is the aging information signal S output from the comparison circuit 8.
84 and the switching storage circuit 21 by the pulse correction signal SSS.
In addition to correcting the memory content Cc of 2, the low frequency oscillation signal fL is adjusted to (1
) is corrected using the formula.

The aging correction operation, which is the second operation of the electronic timepiece having the above configuration, will be explained.

Now, when the temperature detection device 4 detects a specific temperature at which the temperature information value T is 1204T (136), the oscillation timing signal 845 is set to logic 1 for 32 seconds at intervals of at least 4 hours. The oscillation circuit 6 is put into an oscillation operating state.

Also, the temperature detection device 4 sets the comparison timing signal 846 to logic 1 for the latter 16 seconds of this 32 seconds. Thereby, the comparison circuit 8 compares the low frequency oscillation signal fL with the high frequency oscillation signal f8 of the high frequency oscillation circuit 6 which is already oscillating.

Here, the high frequency oscillation frequency fII and the low frequency oscillation frequency f
L will be explained.

When the standard value of the high frequency oscillation frequency flI is set as fH, = 4194304 (fiz), and the standard value of the low frequency oscillation frequency fL is set as fL, = 32768 (Hz), the following relationship exists between f□ and fL. To establish.

fH,=fL, X m...
6) m is a positive integer, and is 128 in this example.

Since this fHm is an integral multiple of fLll, the comparison between the low frequency oscillation frequency fL and the high frequency oscillation station and wave number fH is performed by phase comparison.

The phase comparison circuit 81 of the comparison circuit 8 is a circuit that performs this phase comparison, and the frequency of the phase signal f, which is its output signal, is expressed by the following equation.

f,=l f H−f L xm l
(6) The standard high frequency oscillation frequency fH of the oscillation frequency fII of the high frequency oscillation circuit 6
The frequency deviation dH with respect to m is set by the following formula.

n is the number of overflows of the phase difference counter 84 explained in the comparison circuit 8, and in this embodiment, the high frequency oscillation frequency f takes an appropriate positive integer value within a range that does not deviate greatly from its standard value 'H8. .

At this time, under the condition of fL#fL, the absolute value symbol in equation (6) is unnecessary, and when using equation (6), equation q), and equation (3) above, the phase difference count number C2 is calculated by the following equation. Hail.

CP=[(fH, -fLxm)×16]+512...
(8) The case where fL>fL, will be explained.

At this time, from equation (8), CP 512 is obtained, and the comparator circuit 8 outputs the correction code signal S8. is logical 0, and if CP≧504, then 1
The pulse signal is C, (8 if 504) (a pulse signal is output as the pulse correction signal S0, and the aging correction circuit 21 subtracts the switching storage content CC by the number of pulses.

As a result, the aging correction factor ψ decreases according to the above equation (4), and the low frequency oscillation frequency fL is corrected so as to eventually decrease according to the above equation 0). That is, the low frequency oscillation frequency f
The positive deviation of L from the standard frequency fL8 is corrected in the negative direction by the aging correction operation.

Conversely, when fLll becomes f, C7≧520, the correction code signal S, 4 becomes logic 1, and the switching memory content C becomes
If CP is 520, plus 1, if C7≧520, plus 8
and ψ according to equation (4).

increases, and is corrected so that fL increases according to equation (1). In other words, the standard frequency fL□ of the low frequency oscillation frequency fL
A negative deviation with respect to , will be corrected in the positive direction by the aging correction operation.

Therefore, the low frequency oscillation frequency fL is corrected to the standard low frequency oscillation frequency fz,s by the aging correction operation. That is, from equation (5), the low frequency oscillation frequency fL is the standard high frequency oscillation frequency fI1. Therefore, from equation (7), the accuracy becomes the high frequency oscillation frequency fII.

In addition, in one aging correction operation, the number of pulses of the pulse correction signal is l depending on whether or not the position difference count number C2 falls within the range of ±8 with respect to the standard value 512 when fL=fL. and is limited to 8. The amount of change in the switching memory content Cc is determined by this number of pulses, and the equation (4) (
The amount of correction of the low frequency oscillation frequency fL is determined by equation 1).

Therefore, the aging correction operation limits and limits the amount of correction in one correction operation.

This limitation on the amount of correction is because the amount of correction due to one malfunction is limited against aging correction malfunctions, such as malfunctions due to a difference between the temperature detected by the temperature detection device 4 and the outside temperature due to a sudden change in external temperature. This has the effect of minimizing the impact.

In addition, the correction amount is limited to the minimum correction amount for normal aging of the low frequency oscillator circuit 1, and for a somewhat large frequency shift due to shock, etc., the correction operation with a large correction amount is performed several times. This has the effect of realizing an aging correction operation that quickly corresponds to the current state with a simple circuit that does not use an arithmetic circuit or the like.

Next, the resolution and correction width of the aging correction operation will be explained.

The time width in which the comparison timing signal 846 in the temperature detection device 4 takes logic 1 is set to the phase comparison time of 1° (1° in this embodiment).
6 seconds), and the number of digits of the phase difference counter 84 in the comparator circuit 8 is the number of digits of the phase difference counter KP (10 in this embodiment). Using this, the frequency deviation dII of the high frequency oscillation signal fY with respect to f and H8 is set by the following equation.

At this time, the phase difference count number CP is expressed by the following formula.

Cp −4(f,, −f Lxm ) x t,)−
In 1-2, '''・・・・・・・・・・・・・・・Ql In this example, equations (9) and 00) are replaced by equations C7) and [F
]).

As a result, the resolution of the comparator circuit 8 becomes 0υ, where the dPTh correction width is multiplied by the dPTh correction width. In this example, approximately dP = o, o 149 (pP), h, = 15.26 (
1 unit). Next, let the number of digits of the switching storage circuit 212 of the aging correction circuit 21 be KA (10 in this embodiment),
The period of the aging correction synchronization signal φ is set as the aging correction period "A" (2 seconds in this embodiment).

At this time, naturally, the frequency of the clock input of the presettable counter 214 and the input of the input terminal L2 of the latch circuit 211 becomes KA/tA. At this time, aging correction circuit 2
If the theoretical resolution according to 1 is dA% and the correction width is hA, then using the above equation (1), the following equation is obtained. Among these, the resolution achieved at the low frequency oscillation frequency fL is the larger of dPS and dA.

The correction width is the narrower of hP and hA. Therefore, it is desirable to set d, d, h, and hA to match, and this condition is set using CII), 03 formula and (5) formula, KA −Kp h fIIIFA = 2K”/(t
, X m)・・・・・・・・・・・・0 moat. In this example, =, =l Q, and fswh = 0.5 from t, = l 6, m = 128.
(Hz). However, even if there is some variation in f□, it will affect the resolution and correction width of the aging correction, but it will not cause any problem to the aging correction operation itself.

FIG. 8 is a main circuit diagram showing a specific configuration of the temperature detection device 4 and temperature correction circuit 22 in FIG. 3.

Conventionally, many methods have been proposed in which a temperature sensor is mounted on a small electronic device such as an electronic watch to sense the temperature while the device is being carried and to perform temperature compensation on the time reference signal f8. It goes without saying that any of these methods may be used for temperature correction in the present application. In this embodiment, temperature information is captured as a digital value, and furthermore, this digital temperature information is converted into a monolithic IC without using any external parts such as a temperature sensing element such as a thermistor or another crystal resonator. This is obtained by using a temperature detection circuit that is

That is, FIG. 8 will be explained with reference to the temperature characteristic diagram of FIG. 9.

In the temperature detection device 4, the temperature detection circuit 41 receives T from the temperature register 40. , To, . . . T8 is supplied to the temperature correction circuit 22. The temperature correction circuit 22 generates a temperature correction signal ST from this temperature information signal S4.
is created and supplied to the frequency control circuit 24.

In the temperature detection circuit 41, 47 is a temperature-sensitive oscillation circuit, and 481
482 is a gate signal counter that counts the output signals of the temperature sensitive oscillation circuit 47 by a predetermined number; and 482 is set to a predetermined value in advance and then counts for the same period as the gate signal counter 481 to generate the reference signal generator 9. A comparison counter %40 for counting the output signal fL or its frequency-divided signal is a temperature register that stores the final value of this comparison counter 482, 483 is a control circuit for controlling the above-mentioned components in time series,
Reference numeral 491 denotes a numerical value A storage circuit that supplies a numerical value A to be counted to the gate signal counter 481, and numeral 492 a numerical value B storage circuit that supplies a numerical value B that should be set in advance to the comparison counter 482.

In the present embodiment, the numerical value storage circuits 491 and 492 are constructed of storage circuits within the same IC, but selective connection patterns provided outside the IC chip may also be used.

The operation of the temperature detection circuit 41 having the above configuration will be explained.

As mentioned above, the temperature detection circuit 41 is a circuit that sets the temperature information value T in the temperature register 40 at the falling edge of the synchronous 64-second signal, and the control circuit 486 synchronizes with this to set the temperature at fixed time intervals, that is, every 64 seconds. It controls the detection operation.

When the time to detect this temperature is reached, the gate signal counter 481 and the comparison counter 482 each input a value A1.
Numerical value B is set, then gate signal counter 48.1
is a signal P with a period τ whose signal source is the temperature-sensitive oscillation circuit 47.
is input, and the current counter τ inputs a synchronized C signal φ of frequency fc whose signal source is the reference signal generator 9. is input.

Further, the comparison counter 482 starts counting operation from the state where the count content is the numerical value B, and is controlled by the control circuit 48B so that it operates for exactly the same period as the gate signal counter 481, and the gate signal counter 481 receives the signal P with the period τ.
It stops at τ time when A number of A pieces have been counted, that is, after A×τ seconds. During this period, the comparison counter 482 overflows several times, but the last remaining value becomes the temperature information value T, and the control circuit 483VC controls the synchronous 64-second signal φ64. It is transferred to and stored in the temperature register 40 at the timing of the fall of . The temperature information value T obtained as a result can be calculated using the following formula.

T-[AXrXfa] + B2
tX ``t・'' Q41 Here, Kt is the number of bits of the temperature register 40, and nt is the number of overflows minus 0.

Next, the temperature-sensitive oscillation circuit 47, which is a temperature sensor of the temperature detection circuit 41, will be explained.

471 is a temperature-sensitive constant voltage circuit whose output voltage V varies linearly according to the ambient temperature; 472 is a voltage-current conversion circuit that converts the output voltage into a current;

476 is a ring oscillation circuit connected in series to the voltage-current conversion circuit 472; 474 is an oscillation signal waveform shaping circuit;
475 is a frequency dividing circuit that makes the oscillation cycle an appropriate length, 476
is a switching inverter for turning on the power of each of the circuits. The operation of the temperature-sensitive oscillation circuit 47 having the above configuration will be explained.

Now, when the switching inverter 476 receives logic 1, the temperature-sensitive constant voltage circuit 471 and the voltage-current conversion circuit 47
2. Works to allow the operating current of the waveform shaping circuit 474 to pass through.

The oscillation period of the ring oscillation circuit 473 depends on the current, and the current is an n-channel F used in the voltage-current conversion circuit 472.
ET threshold voltage VTR and the temperature-sensitive constant voltage circuit 47
1 depends on the relationship between the output voltage v8. That is, as the temperature rises, the difference between vTH and V□ becomes smaller, so the current also becomes smaller and one oscillation period τ becomes longer.

It is a straight line and can be expressed by a linear equation.

τ=α×θtenτ.・・・・・・・・・・・・
...(1) However, θ represents the temperature, and τ0 represents the period τ at 0°C.

α represents the temperature coefficient.

Therefore, the temperature information value T is calculated by the following equation from equation 0(a) and equation 09.

T = (Axfcx (α×θ10τ.)]10B-2KtX
n・・・・・・・・・・・・・・・(ie In formula (16), except for the overflow ring 2 tX n t , the temperature information value T is a linear function of the temperature θ, and this −
This shows that the number of intervals can be adjusted freely by numerical values A and B.

Next, the temperature correction circuit 22 will be explained.

As shown in the figure, the temperature correction circuit 22 uses the output signal of the frequency dividing circuit 61 as a synchronization signal. The frequency dividing circuit 61 is divided into continuous frequency dividing circuits 311, 312, 616, and 614, of which 612 is a first frequency dividing circuit and 616 is a second frequency dividing circuit, each having a 7-bit configuration. The 7-bit output signal of this □ frequency divider circuit 612 is used as the first synchronization signal φIBjm.
The 7-bit output signal of the frequency dividing circuit 316 is used as the second synchronization signal φ
It is set as 2nd.

In the temperature correction circuit 22, 221 is a temperature register 40.
T, which is the lowest 7 binoto of the temperature information signal S4 from.

, To is compared with the first synchronization signal φ+st,
The 7 bits of this first synchronization signal φlet are all bits from zero to T. The pulse signal P becomes logic 1 until it matches 7 bits of To.

The first comparator circuit %222 that outputs 7 bits from To to To from the temperature register 40 and the second synchronization signal φ2nd, and this second synchronization signal φ2 is the 7 bits from zero to To to To. A second comparator circuit 226 outputs a pulse signal P which becomes logic 1 until d and d match, and 226 is TtsT, which is the signal from both comparator circuits 221 and 222 and the upper two bits of the temperature information signal S4 from the temperature register 40. , is a pulse synthesis circuit that synthesizes a temperature correction signal ST. The operation of the temperature correction circuit 22 having the above configuration will be explained.

When the value indicated by the lower 7 bits To to To of the temperature register 40 is n, and the period of the input signal of the first frequency dividing circuit 612 is 1, the output pulses P, , P, of the one-car comparator circuit 221, 222 are Each period is 128.16384, and the duty of the signal waveform, that is, the logic 1 for the period.
The time proportions of both are n/128. The pulse synthesis circuit 223 sets the temperature correction signal S2 to logic 1 when the most significant signal Ts of the temperature information signal S4 is 1. That is, the temperature correction factor ψ7 is expressed by the following equation.

ψT-1(256≦T(512)...0
7) Output the AND signal P,·P2 of P, and P2 as the temperature correction signal S7. At this time, temperature correction signal ST
The time during which the logic becomes 1 during the period of 16384 is n2, and the temperature correction factor ψ2 is as follows.

2 ψT: 6384 On the other hand, the same <Ts is logic 0 and m T? When is also logic 0, it is an AND signal of the inverted signal Tomoe of P and the inverted signal Tomoe of P.
[•H is output as the temperature correction signal S7. The time during which the temperature correction signal ST takes logic 1 during the 16384 period is (128-n)''. However, the above n has the following relationship with the temperature information value T of the temperature register 10.

n=T (Q≦T(128)n=T-1
28 (128≦T<256) Therefore, the temperature correction factor ψ7 is given by the following equation.

......................................a8 That is, the temperature correction circuit 22 calculates the temperature correction factor ψ7 shown by the formula 07)208 for the temperature information value T from the temperature register 40. This circuit outputs a temperature correction signal ST having a temperature correction signal ST.

The temperature correction operation, which is the third operation of the electronic timepiece having the above configuration, will be explained using FIG. 9.

FIG. 9 is a temperature characteristic diagram with temperature θ ("C) taken on the horizontal axis, where (a) is a temperature characteristic diagram of the reference signal generator 9, (b) is a temperature characteristic diagram of the temperature correction factor ψ7, and (C ) is a temperature characteristic diagram of the temperature information value T.The output frequency f of the reference signal generator 9
L is calculated by the above equation α). In equation (1), when the frequencies when the temperature correction factor ψ7 is 0 and 1 are fLo and fLl, respectively, fLo = fa
'gwa X (19'A) 's+++r・・
・・・・・・・・・・・・・・・09 fL I =fLO+fmWT ・・・・・・
・・・・・・・・・(201 and hail. Said (1)
) formula shows that the temperature correction factor ψ7 and the aging correction factor ψ act independently on the low frequency oscillation frequency fL. Here, in order to further discuss temperature correction, aging correction factor ψ,
is constant.

° Also, the reference low frequency oscillation frequency f, exhibits a quadratic characteristic that is upwardly convex with respect to temperature, and f□ and 'mW7 can be considered to be constant with respect to temperature. Than this.

When the apex temperature of the quadratic curve of fl is 08T, the % quadratic temperature coefficient is a, and fLo at θ2T is set to the standard low frequency oscillation frequency 'Lm, that is, 32768 Hz, fL
o, d the frequency deviation of LI with respect to this fL. %
If it is set to '1, it is expressed as a linear expression.

・・・・・・・・・・・・・・・(21)・・・・・・
・・・・・・・・・@ value. The specific example shown in the figure is θ, T = 25°C.

a ”” 0.033pPl/ “C”, dgwy
=3opIm.

In Fig. 9(a), the vertical axis shows the frequency deviation -
This is the one taken. curve d. 1 curve d1 corresponds to the above formula 00 (formula 22).Here, the temperature at which dl becomes zero is θ1
, θ, and the following equation is obtained by setting d1=0.

In the specific example, θs=5.15° and θ,=55.15°.

As shown in FIG. 9(e), the temperature information value T is θ1°θ2
are adjusted so that each becomes 0.256.

That is, the temperature information value T is adjusted according to the following equation.

In the specific example, T=4.2453xθ+2187.

The temperature information value T is adjusted to be a linear function of θ in formula (24) using the numerical values A and B in formula (161).At this time, since the temperature information value T is 9 bits, if digital errors are ignored, the 9th At this time, the temperature correction factor ψ7 becomes as shown in FIG. On the other hand, the low frequency oscillation frequency fL is obtained by substituting the equation (1) into the above equation (1) to obtain the following equation.

fL ='LO+'gwr Xψ When formula 09 and formula (c) are applied to the above formula, the frequency deviation dL of the low frequency oscillation signal fL is expressed as follows.

dL-do+d□7×ψ7・・・・・・・・・
-(251 Substituting equation 09 into this equation, the following equation is obtained.

dL2d. +'llwr (256≦T<512)
As a result, the following equation holds true.

dL2dl (256≦T(512)...
...... (To) Also, substitute the G8 formula into the t251 formula to find the next liability.

By substituting the temperature information value T of Equation 34 into this equation, the following equation is obtained.

dL=do-a(θ-θg)” (o≦T(256) After all, the following equation holds true from equation 00.

dL=0 (0≦T(256)...
...Thus, from Equation (A) and Equation (5), the low-frequency oscillation frequency deviation dL becomes as shown in Figure 9 (a). Therefore, 0≦T 256 That is, (θ1 and 0 according to Equation 231)
Temperature correction will be achieved at temperatures between 2.

The operation of the electronic timepiece according to this embodiment will be explained using FIG. 10 based on the three operations described above.

In Figure 10, the temperature θ ('C) is plotted on the horizontal axis, and ('b
) indicates the temperature characteristics of the temperature information value T.

In FIG. 10(a), song #i! do, d1% dL corresponds to the formula (2I), formula (22), and formula (C). The curve dH is a specific temperature range θ, to θ4, and the above c7
) The high frequency oscillation frequency deviation is set to be the frequency deviation when nP=4. This curve d
3 is a cubic curve as shown in the figure, so θ, to θ
When 4 is narrow, the deviation of d is very small and can be ignored. Here, this np:=4 and the specific temperature range θ to 04 will be explained.

In addition to the conditions explained in equation (7) above, n and -4 require that dII and dL be separated to some extent in order to stabilize the phase comparison operation of fH and fL, that is, dYO and dL in the comparator circuit 8, and dL Since this is based on time sharing between do and d, in the specific example, n≧2 is an absolute condition, and this value was chosen with even greater safety in mind. The specific temperature range will be explained in Fig. 10).

As mentioned above, 120≦T (136 is the specific temperature range, and by calculating backwards from the above formula (24), it is approximately θ, = 23.1°θ
,=26. ．． 9, resulting in a temperature range of about 25 degrees.

As explained above, the high frequency oscillation frequency deviation dll is set, and the low frequency oscillation frequency deviation dL is set to zero as shown in FIG. 10(a), that is, the low frequency oscillation frequency fL is set to the standard low frequency oscillation frequency fL. In this case, when the above-mentioned aging correction operation causes a deviation in the low frequency oscillation frequency deviation as shown by the curve dL' shown in the figure, it is quickly corrected to dL.

In this embodiment, for setting the high frequency oscillation frequency f and the low frequency oscillation frequency fL, a trimmer capacitor is used for the oscillation capacitance of the high frequency oscillation frequency, that is, the input side capacitor 64 or the output side capacitor 65, and a single oscillation circuit is used. Both crystal oscillators and this trimmer capacitor are the only external parts of the integrated circuit.

For this reason, after a glass-sealed crystal resonator is attached to the low frequency oscillation circuit 1, the frequency of this crystal resonator is adjusted using a laser. At this time, it is generally said that the aging of the low frequency oscillation circuit 1 becomes a little worse, but in the present application, aging is caused by the high frequency oscillation circuit 6, so there is no problem. Also, the high frequency oscillation circuit 6 adjusts the frequency using a trimmer capacitor, but the amount of adjustment is theoretically 1/2 of the aging correction width (7.631f in the specific example).
Even if you consider the allowance for this, it should be a fairly small amount.

The fact that this adjustment range is small is a good condition for realizing a highly stable high frequency oscillation circuit.

Here, another method of omitting the trimmer capacitor in the low frequency oscillation circuit 1 will be described. Using a frequency-selected crystal oscillator or using it in combination with the switching memory circuit 21
This is possible by adding 1 to the number of digits of 2 and increasing the aging correction width hA to include the low-frequency oscillation frequency fL within the aging correction width with a margin for aging.

FIG. 11 is a main circuit diagram showing another specific example of the comparator circuit 8 shown in FIG. 4.

In FIG. 11, the comparator circuit 88 is exactly the same as the comparator circuit 8 in FIG. 4 except for the addition of an initial phase difference storage circuit 86 and some accompanying changes, so only the differences due to this change will be explained. .

In the figure, in the comparator circuit 88, 86 is a 10-bit initial phase difference storage circuit, and output terminal Q. ,Qo,...
. . Q outputs the initial phase difference signal sa6.

This initial phase difference storage circuit 86 also has the numerical value storage circuit 491.
．． Similarly to 492, it may be set by a selective connection pattern provided outside the IC chip. 87 is a phase difference counter consisting of a 10-pin presettable counter, and receives 10 bits of the initial phase difference signal 886 as a data input terminal. , D7, ...D. Note that this phase difference counter 87 corresponds to the phase difference clear signal 8 in the previous specific example.
a3 is supplied from the preset enable input terminal PE as a phase difference precent signal.

Except for the above points, the comparator circuit 88 has the same configuration as the previous specific example.

In the above configuration, when the storage content of the initial phase difference storage circuit 86 is 08, the phase difference count number C1 in the equation (3) is calculated by the following equation.

C,-[f, X 16+C,]-2"Xn,
-----(281) The high frequency oscillation frequency flI given by the above equation (7) is set here by the following equation.

Here, if C is a real number such that O≦C, (1024), the phase difference count number CP is the same as the equation (8).

In reality, C8 is a digital value, so when the digital error caused by this is ignored, the same aging correction operation as in the previous embodiment is realized in this embodiment as well.

To state this from a different perspective, the high frequency oscillation signal fH is
An appropriate initial phase difference C1l is stored in the initial phase difference storage circuit 86.
When stored, it can be used as is as an aging correction signal.

This makes it possible to design the high frequency oscillation circuit 6 under optimal conditions for highly stable oscillation.

Further, in this specific example, it is possible to use only both crystal oscillators as external components of the integrated circuit.

Both of the above examples have the following advantageous features.

(2): Low frequency oscillation signal fL subjected to aging correction by aging correction factor ψ is converted to high frequency oscillation signal f.

Since the aging correction is performed by increasing or decreasing the aging correction factor ψ based on the comparison result, the aging correction can be realized without using an arithmetic circuit as described above.

■: Since the temperature-corrected low-frequency oscillation signal fL and high-frequency oscillation signal f are compared, when obtaining a high-frequency oscillator with a nearly constant frequency over a wide temperature range by screening, fL
Since the difference between and flI is constant over a wide temperature range, the temperature range of the specific temperature in aging correction can be designed to be wider, and the reliability of the aging correction operation can be improved.

(2): Comparison of both oscillation signals H and fL is performed by a counter that counts the phase difference between the two signals. This counter repeatedly overflows when the aging correction width is exceeded.

As a result, the high-frequency oscillation frequency fB only needs to be an appropriate value within a range that does not adversely affect the phase comparison operation, which reduces the process of adjusting the resonance frequency of the high-frequency resonator. This is a major manufacturing advantage.

(2): Temperature correction and aging correction can be completed in 2 seconds by the capacitance switching means pressure that directly controls the oscillation frequency of the low frequency oscillation circuit. Therefore.

It has the advantage of being able to measure the average rate in a short period of time using a commonly used rate measuring device for electronic watches.

In particular, the aging correction has the feature that the high resolution d in the phase comparison of the 00 formula can be easily realized by the correction resolution d in the capacitance switching shown in the C2 formula.

The electronic timepiece according to the present invention has significant ripple effects (it has the following advantages).

■We can provide clocks with an error of less than 1 second over a two-year period.

(2) Since the dual rate AT resonator is not required to have characteristics outside a limited temperature range, a highly accurate resonator can be manufactured at low cost.

■: The AT resonator only needs to be operated within a limited temperature range (and it does not need to be operated very frequently, so the total power consumption is very small, and only the conventional low frequency oscillation circuit The power consumption is almost the same as that of an electronic clock.

Thus, according to the electronic timepiece of the present invention, it is possible to improve the accuracy of the annual error to within 1 second with a slight increase in power consumption compared to the conventional timepiece, which has a great effect on improving the product appeal of the electronic timepiece. has.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an electronic timepiece according to the present invention. Figure 2 is the first
FIG. 3 is a frequency-temperature characteristic diagram, and FIG. 3 is a circuit diagram of an electronic timepiece showing a specific example of the present invention. 4 and 8 are circuit diagrams of main parts in FIG. 3. 5, 6, and 7 are voltage waveform diagrams in FIG. 4. FIG. 9 is a temperature characteristic diagram of FIG. 8. FIG. 10 is a temperature characteristic diagram of FIGS. 3, 4, and 8. FIG. 11 is a circuit diagram of a main part showing another specific example of the comparison circuit shown in FIG. 4. 1...Low frequency oscillation circuit, 2...Correction device, 4...Temperature detection device, 6...High frequency oscillation circuit, 7... Oscillation control circuit, 8.88... Comparison circuit. Figure 1 Figure 5 Figure 6 Figure 20t21 Figure 7 tl, t2 t3 9 Figure 8 Figure 9 Figure 1θ

Claims (1)

[Scope of Claims] (1) A low frequency oscillation circuit that generates a reference signal, a frequency dividing circuit that divides the frequency of the reference signal to create a time reference signal, and a time display means that displays the time using the time reference signal. In the electronic timepiece provided with the above, first and second correction means for correcting the time reference signal. A high frequency oscillation circuit that generates a calibration signal, a comparison circuit that compares the output signals of the low frequency oscillation circuit and the high frequency oscillation circuit, and temperature detection means are provided, and the first and second correction means are connected to the low frequency oscillation circuit, respectively. An oscillation frequency control means connected to the circuit and a correction circuit for controlling the oscillation frequency control means using signals from a comparison circuit and a temperature detection means, respectively, and temperature correction is controlled by an output signal of the temperature detection means. An electronic timepiece characterized in that the correction for secular change is controlled by the output signal of the comparison circuit. C) The oscillation frequency control means according to claim 1 is constituted by a switching capacitor connected to the oscillation capacitor of the low frequency oscillation circuit and a switch means for switching the switching capacitor. An electronic timepiece characterized in that the switch means is opened and closed by a signal from the correction circuit. (3) The oscillation frequency control means constituting the first correction means according to claim 2 is connected to the input side capacitance of the low frequency oscillation circuit, and the oscillation frequency control means constituting the second correction means An electronic clock characterized in that is connected to an output side capacitor.