JPH09326679A - Clock generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time from power supply to clock output start. SOLUTION: When a power is supplied, since the flip-flops FR1-FRm of a counter circuit 5 are reset by reset signals from a power ON reset circuit 6 and switching signals are turned to 'L', a switching circuit 4 supplies frequency divided clocks for which high-speed oscillation clocks from a high-speed oscillation circuit 2 are frequency divided to the oscillation number frequency of a low-speed oscillation circuit by a frequency divder circuit 3 to a peripheral circuit. Then, when the low-speed oscillation circuit 1 starts oscillation, the low-speed oscillation clocks are inputted to the counter circuit 5 and the counter circuit 5 counts the clock number of the low-speed oscillation clocks by the FR1-FRm. When the prescribed number is counted, since the inverted output terminal QB of the FRm is changed from 'L' to 'H', the switching signals are changed from 'L' to 'H'. Thus, the switching circuit 4 switches supply clocks to the respective peripheral circuits from the frequency divded clocks to the low-speed oscillation clocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit used in a microcontroller or the like and generating a clock of a predetermined frequency.

[0002]

2. Description of the Related Art FIG. 8 is a circuit diagram showing an example of a conventional clock generating circuit. In FIG. 8, the conventional clock generation circuit 100 has an oscillation frequency of 32.768 [kHz].
Component connecting terminals T1 and T2 to which the crystal oscillator X1 is connected, a resistor R1 inserted between T1 and T2, an inverter I1 having an input terminal connected to T1 and an output terminal connected to T2, The input terminal is connected to the output terminal of I1 and has an inverter I2 that outputs a low-speed oscillation clock from the output terminal. A clock having a frequency determined by the crystal oscillator X1 is generated and supplied to each peripheral circuit such as a microcontroller. It is a thing.

[0003]

However, in the above-described conventional clock generation circuit, the lower the oscillation frequency, the longer it takes from power-on to the start of oscillation. As in the clock generation circuit of FIG. When a low frequency clock is generated, there is a problem that it takes 1 to several tens of seconds from power-on to oscillation start. Therefore, the time from power-on to operation start of a clock-supplied microcontroller or the like. Was also subject to this constraint.

The present invention solves such a conventional problem, and an object of the present invention is to shorten the time from power-on to the start of clock output.

[0005]

In order to achieve the above object, a clock generating circuit of the present invention is a first clock which starts generating a clock of a first frequency after a lapse of a first time after power is turned on. Generating means, and second clock generating means for starting to generate a clock having a second frequency higher than the first frequency after a second time shorter than the first time has elapsed after power-on. A frequency conversion circuit for converting the output of the second clock generation means into a clock of the first frequency, and a switching circuit for selectively outputting the output of the first clock generation means and the output of the frequency conversion circuit. When the power is turned on, first, the switching circuit is caused to select the frequency conversion circuit, and after the first clock generating means starts generating the clock of the first frequency, the switching time is changed. It is characterized in that a switching control circuit for selecting the output of said first clock generating means.

According to another aspect of the clock generating circuit of the present invention, the first clock generating means has an oscillation component connection terminal, and when the oscillation component is connected to the oscillation component connection terminal, the first clock generation means cooperates with the oscillation component. It operates and oscillates to generate a clock having the first frequency.

According to another aspect of the clock generating circuit of the present invention, the second clock generating means has an oscillation component connecting terminal, and when the oscillation component is connected to the oscillation component connecting terminal, the second clock generating means cooperates with the oscillation component. It operates and oscillates to generate a clock having the second frequency.

According to a fourth aspect of the present invention, the second clock generating means is a CR oscillator circuit.

According to a fifth aspect of the present invention, in the switching control circuit, the first clock generating means includes:
After the stable generation of the clock of the first frequency, the switching circuit is caused to switch from the output of the frequency conversion circuit to the output of the first clock generating means. is there.

According to a sixth aspect of the present invention, in the clock generation circuit, the switching control circuit outputs the first clock generation means from the output of the frequency conversion circuit to the switching circuit after a lapse of a predetermined time after the power is turned on. It is characterized in that the output is switched to.

According to another aspect of the clock generating circuit of the present invention, the switching control circuit causes the switching circuit to switch from the output of the frequency conversion circuit to the output of the first clock generating means. 2. The clock generating circuit according to claim 1, wherein the first clock generating means stops the output of the clock.

Therefore, according to the present invention, when the power is turned on, the switching control circuit causes the clock from the second clock generating means whose time from power-on to the start of oscillation to be shorter than that of the first clock generating means. The switching circuit outputs the clock converted to the first frequency by the frequency conversion circuit, and the output of the switching circuit is output from the first clock generation means after the first clock generation means starts oscillation. By switching to the clock,
It is possible to shorten the time from power-on to the start of clock output. At this time, the output clock of the first clock generation means and the output clock of the frequency conversion circuit need not be in phase.

According to another aspect of the clock generating circuit of the present invention, by using the CR oscillator that starts oscillation almost at the same time when the power is turned on, as the second oscillating component, a crystal oscillator or the like is used. Furthermore, the time from power-on to clock output start can be shortened. In addition, CR
An oscillator generally has a lower precision (large variation) in the oscillation frequency than a crystal oscillator or the like, but the output clock of the second clock generating means is used because the oscillation of the first clock generating means after the power is turned on. There is no problem because it is a short time to start.

According to another aspect of the clock generating circuit of the present invention, the switching control circuit causes the switching circuit to output the clock from the first clock generating means while outputting the clock of the second clock generating means. Power consumption can be reduced by stopping.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment FIG. 1 is a circuit configuration diagram of a clock generation circuit showing a first embodiment of the present invention. The clock generation circuit shown in FIG.
Crystal oscillator X1 with oscillation frequency of 32.768 [kHz]
(1st oscillation component) is connected,
After a few tens of seconds, the low-speed oscillation circuit 1 (first clock generating means) starts oscillating at the oscillation frequency (first frequency) of the crystal oscillator X1, and the oscillation frequency is 2 ^{n of the} crystal oscillator X1.
A crystal oscillator X2 (second oscillation component) having a frequency twice (n is a positive integer) is connected, and 5 to 1 from power-on
After 0 [ms], the high-speed oscillation circuit 2 (second clock generating means) that starts oscillation at the oscillation frequency (second frequency) of the crystal oscillator X2 and the output clock of the high-speed oscillation circuit 2 (hereinafter referred to as high-speed oscillation) A frequency divider circuit 3 (frequency conversion circuit) that divides the clock signal by 2 ^n, a power-on reset circuit 6 that outputs a reset signal when the power is turned on, and a low level (hereinafter, It is determined that the low-speed oscillation circuit 1 has started steady oscillation (stable oscillation) by outputting a switching signal of "L"), starting counting the number of low-speed oscillation clocks, and counting a predetermined number. Then, the counter circuit 5 that changes the switching signal from "L" to a high level (hereinafter referred to as "H"), and the output clock of the frequency dividing circuit 3 when the switching signal is "L". Clock (hereinafter, referred to as a divided clock) is supplied as a supply clock to each peripheral circuit of the microcontroller, and when the switching control signal is "H", the output clock of the low speed oscillation circuit 1 (hereinafter, referred to as the low speed oscillation clock). ) Is supplied to each peripheral circuit. The counter circuit 5 and the power-on reset circuit 6 form a switching control circuit. In addition, low-speed oscillation circuit 1
Is the same as the conventional clock generation circuit shown in FIG.

The low-speed oscillation circuit 1 includes component connection terminals T1 and T2 to which the crystal oscillator X1 is connected, and T1-T2.
A resistor R1 inserted in between, an input terminal connected to T1, an inverter I1 connected to an output terminal to T2, and an input terminal connected to an output terminal of I1 and an inverter outputting a low-speed oscillation clock from the output terminal. I2 and. Further, the high-speed oscillation circuit 2 has component connection terminals T3 and T4 to which the crystal oscillator X2 is connected, a resistor R2 inserted between T3 and T4, an input terminal connected to T3, and an output terminal connected to T4. Inverter I3 and input terminal I3
And an inverter I4 which is connected to the output terminal of and outputs the high-speed oscillation clock from the output terminal.

The frequency divider circuit 3 has n D-flip-flops F each having a data input terminal D and an inverting output terminal QB connected to each other.
1, F2 ... Fn, a high-speed oscillation clock is input to the trigger input terminal CK of the first-stage F1, and each C of F2 to Fn.
K is connected to the QB of the flip-flop in the previous stage, and the QB of Fn in the final stage outputs a divided clock obtained by ^{dividing the} high-speed oscillation clock by 2 ⁿ .

The power-on reset circuit 6 has a resistor R3 whose one end is grounded, and a capacitor C1 whose one end is connected to the other end of R3 and whose other end is connected to the power supply VDD. Then, the reset signal of "H" is output from the connection point of R3 and C1.

The counter circuit 5 is connected to a 2-input AND gate A1 to which a low-speed oscillation clock is input and a switching signal is inverted, and a data input terminal D and an inverted output terminal QB (m is a positive number). (Integer of) D-flip-flops FR1, FR2 ... FRm with reset terminal
And a reset signal is input to the reset terminals R of the flip-flops FR1 to FRm, the trigger input terminal CK of the first-stage FR1 is connected to the output terminal of A1, and FR2-
Each CK of FRm is connected to the QB of the flip-flop in the previous stage, and the switching signal is output from the QB of FRm in the final stage. Here, the number of stages m of the flip-flop FR is determined in consideration of the transient oscillation period of the low-speed oscillation circuit 1 (the period from the start of oscillation to the start of steady oscillation). For example, if the low-speed oscillation circuit 1 starts steady oscillation by the 15th clock of the low-frequency oscillation clock after starting oscillation, m = 5
As a result, the switching signal is changed from "L" to "H" at the 16th clock of the low frequency oscillation signal.

The switching circuit 4 includes a 2-input AND gate A2 to which the low-speed oscillation clock and the switching signal are respectively input, and a 2-input AND gate A3 to which the divided clock is input and the switching signal is inverted. , Has a two-input OR gate O1 whose input terminals are respectively connected to the output terminal of A2 and the output terminal of A3, and supplies a clock from the output terminal of O1 to each peripheral circuit of the microcontroller.

Next, the operation of the clock generation circuit shown in FIG. 1 will be described. FIG. 2 is a timing chart of the clock generation circuit shown in FIG. FIG. 2 shows a case where the high-speed oscillation circuit 2 outputs a high-speed oscillation clock having a frequency twice that of the low-speed oscillation clock, and the frequency dividing circuit 3 divides this frequency by 2 (when n = 2). The counter circuit 5 has five flip-flops (m = 5). It is assumed that the low-speed oscillation circuit 1 shifts from transient oscillation to steady oscillation during the period from time t2 to time t3.

In FIG. 2, when the power is turned on at time t0, the power-on reset circuit 6 first resets the reset terminals R of the flip-flops FR1 to FRm of the counter circuit 5.
A reset signal is input to reset FR1 to FRm, and the counter circuit 5 is initialized. Therefore, the switching signal is "L", and the switching circuit 4 is set to output the clock from the frequency dividing circuit 3.

Next, at time t1 (5 to 10 [m from time t0
[s] later), the high-speed oscillation circuit 2 starts oscillating, and a high-speed oscillation clock (not shown) is supplied to the frequency dividing circuit 3,
The frequency dividing circuit 3 supplies the divided clock obtained by dividing the high-speed oscillation clock by 2 to the switching circuit 4, and the divided clock is supplied from the OR gate O1 to each peripheral circuit via the AND gate A3 of the switching circuit 4. To be done.

Next, at time t2 (1 to several tens of seconds after time t0), the low-speed oscillation circuit 1 starts oscillation, and the low-speed oscillation clock triggers the flip-flop FR1 via the AND gate A1 of the counter circuit 5. It is input to the input terminal CK, and the flip-flops FR1 to FRm count the number of low-speed oscillation clocks.

Next, at time t3, when the 16th clock of the low-speed oscillation clock is input to the counter circuit 5, the inverting output terminal QB of the flip-flop FRm changes from "L" to "H", so that the switching signal becomes "H". It changes from "L" to "H". As a result, the inverting input terminal of the AND gate A1 becomes "H", and thereafter, the low speed oscillation clock is not input to FR1. Therefore, thereafter, the switching signal is held at "H". The switching circuit 4 switches the clock supplied to each peripheral circuit from the divided clock to the low-speed oscillation clock, and the low-speed oscillation clock outputs the AND gate A.
It is supplied from the OR gate O1 to the peripheral circuit via 2.

As described above, according to the first embodiment,
When the power is turned on, the switching circuit 4 supplies the divided clock of the high-speed oscillation clock to the peripheral circuits, and the counter circuit 5 detects the oscillation start of the low-speed oscillation circuit 1 to determine the number of low-speed oscillation clocks. After counting several times and the low-speed oscillation circuit 1 starts steady oscillation (stable oscillation),
By switching the supply clock to the low-speed oscillation clock by the switching circuit 4, 5 to 10 [m
[s], the clock supply to the peripheral circuits can be started.

The supply clock may be switched from the divided clock to the low-speed oscillation clock when the low-speed oscillation clock is detected without waiting for the start of the steady oscillation of the low-speed oscillation circuit 1.

Second Embodiment FIG. 3 is a circuit configuration diagram of a clock generation circuit showing a second embodiment of the present invention. The clock generation circuit shown in FIG.
In the clock generation circuit of FIG. 1, a high-speed oscillation circuit 7 is provided instead of the high-speed oscillation circuit 2.

The high-speed oscillator circuit 7 is the high-speed oscillator circuit 2 of FIG.
In place of the inverter I3, a two-input AND gate A4 having an input terminal and an inverting input terminal, the input terminal being connected to the component connecting terminal T1, and the switching signal being inputted to the inverting input terminal is provided. is there.

Next, the operation of the clock generation circuit shown in FIG. 3 will be described. FIG. 4 is a timing chart of the clock generation circuit shown in FIG. In FIG. 4, time t0
From time to time t3, the operation is the same as that of the clock generation circuit in FIG.

At time t3, the low-speed oscillation clock 1
When the sixth clock is input to the counter circuit 5, the inverting output terminal QB of the flip-flop FRm changes from "L" to "H", so that the switching signal changes from "L" to "H". As a result, the inverting input terminal of the AND gate A1 becomes "H", and thereafter, the low speed oscillation clock is not input to FR1. Therefore, thereafter, the switching signal is held at "H". The switching circuit 4 switches the clock supplied to each peripheral circuit from the divided clock to the low-speed oscillation clock, and the low-speed oscillation clock is supplied as a generated clock from the OR gate O1 to the peripheral circuits via the AND gate A2. Further, since the inverting input terminal of the AND gate A4 of the high-speed oscillation circuit 7 becomes "H", thereafter,
The high-speed oscillation circuit 7 stops the output of the high-speed oscillation clock, so that the divided clock is not output either.

As described above, according to the second embodiment,
The switching signal is input to the inverting input terminal of the AND gate A4 of the high-speed oscillation circuit 7, and the switching circuit 4 is switched to the low-speed oscillation circuit 1
The power output can be reduced by stopping the clock output of the high-speed oscillation circuit 7 by the AND gate A4 while outputting the clock from.

Third Embodiment FIG. 5 is a circuit configuration diagram of a clock generation circuit showing a third embodiment of the present invention. The clock generation circuit shown in FIG.
In the clock generation circuit of FIG. 1, a counter circuit 8 is provided instead of the counter circuit 5.

The counter circuit 8 is the counter circuit 5 of FIG.
In the above, the number of stages of the flip-flop FR is m '(m' is a positive integer), and the divided clock is input to the input terminal of the AND gate A1 instead of the low-speed oscillation clock. Here, the number of flip-flop FR stages m ′
Is determined in consideration of the time from power-on to the start of oscillation of the low-speed oscillation circuit 1. For example, if the low-speed oscillation circuit 1 starts oscillating about 30 clocks of the divided clock after the power is turned on, m ′ = 6 is set and 3 of the divided clocks are set.
The switching signal is changed from "L" to "H" at the second clock.

Next, the operation of the clock generating circuit shown in FIG. 5 will be described. When the power is turned on, the high-speed oscillation circuit 2 starts oscillating, and the high-speed clock is supplied to the frequency dividing circuit 3, the frequency dividing circuit 3 switches the frequency dividing clock of the high-speed oscillation clock to the switching circuit 4 and the counter circuit 8. To the AND gate A1. This divided clock is input to the trigger input terminal CK of the flip-flop FR1 via the AND gate A1, and the flip-flops FR1 to FRm ′ count the number of divided clocks. The 32nd clock of the divided clock is the counter. When input to the circuit 8, the inverting output terminal QB of the flip-flop FRm 'changes from "L" to "H", so that the switching signal changes from "L" to "H". The following operation is the same as that of the clock generation circuit of FIG.

As described above, according to the third embodiment,
When the power is turned on, the switching circuit 4 supplies the divided clock of the high-speed oscillation clock to the peripheral circuits, the counter circuit 8 counts a predetermined number of divided clocks, and the low-speed oscillation circuit 1 oscillates. After the start, by switching the supply clock to the low-speed oscillation clock by the switching circuit 4, 5 to 10 [ms] after the power is turned on.
Then, the clock supply to the peripheral circuits can be started.

A high-speed oscillation clock instead of the divided clock is input to the AND gate A1 of the counter circuit 8 to change the number of flip-flops FR from the power-on to the low-speed oscillation circuit 1.
It may be set in consideration of the time until the oscillation starts.

Further, the flip-flop F of the counter circuit 8
The number of stages of R may be set in consideration of the time from power-on to the start of steady oscillation of the low-speed oscillation circuit 1 so that the supply clock is switched after the low-speed oscillation circuit 1 starts steady oscillation. .

Fourth Embodiment A clock generation circuit according to a fourth embodiment is the clock generation circuit of FIG. 1, except that the high-speed oscillation circuit 9 shown in FIG. 6 is provided in place of the high-speed oscillation circuit 2.

The high-speed oscillation circuit 9 has component connection terminals T3-T.
4, a resistor R4 is inserted in place of the resistor R2 of FIG. 1, and the crystal oscillator X2 of FIG. 1 is replaced by connecting a capacitor C2 having one end grounded to T3 and a capacitor C3 having one end grounded. Is connected to T4. This R4, C
Reference numerals 2 and C3 constitute a CR oscillator that oscillates at a frequency of 2 ⁿ times that of the crystal oscillator X1 of the low-speed oscillation circuit 1 and can start oscillation almost at the same time when the power is turned on. The operation of this clock generating circuit is the same as that of the clock generating circuit of FIG. Here, the CR oscillator has a lower oscillation frequency accuracy than the crystal oscillator X2, but the output clock of the high-speed oscillation circuit 9 is used for a short time from power-on to the start of steady oscillation of the low-speed oscillation circuit 1. So no problem.

As described above, according to the fourth embodiment,
The crystal oscillator X2 of Fig. 1 is used as the oscillator component of the high-speed oscillator.
Instead, by using a CR oscillator that starts oscillation almost at the same time as power-on, the time from power-on to clock output start can be further shortened.

The high-speed oscillator circuit 9 shown in FIG.
The high-speed oscillation circuit 10 shown in may be used. This high-speed oscillation circuit 10 is similar to the high-speed oscillation circuit 9 in that the component connection terminal T
3 and T4 are removed and capacitors C2 and C3 are built in.

[0043]

As described above, according to the present invention, when the power is turned on, the switching control circuit causes the second clock generation time shorter than the first clock generation means from the power-on until the oscillation start. The switching circuit outputs the clock obtained by converting the clock from the means to the first frequency by the frequency conversion circuit, and the output of the switching circuit is changed to the first clock after the first clock generating means starts oscillation. By switching to the output clock of the clock generating means, there is an effect that the time from power-on to start of clock output can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a clock generation circuit showing a first embodiment of the present invention.

FIG. 2 is a timing chart of the clock generation circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a clock generation circuit showing a second embodiment of the present invention.

FIG. 4 is a timing chart of a clock generation circuit showing a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a clock generation circuit showing a third embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of a high-speed oscillator circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit configuration diagram of another high-speed oscillation circuit according to the fourth embodiment of the present invention.

FIG. 8 is a circuit configuration diagram showing an example of a conventional clock generation circuit.

[Explanation of symbols]

1 Low-speed oscillation circuit 2, 7, 9, 10 High-speed oscillation circuit 3 Dividing circuit 4 Switching circuit 5, 8 Counter circuit 6 Power reset circuit X1, X2 Crystal oscillator T1-T4 Component connection terminals R1-R4 Resistors I1-I4 Inverter C1 to C3 capacitors A1 to A4 AND gates F1 to Fn, FR1 to FRm, FRm ′ flip-flop O1 OR gate

Claims (7)

[Claims] 1. A first clock generating means for starting generation of a clock of a first frequency after a lapse of a first time period after turning on the power source, and a first clock period after the power source is turned on, which is shorter than the first time period. After a lapse of time of 2, the second clock generating means for starting to generate the clock of the second frequency higher than the first frequency, and the output of the second clock generating means to the clock of the first frequency. A frequency converting circuit for converting, a switching circuit for selecting and outputting the output of the first clock generating means and the output of the frequency converting circuit, and when the power is turned on, the frequency converting circuit is first provided in the switching circuit. And a switching control circuit for causing the switching circuit to select the output of the first clock generation means after the first clock generation means starts to generate the clock of the first frequency. The clock generation circuit with. 2. The first clock generating means has an oscillation component connecting terminal, and when the oscillation component is connected to the oscillation component connecting terminal, the first clock generating means oscillates in cooperation with the oscillation component, The clock generation circuit according to claim 1, wherein the clock generation circuit generates a clock having a frequency of. 3. The second clock generating means has an oscillation component connection terminal, and when the oscillation component is connected to the oscillation component connection terminal, the second clock generation means oscillates in cooperation with the oscillation component, The clock generation circuit according to claim 1, wherein the clock generation circuit generates a clock having a frequency of. 4. The clock generation circuit according to claim 1, wherein the second clock generation means is a CR oscillation circuit. 5. The switching control circuit, wherein the first clock generating means starts stable generation of the clock of the first frequency, and then the switching circuit is instructed from the output of the frequency conversion circuit. 2. The clock generation circuit according to claim 1, wherein switching to the output of the clock generation means 1 is performed. 6. The switching control circuit causes the switching circuit to switch from the output of the frequency conversion circuit to the output of the first clock generation means after a predetermined time has elapsed after the power is turned on. The clock generation circuit according to claim 1, wherein: 7. The switching control circuit causes the switching circuit to switch from the output of the frequency conversion circuit to the output of the first clock generating means, and then causes the first clock generating means to clock. 2. The clock generation circuit according to claim 1, wherein the output of the clock is stopped.