JPH051129Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a clock generator, and more particularly to a clock generator for a microcomputer that includes a built-in oscillation circuit using a piezoelectric element such as ceramic or crystal.

[Conventional technology]

FIG. 3 is a block diagram of a conventional clock generator for a microcomputer that incorporates an oscillation circuit using a piezoelectric element. FIG. 4 is a waveform diagram showing signal waveforms at each point in FIG. Referring to both figures, when standby signal D is at low level,
That is, before T41, capacitors 1 and 2,
The oscillation circuit composed of a piezoelectric resonator 3 such as a ceramic oscillator or a crystal oscillator, an inverter 4, and a feedback resistor 6 has stopped its oscillation operation, and the transformer transmission gate 5 is conductive at point A. is fixed at low level. Furthermore, since the trans-mission gate 7 is rendered non-conductive, almost no current flows through the oscillation circuit, resulting in a standby state. At this time, the binary flip-flops 11, 12, 13, 20, and 21 are each reset, and the E point goes to low level.
The F points are each fixed at a high level.

When the standby signal D becomes high level after T41, the trans-mission gate 5 becomes non-conductive, the trans-mission gate 7 becomes conductive, and the oscillation circuit starts oscillating. However, the oscillation immediately after the start of oscillation is unstable;
The oscillation amplitude is also small (see Figures 4A and B). If the output signal of the oscillation circuit in this state is used as a clock for a clock generator such as a microcomputer, malfunction may occur. For this reason,
It is necessary to inhibit the output of the output clock B of the oscillation circuit until the oscillation circuit reaches a stable oscillation state with a large amplitude by the NAND gate 17.

On the other hand, receiving the output clock B of the oscillation circuit (see Figure 4G), the binary flip-flop 1
1, 12, 13, 20, 21 start frequency division, and eventually at the timing of T42, NAND gate 1
The flip-flop composed of transistors 4 and 15 is inverted, and point E becomes high level. At this time
The NAND gate 17 outputs to F a signal having the same phase as the output signal B of the oscillation circuit. After T42, the oscillation amplitude of the oscillation circuit has grown sufficiently and is stable, so that it can supply a stable clock as a clock generator for microcomputers and the like.

[Problem that the invention attempts to solve]

The above-mentioned conventional clock generator has the disadvantage that the frequency divider circuit that counts the time from when the oscillation circuit starts oscillating until it stabilizes requires a large number of elements.

The purpose of this invention is to reduce the number of elements in the frequency divider circuit by adding a circuit that prevents the frequency divider circuit from operating while the oscillation amplitude of the oscillator grows to a certain level. Our goal is to provide the following.

[Means for solving problems]

The clock generator of the present invention includes: an oscillation circuit that performs oscillation by connecting a piezoelectric element to the input and output of an inverter; a Schmitt trigger circuit that receives the same signal as the input signal of the inverter; The device includes a frequency dividing circuit that frequency divides the output of the Schmitt trigger circuit, and a switch circuit that starts sending out an oscillation signal based on the output of the frequency dividing circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a waveform diagram showing signal waveforms at each point in FIG. In the figure, the Schmitt trigger circuit 9 has a hysteresis characteristic in which the rising input threshold hold voltage and the falling threshold hold voltage are different, and basically outputs a signal having the same phase as the input signal. The input A of the Schmitt trigger circuit 9 is the same as the input signal of the inverter 4 of the oscillator circuit, and the output signal C of the Schmitt trigger circuit 9 is connected to the clock input of the first stage flip-flop 11 of the frequency dividing circuit. .

After T21, the clock input signal A gradually grows, but during the period from T21 to T22, the rising input threshold of the Schmitt trigger circuit 9
Since the hold voltage is not reached, the output signal C of the Schmitt trigger circuit 9 remains at a low level. After passing T22, the waveform at point A exceeds the rising and falling threshold hold voltages of the Schmitt trigger circuit 9, and the frequency dividing circuit constituted by flip-flops 11, 12, and 13 starts frequency division. Then, at timing T23, point E becomes high level, and NAND gate 17
outputs a signal having the same phase as the output signal B of the oscillation circuit to F.

[Effect of idea]

As explained above, the present invention uses the signal on the input side of the inverter of the oscillation circuit as input to the Schmitt trigger circuit, divides the output of the Schmitt trigger circuit, and uses the divided output to release the standby mode wait. By doing this, if the oscillation has not grown sufficiently and the input amplitude of the Schmitt trigger circuit is small, the frequency divider circuit will not perform frequency division, and the oscillation will have grown sufficiently and the input amplitude of the Schmitt trigger circuit will become large. Since the frequency dividing circuit performs frequency division after the frequency dividing circuit has been set, the number of stages of the frequency dividing circuit can be reduced and the circuit can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the clock generator of the present invention, FIG. 2 is its waveform diagram, and FIG.
The figure is a block diagram of a conventional clock generator, and FIG. 4 is its waveform diagram. 1, 2... Capacitor, 3... Piezoelectric vibrator,
4... Inverter, 5, 7... Transmission gate, 6... Feedback resistor, 9... Schmitt trigger circuit, 11, 12, 13... Binary flip-flop, 14, 15, 17...
NAND gate.

Claims (1)

[Scope of utility model registration request] An oscillation circuit that performs oscillation by connecting a piezoelectric element to the input and output of an inverter, a Schmitt trigger circuit that receives the same signal as the input signal of the inverter, and a Schmitt trigger circuit that divides the output of the Schmitt trigger circuit. What is claimed is: 1. A clock generator comprising: a frequency divider circuit, and a switch circuit that starts sending out an oscillation signal based on the output of the frequency divider circuit.