JP3345209B2 - Multiplier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplying circuit, and more particularly, to a simple circuit which is suitable for use as an IC and has low power consumption.
The present invention relates to a multiplying circuit that can obtain a double-speed clock.

[0002]

2. Description of the Related Art Generally, in a digital circuit or the like, an oscillation circuit for obtaining a clock or the like oscillates by connecting a multivibrator or an inverter via a multi-stage CR circuit. When the oscillation frequency increases, an inverter, a ceramic vibrating element, a capacitor, and the like are used. A clock can be obtained by using such an oscillation circuit.However, when a demodulation circuit or a modulation circuit is constituted by a digital circuit, a double-speed clock is often required in addition to the basic clock. Absent. In some circuits, a low oscillation frequency signal to a higher oscillation frequency signal may be required. In such a case, a frequency multiplier circuit is usually used. By overdriving the varactor element, it is possible to generate harmonics and multiply the frequency, but simply, by combining a delay circuit with a predetermined amount of delay, a flip-flop, and a logic circuit, etc. realizable.

[0003]

As the delay circuit, a delay logic element or a CR delay circuit is used. However, when the delay amount varies, there is a drawback that the phase of a clock at twice the speed of the input clock becomes inaccurate. is there. In order to avoid such a situation, it is possible to provide an oscillation circuit having a high-frequency oscillation element and divide the frequency by a frequency divider to obtain a clock of a predetermined frequency. The problem is that the consumption increases and the high frequencies act as noise on the surrounding circuits. Furthermore, an oscillation element and a capacitor having a large capacity have a drawback that they become external components when integrated. SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem of the prior art, and to provide a multiplier circuit which can obtain a double speed clock suitable for IC integration with a simple circuit and low power consumption. It is in.

[0004]

SUMMARY OF THE INVENTION In order to achieve the above object, a multiplying circuit according to the present invention is characterized in that two pulses having a duty of substantially 50% and mutually opposite in phase are inverted from an input signal. A pulse generation circuit to generate these two
First and second switch circuits that are turned on / off alternately in response to one pulse, first and second constant current circuits provided downstream of the first and second switch circuits, respectively, A capacitor provided between a line on the first constant current circuit side of the switch circuit and a line on the second constant current circuit side of the second switch circuit; There is provided a comparator which inverts one of the input signals so as to have the same phase relationship as the input phase of the other and receives a signal of both terminal voltages at each input.

[0005]

As described above, by charging and discharging both terminal voltages of the capacitor using the constant current circuit through the switch circuit which turns on / off with almost 50% duty, the linearity of the original input signal is improved. Can generate a waveform having a phase difference of 180 ° over a phase width of approximately 180 °,
The signals are superimposed by inverting one of them and continuously applying the respective ramp waveforms to the comparator at every 180 ° phase to obtain a sawtooth wave having a frequency twice as high as a constant discharge ramp, thereby substantially substantially. It is possible to obtain a clock with a double speed of 50% duty. As a result, it is possible to obtain a simple multiplying circuit having a small number of elements, a small variation in clock phase, and suitable for IC.

[0006]

1 is a block diagram mainly showing a multiplying circuit to which the present invention is applied, and FIG. 2 is a waveform diagram for explaining the multiplying operation. In FIG. 1, reference numeral 1 denotes a multiplication circuit, and a differential comparator (COM) 2 receives a clock from a clock generation circuit 3 at an input terminal 1a. The comparator 2 receives one signal from the clock input signal (see FIG. 2A).
A pair of pulses having a phase difference of 80 ° (see FIGS. 2 (b) and 2 (c))
And sends them to the charging / discharging circuit 5 of the capacitor 4.

The charging / discharging circuit 5 compares a ramp waveform signal of the terminal A among the ramp voltage signals generated by charging / discharging generated at the terminals A and B by charging / discharging of the capacitor 4 with a comparator 6.
To send to. Further, it sends the ramp waveform signal at the terminal B to the comparator (COM) 6 via the inverting amplifier 6a. At this time, the slope waveforms of the terminals A and B differ from each other by 180 ° according to the phase of the input pulse. When one has a ramp waveform, the other terminal is fixed at a constant voltage.

The comparator 6 is also a differential comparator similar to the comparator 2, in which the voltage signal at the terminal A of the capacitor 4 is applied to the reference terminal (-phase input), and the inverted voltage signal is applied to the voltage signal at the terminal B. To the signal input terminal (+ phase input). As a result, the comparator 6
Generates a pulse corresponding to the signal level of the other signal based on one signal at every 180 ° in accordance with the phase of the input signal. Thereby, a double clock is generated and output from the output terminal 1b.

Here, the charge / discharge circuit 5 is connected to a power supply line Vcc.
A first series circuit 5a of a transistor Q1 and a constant current source I1 connected between the power supply line Vcc and the ground GND.
2 and a second series circuit 5b of a constant current source I2,
A capacitor 4 is connected between the connection points of these transistors and the constant current source. The transistor Q1 has its base receiving the non-inverting pulse from the comparator 2, its collector-emitter side is connected to the power supply line Vcc and the terminal of the capacitor 4, and the transistor Q2 has its base 180 ° out of phase with the comparator 2 at the base. A pulse on the different inversion side is received, and its collector-emitter side is connected to the power supply line V.
cc and the remaining terminals of the capacitor 4.

Here, the charging / discharging operation of the capacitor 4 and the operation of generating the output signal will be described with reference to FIG. 2. The input clock is (a), and the phase of (b) and (c) is Two pulse signals differ by 180 °. When these pulse signals turn ON / OFF the transistors Q1 and Q2 of the series circuits 5a and 5b, the voltage at the terminal A of the capacitor 4 is charged and discharged by the constant current source according to the ON / OFF. d), and the voltage at the terminal B similarly changes as in (e).

The change in the terminal voltage of the capacitor 4 will be described from the case where the transistor Q1 is on and the transistor Q2 is off. First, when the transistor Q1 is turned on and the transistor Q2 is turned off, The terminal A of No. 4 is set to a predetermined level lower than the power supply line Vcc by a certain voltage, and maintains that value. At this time, since the charge of the capacitor 4 is held, the terminal B rises by a fixed voltage. Next, since the charge of the capacitor 4 flows through the constant current source I2, the terminal B of the capacitor 4 gradually decreases at a constant discharge gradient. During this time, the clock is inverted, the transistor Q1 is turned off, and the transistor Q2 is turned on. As a result, the voltage at the terminal B returns to the original constant value, and the voltage at the terminal A follows the same course as described above. As a result, the terminal A
Changes as shown in (d), and the voltage at the terminal B changes as shown in (e).

As a result, the output of the inverting amplifier 6a becomes (e)
Is inverted (f). Therefore, the signals of (d) and (f) are input to the input of the comparator 6, respectively, so that as shown in (g), the pulse having a frequency twice that of the input signal (a) is input. The signal is output to the output terminal 1b.

As can be understood from the description of this embodiment, according to the present invention, a signal having a constant discharge gradient is obtained for an input signal (pulse) of substantially 50% duty as an input signal. Generates a clock at a double speed of substantially 50% duty. For this purpose, the capacitor 4 is charged and discharged with a constant current I. Here, assuming that discharging is performed from the terminal voltage V of the capacitor 4 toward the ground level, and assuming that the discharging time is t and the capacitance of the capacitor 4 is C, these relationships are expressed by the following equations. It / C = V Assuming that the clock cycle of the input signal is T, the output waveform of (g) generated from the description of the waveforms from (a) to (g) in FIG. Similarly, the pulse width has a relationship of T / 4 from the relationship of 50% duty with respect to the clock period T. Therefore, assuming that the period of the input clock is f, the following relational expression holds between the input clock and the generated double-speed clock. f = I / 4CV where C is the capacitance of the capacitor 4, V is the terminal voltage at points A and B, and I is the current value of the constant current circuit. Although the constant current sources I1 and I2 are constant current sources, they may be used as variable constant current sources and the width of the generated double-speed clock pulse may be adjusted to absorb variations in elements. . Further, by cascading a plurality of such circuits, a multiplying circuit of a multiple of 2, such as quadruple speed and octuple speed, can be configured.

As described above, the comparators 2 and 6 in the embodiment use a differential comparator to simultaneously generate two pulses whose phases are different from each other by 180 °. A configuration in which a pulse is generated and the other pulse is generated by the inverting amplifier may be used. In the embodiment, the terminal B side of the capacitor 4 is inverted and input to the + terminal of the comparator 6.
By inverting the terminal A side of the capacitor 4, the comparator 6
The same operation can be performed by exchanging the input terminals A and B so that the input signals of the comparator 6 have the same phase relationship with each other. For example, the same phase input relationship as the (+) input side through the inverting amplifier for the (-) input, or conversely, as in the embodiment, the (-) input through the inverting amplifier through the inverting amplifier (- ) The same phase input relationship as the input. Also,
In the embodiment, the bipolar transistor is used as the switch circuit. However, this is for high-speed switching, and may be, for example, an analog switch such as a transmission gate, and it is not always necessary to use the bipolar transistor. . In addition, it goes without saying that the input from the clock generation circuit of the embodiment may be simply input from outside, not from the clock generation circuit.

[0015]

According to the present invention, the voltage at both terminals of the capacitor is reduced by approximately 50% duty by using a constant current circuit.
By charging / discharging through a switch circuit for N / OFF, almost 180 degrees with a good linearity gradient to the original input signal.
It is possible to generate a waveform having a phase difference of 180 ° over a phase width of °, invert one of the waveforms, and continuously apply the respective gradient waveforms to the comparator at every 180 ° phase, thereby superimposing the signals. As the input signal, a sawtooth wave having a frequency twice that of the input generated every 180 ° is obtained,
As a result, it is possible to substantially obtain a clock having a duty of about 50%. As a result, the number of elements is small,
It is possible to obtain a simple multiplying circuit with little variation in the clock phase and suitable for IC. Further, since the circuit scale is small, power consumption is also reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram mainly showing a frequency multiplier to which the present invention is applied;

FIG. 2 is a waveform diagram for explaining the multiplying operation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Clock control circuit, 2, 6 ... Comparator, 3 ... Clock generation circuit, 4 ... Capacitor, 5 ... Charge / discharge circuit, 6
a: Inverting amplifier.

Claims (1)

(57) [Claims] 1. A pulse generating circuit for generating two pulses of substantially 50% duty and mutually opposite phases from an input signal, and a first pulse generator which is turned on / off alternately in response to these two pulses. And a second switch circuit, first and second constant current circuits provided downstream of the first and second switch circuits, respectively, and the first switch circuit side of the first switch circuit. And a capacitor provided between the line of the second switch circuit and the line on the side of the second constant current circuit, and inverting either one of the signals of the voltage at both terminals of the capacitor to obtain the other input phase. And a comparator having the same phase relationship as above and receiving at both inputs the signals of the two terminal voltages.