JPH08228132A - Multiplier circuit - Google Patents

Abstract

PURPOSE: To provide a double-speed clock suitable for making into IC by inverting one of signals at voltages at both the terminals of a capacitor, providing the same phase relation as the other input phase and receiving the signals at the voltages at both the terminals with a comparator. CONSTITUTION: A pair of pulses, for which the phases are made different at 180 deg. each other, are generated from the input signal of a clock by a comparator 2 and sent to a charging/discharging circuit 5 of a capacitor 4. The circuit 5 sends an inclined waveform signal, which is generated by charging/discharging the capacitor 4, to a comparator 6 and sends the inclined waveform signal of a terminal B through an inverted amplifier 6a to the comparator 6. Then, the voltage signal of a terminal A of the capacitor 4 is received at a reference side terminal and the inverted voltage signal of the voltage signal of the terminal B is received at a signal input terminal. Then, the comparator 6 generates the pulse corresponding to the other signal level while defining one side as a reference for each 180 deg. corresponding to the phase of the inputted signal. Thus, the double-speed clock is generated and that is outputted from an output 1b at double speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier circuit, and more particularly, it is a simple circuit and is suitable for use as an IC and has low power consumption.
The present invention relates to a multiplication circuit capable of obtaining a double speed clock.

[0002]

2. Description of the Related Art Generally, in a digital circuit or the like, an oscillation circuit for obtaining a clock or the like is connected with a multivibrator or an inverter via a multi-stage CR circuit to oscillate. When the oscillation frequency becomes high, an inverter, a ceramic vibrating element, a capacitor, etc. are used. A clock can be obtained by using such an oscillation circuit, but when a demodulation circuit or a modulation circuit is composed of a digital circuit, in addition to the basic clock, a double-speed clock is rarely needed. Absent. Also, in some circuits, a low oscillation frequency signal to a higher oscillation frequency signal may be required. In such a case, a frequency multiplication circuit is usually used. By overdriving the varactor element, it is possible to generate harmonics and frequency-multiply it, but simply by combining a delay circuit with a predetermined delay amount, a flip-flop, and a logic circuit, etc. realizable.

[0003]

The delay circuit uses a delay logic element or a CR delay circuit. However, if the delay amount varies, the phase of the double-speed clock becomes inaccurate with respect to the input clock. is there. In order to avoid such a situation, it is possible to provide an oscillating circuit having a high-frequency oscillating element and divide the frequency by a frequency dividing circuit to obtain a clock of a predetermined frequency, but the circuit scale becomes large, and There is the problem of increased consumption and high frequencies acting as noise on the surrounding circuits. Further, the oscillation element and the capacitor having a large capacity have a drawback that they become external parts when integrated into an IC. An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a multiplication circuit which can obtain a double speed clock suitable for an IC with a simple circuit and low power consumption. Especially.

[0004]

The characteristics of the multiplier circuit of the present invention for attaining such an object are that two pulses, which are substantially 50% in duty and opposite in phase from each other, are inverted from an input signal. Pulse generator circuit to generate and these 2
First and second switch circuits which are alternately turned on / off in response to one pulse, first and second constant current circuits respectively provided downstream of the first and second switch circuits, and a first Any one of a capacitor provided between the line on the first constant current circuit side of the switch circuit and the line on the second constant current circuit side of the second switch circuit, and a signal of both terminal voltages of this capacitor. It is provided with a comparator that inverts one of them and makes them have the same phase relationship as the input phase of the other and receives the signals of both terminal voltages at their respective inputs.

[0005]

As described above, the constant current circuit is used to charge and discharge the voltage of both terminals of the capacitor through the switch circuit which is turned on / off at a duty of about 50%, so that a gradient having good linearity with respect to the original input signal is obtained. , It is possible to generate a waveform with a 180 ° phase difference over a phase width of approximately 180 °,
One of them is inverted, and the respective ramp waveforms are continuously applied to the comparator at every 180 ° phase so that the signals are overlapped to obtain a sawtooth wave having a frequency twice as high as a constant discharge ramp. A double speed clock with a duty of 50% can be obtained. As a result, it is possible to obtain a simple multiplier circuit having a small number of elements and a small variation in the clock phase, which is suitable for an IC.

[0006]

1 is a block diagram centering on a multiplication circuit to which the present invention is applied, and FIG. 2 is a waveform diagram for explaining the multiplication operation. In FIG. 1, reference numeral 1 is a multiplication circuit, and a differential comparator (COM) 2 receives a clock from a clock generation circuit 3 at an input terminal 1a. Comparator 2 outputs the clock input signal (see Figure 2 (a))
A pair of pulses with a phase difference of 80 ° (see Fig. 2 (b) and (c))
Are generated and sent to the charging / discharging circuit 5 of the capacitor 4.

The charge / discharge circuit 5 compares the slope waveform signal at the terminal A among the slope voltage signals generated at the terminals A and B by the charge / discharge of the capacitor 4 with the comparator 6
Send to. Further, the ramp waveform signal at the terminal B is sent to the comparator (COM) 6 via the inverting amplifier 6a. The inclined waveforms of the terminals A and B at this time are different from each other by 180 ° depending on the phase of the input pulse. Further, when one has a ramp waveform, the other terminal is fixed to a constant voltage.

The comparator 6 is also a differential comparator similar to the comparator 2, and the voltage signal at the terminal A of the capacitor 4 is applied to the reference side terminal (-phase input) and the voltage signal at the terminal B is an inverted voltage signal thereof. To the signal input terminal (+ phase input). As a result, the comparator 6
Generates a pulse corresponding to the signal level of the other with respect to one as a reference every 180 ° according to the phase of the input signal. As a result, a doubled clock is generated and output from the output terminal 1b.

The charging / discharging circuit 5 has a power supply line Vcc.
And the first series circuit 5a of the constant current source I1 and the transistor Q1 connected between the ground and the ground GND, and the transistor Q also connected between the power supply line Vcc and the ground GND.
2 and a second series circuit 5b of a constant current source I2,
The capacitor 4 is connected between the connection point of these transistors and the constant current source. The transistor Q1 receives a pulse on the non-inverted side from the comparator 2 at its base, and its collector-emitter side is connected to the power supply line Vcc and the terminal of the capacitor 4, and the transistor Q2 has its base 180 ° out of phase from the comparator 2 described above. Receiving different pulses on the inversion side, the collector-emitter side receives the power supply line V
It is connected to cc and the remaining terminals of the capacitor 4.

The charging / discharging operation of the capacitor 4 and the output signal generating operation will now be described with reference to FIG. 2. The inputted clock is (a), which is the phase of (b) and (c) by the comparator 2. Two pulse signals differ by 180 °. These pulse signals turn on / off the transistors Q1 and Q2 of the series circuits 5a and 5b, and the voltage of the terminal A of the capacitor 4 is charged / discharged by the constant current source according to this ON / OFF. As shown in (d), the voltage at the terminal B also changes as shown in (e).

The change in the terminal voltage of the capacitor 4 will be described from the time when the transistor Q1 is on and the transistor Q2 is off. First, when the transistor Q1 is on and the transistor Q2 is off, the capacitor The terminal A of No. 4 is set to a predetermined level lower than the power supply line Vcc by a constant voltage and maintains the value. At this time, since the electric charge of the capacitor 4 is held, the terminal B rises by a certain voltage. Next, at the terminal B of the capacitor 4, since the charge charged in the capacitor 4 flows through the constant current source I2, it gradually decreases with a constant discharge gradient. During that time, the clock is inverted, the transistor Q1 is turned off, and the transistor Q2 is turned on. As a result, the voltage at the terminal B returns to the original constant value, and this time the voltage at the terminal A follows the same process as described above. As a result, terminal A
Changes as shown in (d), and the voltage at the terminal B changes as shown in (e).

As a result, the output of the inverting amplifier 6a is (e)
It becomes a waveform like (f) which is the inversion of. Therefore, since the signals (d) and (f) are input to the input of the comparator 6, respectively, as shown in (g), a pulse having a frequency double that of the input signal (a) is input. The signal is output to the output terminal 1b.

By the way, as can be understood from the description of this embodiment, in the present invention, a signal having a constant discharge slope is obtained with respect to an input signal (pulse) having substantially a duty of 50%. Thereby substantially generating a double speed clock with a duty of about 50%. Therefore, the capacitor 4 is charged and discharged with the constant current I. Here, assuming that the terminal voltage V of the capacitor 4 is discharged toward the ground level, and the discharge time is t and the capacity of the capacitor 4 is C, these relationships are as follows. It / C = V When the clock cycle of the input signal is T, the output waveform of (g) generated from the description of the waveforms of (a) to (g) of FIG. Similarly, with respect to the clock cycle T, the pulse width is T / 4 because of the duty of 50%. Therefore, when the cycle of the input clock is f, the following relational expression holds with the generated double speed clock. f = I / 4CV where C is the capacitance of the capacitor 4, V is the terminal voltage at points A and B, and I is the current value of the constant current circuit. Further, although the constant current sources I1 and I2 are constant current sources, they may be set as variable constant current sources so that variations in elements can be absorbed by adjusting the width of the generated double speed clock pulse. . Further, by multiplying and connecting such circuits in a plurality of stages, it is possible to construct a multiplier circuit of a multiplier of 2 such as 4 × speed and 8 × speed.

As described above, the comparators 2 and 6 in the embodiment use the differential comparators to simultaneously generate the pulses whose phases are different by 180 °. The configuration may be such that a pulse is generated and the other pulse is generated by the inverting amplifier. In the embodiment, the terminal B side of the capacitor 4 is inverted and input to the + side terminal of the comparator 6,
Inverting the terminal A side of the capacitor 4, the comparator 6
The same operation can be performed by switching the input terminals of A and B so that the input signals of the comparator 6 are in phase with each other. For example, the same phase input relationship as the (+) input side is provided for the (-) input through the inverting amplifier, or conversely, as in the embodiment, the (+) input is provided through the inverting amplifier (- ) Is it the same phase input relationship as the input? Also,
In the embodiment, the bipolar transistor is used as the switch circuit, but this is for performing high-speed switching, and for example, an analog switch such as a transmission gate may be used, and the bipolar transistor is not necessarily used. . Further, it goes without saying that the input from the clock generation circuit of the embodiment need not be from the clock generation circuit, but only the clock may be input from the outside.

[0015]

According to the present invention, the voltage at both terminals of the capacitor is reduced to about 50% by using a constant current circuit.
By charging / discharging via the switch circuit that turns on / off, the linearity is approximately 180 with respect to the original input signal.
Waveforms that are 180 ° out of phase over a phase width of ° can be generated, one of which is inverted and each ramped waveform is continuously added to the comparator at every 180 ° phase to overlay the signals, As the input signal, obtain a sawtooth wave with a frequency twice that of the input generated every 180 °,
As a result, a double speed clock with a duty of about 50% can be obtained. As a result, the number of elements is small,
It is possible to obtain a simple multiplication circuit suitable for integration into an IC with little variation in the clock phase. Moreover, since the circuit scale is small, power consumption is also reduced.

[Brief description of drawings]

FIG. 1 is a block diagram centering on a multiplication circuit to which the present invention is applied.

FIG. 2 is a waveform diagram for explaining the multiplication operation.

[Explanation of symbols]

1 ... Clock control circuit, 2, 6 ... Comparator, 3 ... Clock generation circuit, 4 ... Capacitor, 5 ... Charge / discharge circuit, 6
a ... Inverting amplifier.

Claims (1)

[Claims] 1. A pulse generation circuit for generating two pulses having mutually opposite phases with substantially 50% duty, which are mutually inverted from an input signal, and a first ON / OFF circuit which is alternately turned ON / OFF according to these two pulses. And a second switch circuit, first and second constant current circuits provided downstream of the first and second switch circuits, respectively, and the first constant current circuit side of the first switch circuit. Of the capacitor provided between the line of the second switch circuit and the line of the second switch circuit on the side of the second constant current circuit, and inverting either one of the signals of the terminals of the capacitor to input the other input phase. And a comparator that receives the signals of the voltage of both terminals at the respective inputs in the same phase relationship as.