JP3136736B2 - Oscillator circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit, and more particularly to stabilization of an oscillation frequency.

[0002]

2. Description of the Related Art As a basic configuration of a conventional oscillation circuit, there is one shown in FIG. 4 using an inverter and a capacitor. The inverter 13 is connected to a potential VDD via a first constant current source 16 and a predetermined potential V
Connected to ss. The connection point b between the two capacitors 11 and 12 is connected to the output terminal of the inverter 13, the other end of the capacitor 11 is connected to the input terminal a of the inverter 13, and the other end of the capacitor 12 is connected to the predetermined potential Vss. The inverters 14 and 15 form a positive feedback circuit.

Assuming that the potential VDD is a high potential and the potential Vss is a low potential, the capacitances of the capacitors 11 and 12 are equal, and the threshold level V2 of each of the inverters 13 to 15 is exactly intermediate between the high potential V3 and the low potential V1. The operation will be described with reference to FIG. In the figure, (a) is an input terminal a,
(B) shows the waveform at the connection point b. First, in the initial state, the potential 25 at the connection point b between the capacitors 11 and 12 is at zero potential V1. When the voltage VDD is applied, the input terminal a of the first inverter 13 is at a low potential, so that the output terminal of the first inverter 13 is connected to the first constant current source 16. Through this, a constant output source current Iob is supplied to capacitors 11 and 12 as a charging current. Thereby, the potential Sb of the connection point b of the capacitors 11 and 12 is obtained.
Rises linearly from the low potential V1 toward the threshold level V2 as in Sb1.

When the voltage exceeds the threshold level V2, the outputs of the second and third inverters 14 and 15 are inverted. The output of the third inverter 15, that is, the potential Sa of the input terminal a of the inverter 13 is inverted like Sa1, and becomes the high potential V3. At the time of this inversion, the potential Sb at the connection point b is at the threshold voltage V2. Since the capacitors 11 and 12 have the same capacitance,
Due to the voltage dividing ratio, the potential Sb at the connection point b immediately after the inversion is "threshold voltage V2" + "half of the high potential V3",
That is, the voltage Sb2 becomes equal to the high potential V3.

Since the potential Sa of the input terminal a has become high, the output terminal of the first inverter 13 is connected to the second constant current source 17. The first from capacitors 11 and 12
A constant sink current Isb flows through the second constant current source 17 through the inverter 13 of FIG. 3, and the potential of the connection point b decreases linearly as in Sb3. When the potential Sb at the connection point b falls below the threshold voltage V2, the outputs of the second and third inverters 14 and 15 are respectively inverted, and the output of the third inverter 15, that is, the potential of the input terminal a is Sa.
It reverses to a low potential V1 as shown in FIG. This returns to the initial state. By repeating the above, the circuit continues to oscillate.

[0006]

However, in such a conventional oscillating circuit, when the capacitance values of the capacitors 11 and 12 fluctuate due to manufacturing errors or deviate from the set values due to environmental changes, the output source current of the inverter 13 or the The time from the start of charging and discharging by the output sink current until the terminal voltage Sb of the capacitors 11 and 12 gradually rises or falls, and exceeds the threshold voltage of the inverters 14 and 15 and the output signal is inverted. It will change. As a result, there is a problem that the oscillation frequency fluctuates due to variation in the capacitance value of the capacitor.
Therefore, the present invention has been made in view of such conventional problems,
An object of the present invention is to provide an oscillation circuit in which the oscillation frequency is kept stable even when the capacitance value of the capacitor varies.

[0007]

SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a first inverter having a first, second and third capacitors formed on the same substrate and having an output terminal connected to the first capacitor. A circuit, first current control means for flowing a predetermined value of current according to the terminal voltage of the first capacitor, and second current control for flowing a predetermined value of current according to the terminal voltage of the first capacitor Means, a high potential voltage is supplied from a high potential voltage source via the first current control means, and a low potential voltage is supplied from a low potential voltage source via the second current control means. A second inverter circuit to which the third capacitor is connected, an input terminal connected to an output terminal of the second inverter circuit, and an output terminal connected to input terminals of the first and second inverter circuits; Between the input terminal and the output terminal. Of the capacitor was assumed to have a buffer connected.

[0008]

When the capacitance of the second and third capacitors fluctuates, for example, in a direction larger than a set value due to manufacturing variations, the capacitance of the first capacitor formed on the same base also fluctuates to a larger value. Then, the charge / discharge gradient of the first capacitor becomes gentler, and the charge or discharge current value controlled by the first or second current control means based on the terminal voltage of the first capacitor becomes higher. The change in the time constant due to the increase in the capacitance value of the third capacitor is canceled. Therefore, the oscillation frequency does not fluctuate due to the variation in the capacitance value of the capacitor.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing an overall outline, having first, second, and third capacitors 34, 38, and 39 formed on the same base, and an output terminal connected to the first capacitor 34. First inverter circuit 31
And the second terminal whose output terminal is connected to the third capacitor 39.
And an inverter circuit group 40 as a buffer connected to the output terminal of the second inverter circuit 35. The second inverter circuit 35 has a first current control means 36 for controlling the output source current so as to correspond to the terminal voltage of the first capacitor 34, and the output sink current of the second inverter circuit 35 A second current control means 37 for controlling the voltage corresponding to the terminal voltage of the first capacitor 34 is connected to the first inverter circuit 31. The first inverter circuit 31 has a first constant voltage for holding its output source current at a predetermined value. A current source 32, and a second constant current source 33, which also holds the output sink current of the first inverter circuit at a predetermined value.
And are connected. The inverter circuit group 40 constitutes a feedback circuit whose output is connected to each input terminal of the first and second inverter circuits 31 and 35 and the output of the second inverter circuit which is the input of the inverter circuit group 40 is positively fed back. A second capacitor 38 connects between the input terminal and the output terminal of the inverter circuit group 40.

FIG. 2 shows the details of the above circuit. The high potential voltage VDD and the low potential voltage Vss are supplied to power supply terminals 81 and 82. The P-type MOS transistors 32a and 32b form a current mirror circuit, function as a first constant current source 32, and supply an output source current Ioj to the first capacitor 34 via the P-type MOS transistor 31a. The N-type MOS transistors 33a and 33b also form a current mirror circuit, function as the second constant current source 33, and supply an output sink current Isj to the first capacitor 34 via the N-type MOS transistor 31b. P type M
The OS transistor 31a and the N-type MOS transistor 31b form a first inverter circuit 31.

The P-type MOS transistor 36a is the first current control means 36, and the N-type MOS transistor 37a is the second current control means 36.
Function as current control means 37 of the P-type MOS
Output source current Iok is applied to capacitors 38 and 39 via transistor 35a and N-type MOS transistor 35b.
And an output sink current Isk. P-type MOS transistor 35a and N-type MOS transistor 35b form a second inverter circuit 35. The output source current Iok is supplied when the terminal voltage Sj of the first capacitor 34 is equal to or lower than the threshold level V2.
Decreases as the value increases. The output sink current Isk is supplied when the terminal voltage Sj of the first capacitor 34 is equal to or higher than the threshold level V2, and its value decreases as the voltage Sj decreases.

The P-type MOS transistor 41a and the N-type MOS transistor 41b are connected to the third inverter circuit 4
1. P-type MOS transistor 42a and N
Type MOS transistor 42b is connected to the fourth inverter circuit 4
Constituting No. 2. The third and fourth inverter circuits form an inverter circuit group 40 as a buffer, and form a positive feedback circuit.

Next, the operation will be described with reference to FIG. In the figure, (a) shows the terminal voltage Sj of the capacitor 34, (b)
Represents the potential of the connection point k, (c) represents the potential of the input terminal h of the inverter circuit 31, and (d) represents the potential of the capacitor 34.
(E), the terminal voltage when the capacitance value of
(F) shows the potential Sh of the connection point k and the input terminal h when the capacitance values of the capacitors 38 and 39 increase. In the initial state, the first to third capacitors 3
The charges of 4, 38 and 39 are 0, and the potentials of the input terminal h of the first inverter circuit 31 and the terminal j of the first capacitor 34 are also 0. When the power supply voltage VDD is applied, since the potential of the input terminal h is 0, the P-type MOS transistor 31a of the first inverter circuit 31 turns on,
The output terminal is connected to the first constant current source 32. That is, the output source current Ioj is supplied from the P-type MOS transistor 32b to the capacitor. This value is kept constant. The terminal voltage of the first capacitor 34 is S
It increases linearly like j1. This terminal voltage Sj is P
It is supplied to each gate of the type MOS transistor 36a and the N-type MOS transistor 37a.

In the initial state, since the potential of the input terminal of the second inverter circuit 35 is also 0, the P-type MOS transistor 35a of the second inverter circuit 35 turns on,
The output terminal is connected to the P-type MOS transistor 36a. As a result, the output source current Iok is reduced to the second and third
Are supplied to the capacitors 38 and 39. This value is controlled so as to be inversely proportional to the terminal voltage Sj of the first capacitor 34. Therefore, the second and third capacitors 3
8 and 39 are connected to the output source current I
A waveform Sk1 obtained by integrating ok is obtained.

When the charging of the second and third capacitors 38 and 39 progresses and the potential at the connection point k exceeds the threshold level V2 of the inverter circuit group 40, the outputs of the inverter circuits 41 and 42 are inverted. As a result, the potential of the input terminal h of the first inverter circuit 31 becomes S
As shown by h1, it is inverted to high potential V3. During this reversal,
The potential at the connection point k is the threshold voltage V2. Since the capacitances of the second and third capacitors 38 and 39 are made equal, the potential Sk at the connection point k after inversion is "threshold voltage V2" + "half of the high potential V3" due to the voltage division ratio. , That is, a potential equal to the high potential V3.

Since the potential of the input terminal h has become high,
In the first inverter circuit 31, the N-type MOS transistor 31b is turned on, and its output terminal is connected to the second constant current source 33. That is, the N-type MOS transistor 33b
, A constant sink current Isj flows from the capacitor 34. The terminal voltage at the j point of the capacitor 34 decreases linearly like Sj2.

At the same time as the potential of the input terminal h becomes high, the N-type MOS transistor 35b of the second inverter circuit 35 is turned on, and its output terminal is connected to the second current control circuit. That is, the sink current Isk flows from the second and third capacitors 38 and 39 via the N-type MOS transistor 37a. The value of the sink current Isk is controlled so as to be proportional to the terminal voltage Sj of the first capacitor 34. Therefore, the potential of the connection point k has a waveform like Sk2 obtained by integrating the output sink current Isk.

When the discharge of the second and third capacitors 38 and 39 progresses and the potential at the connection point k reaches the threshold level V2 of the inverter circuit group 40, the outputs of the inverters 41 and 42 are inverted, and the first inverter The potential of the input terminal h of the circuit 31 is inverted like Sh2, and becomes the low potential V1. At the time of this inversion, the potential at the connection point k is at the threshold voltage V2. Since the capacitances of the second and third capacitors 38 and 39 are made equal, the potential Sk at the connection point k after inversion is "threshold voltage V2"-"half of the high potential V3" due to the voltage division ratio. , That is, a voltage equal to the low potential V1. This returns to the initial state. The above is repeated, and the oscillation is continued.

Assuming that the capacitance values of the second and third capacitors 38 and 39 are larger than the set values due to manufacturing variations, the time constant is increased by the excessive capacitance of the capacitors 38 and 39. Then, the potential waveform at the connection point k becomes as shown by Sk3 and Sk4. As a result, the period of the potential of the input terminal h is extended as shown by the waveforms Sh3 and Sh4, and the frequency is reduced. However, here, since the first capacitor 34 and the second and third capacitors 38 and 39 are formed on the same substrate, the capacitance value of the first capacitor 34 is similarly increased. Therefore, the slope of the change in the terminal voltage due to the charging and discharging of the first capacitor 34 becomes gentler as Sj3 and Sj4 due to the excess capacity. Therefore, during the charging of the first capacitor 34, the current flowing through the P-type MOS transistor 36a is smaller than the current flowing through the transistor 36a when the second and third capacitors 38 and 39 have the set capacitances. As a result, the change in the time constant that determines the terminal voltage value of the second and third capacitors 38 and 39 at the connection point k is offset. The same applies during the discharge of the first capacitor 34.

For this reason, the second and third capacitors 3
Also, when the capacitance values of the capacitors 8 and 39 vary, the charge / discharge speed of the capacitor, that is, the charging or discharging is started, and the terminal voltage gradually rises or falls, exceeding the threshold voltage of the inverter circuits 41 and 42 and the output signal. The change in the time until the signal is inverted is suppressed, so that stable oscillation performance is maintained without fluctuation of the oscillation frequency.

The other ends of the capacitors 34 and 39 need only be connected to a predetermined constant voltage, and need not necessarily be connected to the power supply voltage Vss. Each inverter circuit 3
The output source currents and output sink currents of 1, 35 may not be equal. The same applies to the capacitors 34, 38 and 39. The number of stages of the inverter circuit group such as the inverter circuits 41 and 42 of the buffer functioning as a positive feedback circuit is arbitrary as long as it is an even number. An operational amplifier or the like may realize a function equivalent to these, that is, a function in which the input and the output are in phase and the output switches between logic levels 1 and 0 at a predetermined threshold level.

[0022]

As described above, according to the present invention, the first to third capacitors are formed on the same substrate, the output terminal of the first inverter circuit is connected to the first capacitor, and the second and third capacitors are connected. A capacitor is connected to the output terminal of the second inverter circuit, and the output current of the second inverter circuit is controlled by the terminal voltage of the first capacitor.
Even when the capacitance values of the capacitors vary, the fluctuation of the time constant due to the variation is canceled out, and the oscillation frequency is stably maintained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a circuit diagram showing an embodiment.

FIG. 3 is a diagram showing waveforms at various points in the embodiment.

FIG. 4 is a circuit diagram showing a conventional example.

FIG. 5 is a diagram showing waveforms of respective parts in a conventional example.

[Explanation of symbols]

 31 first inverter circuit 32 first constant current source 33 second constant current source 34 first capacitor 35 second inverter circuit 36 first current control means 37 second current control means 38 second capacitor 39 Third capacitor 40 Inverter circuit group Ioj, Iok Output source current Isj, Isk Output sink current Sh Potential at input terminal h Sk Potential at connection point k Sj Terminal voltage of first capacitor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 3/023

Claims (1)

(57) [Claims] 1. A first, a second, and a third capacitor formed on the same base, a first inverter circuit having an output terminal connected to the first capacitor, and a terminal of the first capacitor. First current control means for flowing a current of a predetermined value in accordance with a voltage; second current control means for flowing a current of a predetermined value in accordance with a terminal voltage of the first capacitor; A high potential voltage is supplied via the first current control means, a low potential voltage is supplied from the low potential voltage source via the second current control means, and the third capacitor is connected to the output terminal. And an input terminal connected to the output terminal of the second inverter circuit, an output terminal connected to the input terminals of the first and second inverter circuits, and an input terminal connected between the input terminal and the output terminal. The battery to which the second capacitor is connected Oscillation circuit; and a §.