JPH05233091A - Clock generating circuit - Google Patents

Abstract

PURPOSE:To oscillate a clock output just after impressing power supply by selectively switching either an oscillator using a control element with a high Q or an oscillator using a control element with a low Q at a frequency almost equal to each other in the case of activating power supply. CONSTITUTION:Oscillators 1 and 2 start oscillation when a power supply voltage is impressed. In this case, since the high Q frequency control element such as a crystal oscillator is used for the oscillator 1, stable oscillation time at the degree of several dozens of mS is required. Since the oscillator 2 is the CR oscillation circuit of the low Q frequency control element, however, the oscillator 2 is started just after the power supply voltage impression and starts stable oscillation. Therefore, control is executed in the beginning to a switching circuit 3 so as to select the oscillator 2 and when a microcomputer is operated by a clock CK and the stable oscillation time of the oscillator 1 is lapsed, control is executed to the switching circuit 3 so as to select the oscillator 1. At the same time, the oscillator 2 is stopped by an oscillation stop signal S. Therefore, the output of the oscillator 1 is supplied to a clock generating circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generating circuit, and more particularly to a clock generating circuit for a microcomputer using a crystal oscillator or the like.

[0002]

2. Description of the Related Art Generally, an oscillator using a high-Q frequency control element such as a crystal oscillator has a time required for the oscillation to be sufficiently stabilized after the power is applied to start oscillation, that is, an oscillation stabilization time ts. There are several tens of mS. Therefore, since the oscillation is unstable during the period of the oscillation stabilization time, the microcomputer or the like using the clock due to the oscillation is configured to stop the clock output during this period in order to avoid malfunction.

A conventional clock generating circuit of this type is shown in FIG.
3, an oscillator 1 using a crystal oscillator or a ceramic oscillator as a frequency control element, a counter 8 for counting the output frequency of the oscillator 1, and a flip-flop 9 set by an overflow signal of the counter 8
And an AND circuit 10 that takes the logical product of the output of the oscillator 1 and the output of the flip-flop 9, and a clock generation circuit 5 that generates the system clock CK from the output of the oscillator 1 via the AND circuit 10. Was there.

Next, the operation of the conventional clock generating circuit will be described.

FIG. 5 is an operation time chart of the conventional clock generation circuit.

First, the oscillator 1 starts to oscillate when the power supply voltage V is applied. At the same time, the counter 8 and the flip-flop 9 are reset by the reset signal R from the outside. At this time, the output Q of the flip-flop 9 which is one input of the AND circuit 10 is at "L" level, and the output F of the oscillator 1 which is the other input, that is, the input of the clock generation circuit 5 is blocked. Therefore, the clock generation circuit 5 stops its operation and the clock CK is not output. Next, the counter 8 starts counting the frequency of the output F of the oscillator 1, and outputs the overflow signal O when the preset count value corresponding to the oscillation stabilization time ts is reached. The flip-flop 9 is set by the overflow signal O and sets the output Q to "H" level. As a result, the AND circuit 1
0 is the output F of the oscillator 1, that is, the clock generation circuit 5
Pass the input of. Therefore, the clock generation circuit 5
Was to start the operation and output the clock CK.

As described above, the oscillation stabilization time t of the oscillator 1
s is about several tens of mS. During this time, a microcomputer using a clock of several MHz can execute instructions of tens to hundreds of steps. Therefore, in the application of the microcomputer in which it is necessary to urgently execute the processing after the reset, the stop of the clock supply during this period is an extremely serious drawback.

[0008]

Since the above-described conventional clock generation circuit stops the operation until the oscillation is sufficiently stabilized, it does not generate the clock. Therefore, the microcomputer equipped with it can execute the processing during that period. It had the drawback of being impossible. In particular, in the application of a microcomputer that needs to execute processing urgently after resetting, there is a problem that this waiting time is an extremely large problem.

[0009]

The clock generation circuit of the present invention comprises a first oscillator using a high Q frequency control element,
A second oscillator using a low Q frequency control element having a frequency substantially equal to that of the first oscillator, and oscillator switching means for selecting an output of either the first oscillator or the second oscillator. ..

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a clock generation circuit of the present invention.

As shown in FIG. 1, the clock generation circuit of this embodiment includes an oscillator 1 using a crystal oscillator or a ceramic oscillator, an oscillator 2 using a CR oscillation circuit composed of resistors and capacitors, and an oscillator. 1 and an oscillator 2, a switching circuit 3, a flag 4 for setting a switching instruction of the switching circuit 3 which is set by a command C from the CPU and reset by a reset signal R, and a clock generated by the output of the switching circuit 3. And a clock generation circuit 5 that operates.

Next, the operation of this embodiment will be described when it is installed in a microcomputer as in the conventional example.

FIG. 2 is a time chart of the clock generation circuit of this embodiment shown in FIG.

First, the oscillator 1 and the oscillator 2 start oscillating when the power supply voltage V is applied. At the same time, the flag 4 is reset by the reset signal R. Here, since the oscillator 1 uses the high-Q frequency control element such as the crystal oscillator as described above, the oscillation stabilization time ts of about several tens of mS is required. However, since the oscillator 2 is a CR oscillation circuit composed of a resistor and a capacitance which are low Q frequency control elements as described above, it immediately rises and starts stable oscillation immediately after the application of the power supply voltage V. The output P of the flag 4 in the reset state is, for example, "0", and controls the switching circuit 3 to select the oscillator 2. Therefore, the output of the oscillator 2 is supplied to the clock generation circuit 5, and the clock CK is generated in synchronization with this.

Next, the microcomputer is operated by the clock CK, and when the time corresponding to the oscillation stabilization time ts of the oscillator 1 is measured, the output P of the flag 4 is issued by the command C.
Is set to '1'. When the output P of the flag 4 is set to "1", the switching circuit 3 is controlled to select the oscillator 1. At the same time, the oscillation stop signal S is sent to the oscillator 2
To stop this. Therefore, the output of the oscillator 1 is supplied to the clock generation circuit 5, and the clock CK is generated in synchronization with this.

From the above, the oscillation stabilization time ts of the oscillator 1
The microcomputer can operate even during the period.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

The difference of this embodiment from the first embodiment is that, in addition to the oscillator 2, a frequency dividing circuit group 6 composed of a plurality of frequency dividing circuits 61 to 6n connected in cascade, the oscillator 2 and the frequency dividing circuit. That is, a switch circuit 7 for switching and outputting the outputs of the circuits 61 to 6n is added. The other components are common to the first embodiment and are not shown.

The switching of the switch circuit 7 is prepared, for example, at the stage of an optical mask for determining a circuit pattern at the time of manufacturing, and can be realized by a mask option for selecting a mask corresponding to each output.

Next, the operation of this embodiment will be described.

For example, when the user operates the microcomputer with a power source having a low power source voltage such as a battery,
Generally, it is necessary to reduce the clock frequency. In this embodiment, the clock frequency is reduced by the frequency dividing circuit group 6. This makes it possible to provide a microcomputer that can operate in a wider power supply voltage range.

[0024]

As described above, the clock generation circuit of the present invention comprises a first oscillator using a high Q frequency control element, a second oscillator using a low Q frequency control element, and
By providing the oscillator switching means for selecting the output of either the first oscillator or the second oscillator, it is possible to output the clock immediately after the power is applied. Therefore, there is an effect that a microcomputer or the like equipped with this clock generation circuit can operate directly without a waiting time after application of power.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a clock generation circuit of the present invention.

FIG. 2 is a time chart showing an example of the operation of the clock generation circuit of this embodiment.

FIG. 3 is a block diagram showing a second embodiment of the clock generation circuit of the present invention.

FIG. 4 is a block diagram showing an example of a conventional clock generation circuit.

FIG. 5 is a time chart showing an example of the operation of the conventional clock generation circuit.

[Explanation of symbols]

 1, 2 oscillator 3 switching circuit 4 flag 5 clock generation circuit 6 frequency dividing circuit group 7 switch circuit 8 counter 9 flip-flop 10 AND circuit 61 to 6n frequency dividing circuit

Claims (3)

[Claims] 1. A first oscillator using a high-Q frequency control element, a second oscillator using a low-Q frequency control element having a frequency substantially equal to that of the first oscillator, and the first and second oscillators. And an oscillator switching means for selecting any one of the outputs. 2. A frequency divider circuit for dividing the output of the second oscillator, and an output switching means for selecting one of the output of the second oscillator circuit and the output of the frequency divider circuit. The clock generating circuit according to claim 1, wherein 3. The first oscillator is a crystal oscillator,
2. The clock generation circuit according to claim 1, wherein the second oscillator is a CR oscillation circuit using a time constant circuit of resistance and capacitance.