JP3120352B2 - Clock supply system, real-time clock module, operation clock supply unit, and information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for supplying a clock signal used in an information processing apparatus such as a computer and other electronic equipment, and to a system for supplying a clock signal used for constructing this system. It is about a unit.

[0002]

2. Description of the Related Art FIG. 20 shows an example of a conventional system which includes a semiconductor integrated circuit, a piezoelectric vibrator and the like, and supplies an operation clock to a CPU unit and the like. In this system, a crystal oscillator 101 using an integrated circuit (IC) chip such as a CMOS type and a piezoelectric vibrator such as a crystal vibrator is provided.
It is provided for each processing unit. That is, the central control unit (CPU) 102 has an oscillator 101 of 80 MHz, and the floppy disk drive (FDD) / hard disk drive (HDD) unit 103 has an oscillator 101 of 24 MHz.
The bus control unit 104 has 16 MHz
And a 14.318 MHz oscillator, and a video graphic array (VGA) has 25 oscillators.
Two oscillators are provided, one at MHz and one at 32 MHz. In such a system, each processing unit is provided with an oscillator for a clock signal having a frequency required by each processing unit, and operates by receiving a clock signal from the oscillator. Therefore, a crystal oscillator equal to the number of clock signals of the frequency required by each processing unit is required. In such a supply system, the function of the electronic device is improved and the number of crystal oscillators is also increased, which causes an increase in cost and size of the electronic device.

Further, AT-cut quartz oscillators are used in crystal oscillators having stable temperature characteristics adopted for these electronic devices. These AT-cut quartz oscillators have an oscillation frequency of 40 MHz to 80 MHz or the like. The higher the frequency, the more expensive. Therefore, there is a problem that the cost of the electronic device is further increased when trying to obtain a clock signal with a high frequency in order to improve the processing speed.

In addition, these processing units, CPU 10
2. A reset signal generating circuit 110 for supplying a reset signal to each processing unit such as the FDD / HDD unit 103 and the bus control unit 104 is provided so that these processing units can be reset simultaneously. I have. However, the timing for generating the reset signal must be synchronized with the timing of the entire system including a plurality of processing units. Since each processing unit operates with an independent clock signal, the timing of the circuits of these units must be adjusted. If it is necessary to match, a complicated and expensive system is required.

In the conventional clock signal supply system shown in FIG. 21, a multi-output oscillator 105 using a phase locked loop (PLL) circuit is combined with a crystal oscillator 106 to prepare clock signals of a plurality of frequencies with the multi-output oscillator 105. And
In this system, these clock signals are supplied to respective processing units, for example, the CPU 102, the FDD / HDD unit 103, the bus control unit 104, and the like for each frequency. Such a scheme has recently become popular.

[0006] Such a supply method has an advantage that the number of crystal oscillators can be reduced even if the number of processing units increases. However, since a high-frequency clock signal, which is a high frequency, is supplied, there is a problem that radiation noise from the wiring increases. For example, when a multi-output oscillator is laid out near the CPU 102, FDD / H
A clock line such as a bus clock needs to be routed to the DD unit 103 and other processing units. Therefore, when a high-frequency clock signal required to increase the processing speed is supplied by such routing, EMI (Electro Magnetic) is provided.
Interference is a source of radiation noise. Also, since multiple frequencies are generated at the same time,
Due to mutual interference of a plurality of PLL circuits or a plurality of output buffers, the purity (C / N ratio) of a signal output from a voltage controlled oscillation circuit included in each PLL circuit is deteriorated, or a waveform called phase jitter. Causes fluctuation of the image. Also, this may cause a problem such as the lock of the PLL circuit being released. Further, since the frequency is also predetermined, the entire multi-output oscillator must be newly created in order to change only one frequency.

The clock signal supply system shown in FIG. 22 includes semiconductor integrated circuits 122 to 122 constituting each processing unit.
A circuit for supplying a clock signal necessary for the operation of each processing unit is formed at 125. The clock signal supply system is described in detail in Japanese Patent Application Laid-Open No. 4-140812.
It has a phase locked loop circuit (PLL circuit) 126 for generating a clock signal for each unit, and a clock signal as a reference is supplied from the clock generation circuit 121 to these PLL circuits 126.

In this clock signal supply system, the generation of EMI noise can be suppressed by keeping the frequency of the reference clock signal supplied to each processing unit low. However, since a PLL circuit that generates a clock signal suitable for each processing unit is incorporated in each semiconductor integrated circuit that is the same as the processing unit, the frequency of a clock for operating a CPU, a memory, an I / O controller, or the like is limited. If it is necessary to change the frequency, for example, to change the operation speed, each semiconductor integrated circuit must be newly created. Further, since the PLL circuit is integrated inside each semiconductor integrated circuit, the size of each processing unit becomes large, and in order to reduce the manufacturing cost and size, a flexible PLL circuit such as a common PLL circuit is used. Can't design. Furthermore, if the PLL circuit is CP
Since the semiconductor device is integrated with the U or the like, the semiconductor device including the processing unit requires a heat radiation measure including a PLL circuit that generates an increased amount of heat as the operating clock frequency increases.
Such heat dissipation measures also increase the manufacturing cost. Also,
Since PLL circuits handle high frequencies, this circuit is
When integrated on the same semiconductor substrate as digital circuits such as
Affects the performance of the digital circuit, such as causing a malfunction of the digital circuit. Therefore, there is a problem that it is difficult to design and develop a semiconductor integrated circuit on which a PLL circuit is mounted.

[0009]

Therefore, in the present invention, in view of the above problems, the manufacturing cost is low, the size can be reduced, the generation of noise is small, and furthermore,
It is an object of the present invention to provide a clock supply system that can flexibly cope with designing a device or a unit to which a clock supply system such as an information processing device and a CPU is applied. It adopts a unitized reference clock source and a unitized clock source that can be distributed and installed. The reference clock source has a power supply voltage monitoring function, a reset function, and a real-time clock function. Another object is to provide a system and a unit having various functions. Furthermore, as a clock source that can be installed in a distributed manner, it is an object to provide a unit that can appropriately supply a clock signal suitable for various processing units while being a unit that can be manufactured at a low cost with a unitized configuration. I have. By using these reference clock sources and unitized clock sources that can be installed in a distributed manner, the objective is to realize a compact, high-performance, and inexpensive clock supply system that can be used in various electronic devices. And

[0010]

According to the present invention, a reference clock supply unit for supplying a reference clock signal is provided.
A clock supply system is constructed by using an operation clock supply unit that can be installed separately for one or a plurality of processing units. The operation clock supply unit according to the present invention is a unit capable of receiving a reference clock signal from the reference clock supply unit, dividing or multiplying the reference clock signal to supply an operation clock signal suitable for each processing unit. The unit itself is independently configured as a single device. Such a unit can be provided, for example, as being configured on one semiconductor substrate. The operation clock supply unit, which is unitized independently, can be mounted near an integrated processing unit such as a CPU or an FDD / HDD unit, and an operation clock signal having a frequency suitable for each processing unit is used as a reference clock. It can be supplied based on a signal.

As described above, the clock supply system according to the present invention is a reference clock supply unit including the oscillating means for oscillating a reference signal having a constant frequency and the reference clock supply means for supplying a reference clock signal based on the reference signal. And at least one that performs processing based on a clock signal.
A function of supplying an operation clock signal of a predetermined frequency to one processing unit includes at least one operation clock supply unit that is unitized independently. And the operation clock supply unit,
Frequency synthesizer means for receiving a reference clock signal from the reference clock supply unit and multiplying or dividing the reference clock signal to generate an operation clock signal, and controlling the frequency of the operation clock signal generated by the frequency synthesizer means And control means.

In such a clock supply system, if the reference clock supply unit can supply a stable reference clock signal using a crystal oscillator or the like, a stable clock signal can be supplied as a whole system. Therefore, even if an expensive oscillation source having stable performance, such as a temperature-compensated crystal oscillator (TCXO), is employed to generate the reference clock signal, the influence on the cost is small, and the clock supply with low cost and high reliability is provided. The system can be realized.

Further, even when supplying an operation clock signal having a high frequency to operate the processing unit at a high speed, the operation clock supply unit is arranged near the processing unit and the distance between the operation clock supply unit and the processing unit is reduced. , Can be equal to or shorter than the distance between the operation clock supply unit and the reference clock supply unit. Therefore, even when a clock signal having a high frequency is supplied, generation of noise accompanying the clock signal can be suppressed.

Also, since the operation clock supply unit according to the present invention is configured as a single unit,
An operation clock suitable for a processing unit such as U can be easily supplied. Even if you want to design and manufacture an information processing device that changes the frequency of the clock signal that operates the processing unit, there is no need to redesign the semiconductor integrated circuit including the processing unit, and it operates to supply the clock signal at that frequency. What is necessary is just to change the setting of the clock supply unit.
Alternatively, an information processing device or the like may be designed and assembled using an operation clock supply unit manufactured to supply a clock signal having such a frequency. As described above, since the means for supplying the operation clock signal from the reference clock signal is independently unitized, the degree of freedom in designing and manufacturing an electronic device such as an information processing device can be ensured. A stable clock signal suitable for the purpose and function of the processing device or the processing unit can be supplied by an inexpensive system.

In such a clock supply system, the operation clock signal supplied to each processing unit can be managed collectively by the reference clock signal. Therefore, the operation of each processing unit can be managed by providing various functions in the reference clock supply unit. For example, when the reference clock supply unit is supplied with the main power supply and the battery power supply, means for comparing the voltage of the main power supply with the voltage of the battery power supply and the specified voltage, It is effective to provide a means for stopping the supply of the reference clock signal when the voltage is lower than any one of the predetermined voltage and the specified voltage. As a result, it is possible to prevent the processing units from operating in a state where the power supply voltage has not been established, and prevent these processing units from malfunctioning or becoming unstable. In addition, when the processing unit cannot operate stably, the supply of the clock signal to the processing unit can be stopped, so that the current consumption of the battery, which is an auxiliary power supply, can be reduced and the life of the battery can be extended. Become.

In the reference clock supply unit, a predetermined time has elapsed from the time when the voltage of the main power supply is higher than either the voltage of the battery power supply or the specified voltage, or becomes higher than one voltage and equal to the other voltage. It is also effective to provide a means for supplying a reset signal later. As described above, in the system of the present example, the reset signal can be supplied to each processing unit at the same timing. Therefore, by providing such a reset signal, the processing units can be operated at the same time after the power supply voltage is established and stabilized.

Further, the reference clock supply unit may be provided with a means for supplying a reference signal for measuring at least one of a time and a calendar. Further, the reference clock supply unit may be provided with means for measuring at least one of the time and the calendar by the reference signal, and may have a function as a real-time clock module.

It is of course possible to supply an operation clock signal from the operation clock supply unit to a plurality of processing units. By providing the frequency synthesizer means with at least one PLL circuit capable of generating at least one frequency, It is also possible to supply operation clock signals of different frequencies. 2 with different frequencies
Of course, the above operation clock signal can be supplied to one or a plurality of processing units.

If the frequency synthesizer means is capable of oscillating operation clock signals having different frequencies by changing the set value, the control means is provided with a set value for oscillating at a predetermined frequency from a plurality of set values. By providing setting means for setting the frequency synthesizer means, operation clock signals of various frequencies can be supplied from the unitized operation clock supply unit. Therefore,
When operation clock signals of various frequencies are required,
It is not necessary to design and manufacture the operation clock supply unit according to the frequency, and a common unit can cope with the operation clock supply unit. In addition, it becomes easy to change the frequency of the operation clock signal.

A frequency synthesizer compares a reference signal with an output signal oscillated by the voltage controlled oscillator by a phase comparator and supplies an output signal of a predetermined frequency.
When an L circuit is provided, an adjustment circuit may be provided which divides an output signal according to a set value and supplies the divided signal to a phase comparison circuit.

Further, the setting means is provided with a storage means for storing a plurality of set values, and further, a control input means for receiving a control input supplied from outside the operation clock supply unit;
Decoding means capable of selecting a set value to be set in the frequency synthesizer means from a plurality of set values based on the control input is provided, so that the frequency of the operation clock signal supplied from the operation clock supply unit can be changed by the operation clock supply unit. Can be set freely from outside. If the control input means is provided with a plurality of input terminals and means for pulling up or pulling down each of these input terminals, the frequency of the operation clock signal can be changed by arranging the bonding wiring connecting these input terminals to the substrate. Can be set. In addition, a storage unit that stores only the set value set in the frequency synthesizer unit of the unit among the plurality of set values may be provided. Storage means: fuse ROM, EEPROM
An OM or the like can be adopted, and an operation clock signal of a predetermined frequency can be easily oscillated simply by setting the storage contents of the storage means or installing a storage means in which predetermined information is recorded.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

[Schematic Configuration of Clock Supply System] FIG.
2 shows a part related to the clock supply system of the present example in the schematic configuration of the information processing apparatus employing the clock supply system according to the embodiment of the present invention. The information processing apparatus 1 according to the present embodiment includes a CPU 2 as a processing unit, an FDD / HDD
A unit 3, a bus control unit 4, a communication unit 5, a VGA unit 6, and a keyboard unit 7 are provided. These processing units 2 to 7
Is realized by arranging a single-chip semiconductor integrated circuit or a plurality of elements on a printed circuit board in a single area. A single-chip semiconductor circuit is provided near the substrate on which the processing units 2 to 7 are provided. An operation clock supply unit 20 implemented as an integrated circuit is mounted.

In the clock supply system of this embodiment, the operation clock supply unit 20 can supply an operation clock signal having a frequency required for the operation of each of the processing units 2 to 7. For this reason, the operation clock supply unit 20 of this example can generate and supply an operation clock signal of a predetermined frequency from a wide frequency range of 1.84 MHz to 80 MHz.

In the FDD / HDD unit 20,
The operation clock supply unit 20b is set to supply a 24 MHz operation clock signal, and the operation clock supply unit 20e is set to supply the communication unit 5 with a 1.84 MHz clock signal.
Is set. The operation clock supply unit 20f for the VGA unit 6 is set so as to be able to supply both a 40 MHz clock signal and a 24 MHz clock signal. Further, a reference clock signal described later is also supplied to the VGA unit 6 as it is. It is supplied as a clock signal.

The information processing apparatus 1 of this embodiment includes a real-time clock module 10 in addition to the operation clock supply unit 20. The real-time clock module 10 is connected to each operation clock supply unit 20 by a wiring 19 on a substrate, and can supply a reference clock signal from the real-time clock module 10 to each operation clock supply unit 20. That is, in the information processing apparatus of the present embodiment, one real-time clock module 10 and a plurality of operation clock supply units 20 dispersedly arranged in the vicinity of each processing unit are connected, and an operation clock signal of a predetermined frequency is transmitted. A clock supply system that can supply each processing unit is constructed. In addition, a clock signal having a low frequency of 32.768 kHz, which is a clock clock source generally used for measuring the time or calendar, is selected as a reference clock signal, and a considerable distance in the information processing apparatus is selected. High-frequency noise is not generated from the wiring 19 for supplying the running reference clock signal. On the other hand, since the distance between each processing unit and the operation clock supply unit 20 is short, the wiring 29 for supplying the operation clock signal can be short. Therefore, even when a high-frequency operation clock signal is supplied from the operation clock supply unit 20, generation of high-frequency noise can be suppressed.

The frequency of the reference clock signal is not limited to the frequency of the present embodiment, but is preferably several MHz or less, particularly preferably 100 KHz or less, in consideration of minimizing noise generation and power consumption. As described below, such a reference clock signal is obtained in the system of the present embodiment by using a quartz oscillator as the piezoelectric oscillator in the real-time clock module 10 and oscillating the quartz oscillator. By using a crystal oscillator, a reference clock signal that is stable with respect to temperature or the like can be obtained at low cost and easily. Further, in order to obtain a stable reference clock signal, it is desirable to use a piezoelectric element such as a crystal oscillator that oscillates stably.

Such a clock supply system can of course be applied to electronic equipment other than the information processing apparatus, and is particularly suitable for electronic equipment that requires a plurality of clocks. In addition, the range of the processing units that receive the operation clock signal from the operation clock supply unit can be freely set according to the arrangement on the substrate and the frequency of the operation clock signal, and the operation clock supply unit is installed for each processing unit. Alternatively, a common operation clock signal may be supplied from one operation clock supply unit 20c such as the CPU 2 and the bus control unit 4. When a plurality of processing units are adjacent to each other, by providing a common operation clock supply unit, the number of operation clock supply units installed in an information processing device or the like can be reduced, and the size and power consumption of the device can be reduced. Can be planned.

In a system such as the clock supply system of this embodiment, which receives a reference clock signal from a single real-time clock module 10 and an operation clock signal from an operation clock supply unit, Since only one inexpensive low-frequency vibrator needs to be used, the cost of the device can be reduced, and the mounting density of the substrate and the like can be reduced. Response is possible.

[Real-Time Clock Module] Configuration of Real-Time Clock Module The real-time clock module of this embodiment will be described in more detail below. The real-time clock module 10 of the present embodiment has a function of clocking a time and a calendar required for a computer or the like, and further includes a clock signal required for clocking the clock and a reference clock signal based on the above-described operation clock signal. Is a clock module also provided with a circuit for oscillating.

FIG. 1 shows a schematic configuration of a real-time clock module 10 of the present embodiment. The real-time clock module 10 of the present embodiment is configured to receive power supply from outside as a main power supply 30 and to receive power supply from a battery built in the information processing apparatus 1 as a backup auxiliary power supply 31. The voltages of these power supplies are monitored by the voltage detection circuit 11, and the reference clock signal is supplied to each operation clock supply unit after the power supply voltage reaches a predetermined value and it is confirmed that the power supply has been established. Thereafter, after a predetermined elapsed time has elapsed in the delay circuit 12, a reset signal is output to each processing unit, and when the operation clock signal is stabilized, the operation of each processing unit is started, and the function of the information processing apparatus 1 is started. Is to be exerted normally.

The real-time clock module 1 of the present embodiment
Numeral 0 is provided with an oscillation circuit 14 using a crystal oscillator 13, and a reference signal of a constant frequency can be obtained by the oscillation circuit 14. This reference signal is supplied to an RTC circuit 15 that measures the time and calendar, and is used to measure them. Further, the reference signal is
The signal is supplied to an oscillation frequency processing circuit 17 which adjusts to a frequency as a reference clock signal via a switching circuit 16 which is turned on / off based on the determination result of the voltage detection circuit 11. The oscillation frequency processing circuit 17 divides or multiplies the reference signal by a predetermined frequency, in this example, 32.768 KH.
Adjust to the z reference clock signal and output from the output terminal. Note that the crystal unit 13 may be built in the real-time clock module 10 as in this example, and a system in which the crystal unit 13 is arranged outside the real-time clock module 10 and connected to the module 10 is adopted. You may.

The real-time clock module 10
In order to maintain the normal time and calendar function in the RTC circuit 15, it is necessary to receive a reference signal of an accurate frequency from the oscillation circuit 14 and keep the time counting. For this reason, the real-time clock module 10 is backed up by the battery power supply 31 and does not output the reference clock signal while being backed up by the battery power supply 31 so as to prevent the battery power supply 31 from being wasted. At this time, the current consumption of the real-time clock module 2 is a low power of only 0.3 to 0.4 μA.

The RTC circuit may have a function of measuring only one of the time and the calendar.

Various functions of the real-time clock module FIG. 2 shows the voltage detection circuit 11 and the switching circuit 1 used in the real-time clock module 10 of this embodiment.
6 and the configuration of the oscillation frequency processing circuit 17 are shown. The voltage detection circuit 11 according to the present embodiment is configured such that the voltage VDD of the main power supply 30 is
A first comparator 41 for comparing the battery voltage VBAT of the backup power supply 31 with a second comparator 42 for comparing the voltage VDD with the reference voltage Vref. An AND gate 43 for outputting a signal indicating the establishment is provided. The reference voltage Vref is obtained by applying the battery voltage VBAT to the Zener diode 44.
The comparator 42 can compare 1 with a value obtained by internally dividing the voltage VDD of the main power supply by the resistors R1 and R2. That is, the reference voltage Vref to be compared with the power supply voltage VDD
Is (R1 + R2) × V1 / R2.

The operation of the voltage detection circuit 11 of this embodiment will be described with reference to the timing charts shown in FIGS. FIG. 3 shows a case where the battery voltage VBAT is higher than the reference voltage Vref. When the power supply voltage VDD starts to increase at time t1 when supplied from the external power supply, the voltage VDD at time t2.
Reaches the reference voltage Vref, and the output of the comparator 42 is inverted to a high level. At time t3, the voltage VDD reaches the battery voltage VBAT, and the output of the comparator 41 is inverted to a high level. As a result, the output of the AND gate 43 is also inverted to a high level. Further, at time t4, the voltage VDD of the external power supply is applied.
At the time t5, the voltage VDD becomes lower than the battery voltage VBAT, the output of the comparator 41 is inverted to a low level, and at the same time, the output of the AND gate 43 is also inverted to a low level.

On the other hand, as shown in FIG.
Is lower than the reference voltage Vref, the comparator 4
1 is inverted to a high level at time t6, and when the output of the comparator 42 is inverted at time t7, AND
The output of gate 43 is also inverted to a high level. Then, at time t8 when the power supply voltage VDD becomes lower than the reference voltage Vref, the output of the comparator 42 is first inverted to a low level, and accordingly, the output of the AND gate 43 is also inverted to a low level. As described above, the power supply voltage VDD is applied by using the voltage detection circuit 11 of the present embodiment.
When the power supply voltage VDD is higher than or equal to the battery voltage VBAT, a signal is established from the AND gate 43 only when the power supply voltage VDD is higher than or equal to the reference voltage Vref.

As shown in FIG. 2, the switching circuit 16 of the present embodiment includes a NAN to which a signal indicating voltage establishment from the voltage detection circuit 11 and a reference signal from the oscillation circuit 14 are input.
A D gate 45 is provided. Therefore, when the voltage is established and A
Only when the signal from the ND gate 43 becomes high level,
NAN in response to the reference signal supplied from the oscillation circuit 14
The output of the D gate 45 is inverted to a low level, and the reference signal is supplied to the oscillation frequency processing circuit 17. As described above, in the real-time clock module 10 of the present embodiment, the power supply voltage VDD is equal to or higher than the battery voltage VBAT, and the reference voltage V
Only at the time of ref or more, the reference clock signal is supplied to the operation clock supply unit 20, and the operation clock signal is supplied to each processing unit via the supply unit 20. Therefore, when the power supply voltage is the battery voltage VBAT
The processing unit does not operate in a state where a voltage lower than any one of the reference voltage Vref and the reference voltage Vref is not established.
Has increased its reliability. In addition, since the reference clock signal is not output under the condition that the processing unit does not operate, the power consumption of the real-time clock module can be significantly reduced. Under the condition in which the processing unit does not operate, the real-time clock module operates by consuming the backup battery power supply 31 as described above. Therefore, by providing the above functions, the life of the backup battery can be greatly extended. .

Further, in this embodiment, the power supply voltage VDD is added to the backup voltage VBAT and compared with the reference voltage Vref.
Only when is sufficient voltage for the processing unit
The processing unit operates. For this reason, even if the battery voltage is reduced, the operation is performed only under the condition that each processing unit can perform the predetermined function, and the predetermined performance can be ensured.

The switching circuit 16 can of course be configured by using an AND gate or an OR gate instead of the NAND gate as in this embodiment. Although the output of the switching circuit 16 is set to a high level when the switch is off, the output may be set to a low level when the switch is off.

When the power supply is established, the reference signal generated by the oscillation circuit 14 is supplied to the oscillation frequency processing circuit 17, which generates a reference clock signal having a predetermined frequency. In the oscillation frequency processing circuit 17 of this example,
The n dividers 46 are connected in series, and the output of each divider 46 can be selected by the multiplexer 47 and output from the frequency processing circuit 17. That is, the oscillation frequency processing circuit 17 of this example
Is a circuit for dividing the frequency of the reference signal (frequency f0), and can output a reference clock signal of frequency f0 / 2n from the reference clock signal of frequency f0 to the multiplexer 47 by control. Oscillation frequency processing circuit 17
May be a type that divides the reference signal as in this example,
Of course, a type that multiplies the reference signal using a phase locked loop (PLL) may be used. In the case where the reference signal is oscillated using an oscillator developed for a timepiece, the oscillation circuit 14 does not pass through the oscillation frequency
Can be output from the real-time clock module as a reference clock signal as it is.

FIG. 5 shows the configuration of the delay circuit 12 of this embodiment. When a signal whose voltage is established is output from the voltage detection circuit 11, the signal is supplied to the delay circuit 12. After a lapse of a predetermined time, a reset (bar) signal is output from the delay circuit 12 to each processing unit,
Each processing unit starts operation. Delay circuit 12 of this example
Has 14 dividers 48 connected in series,
The reference clock signal (3 in this example) generated by the oscillation frequency processing circuit 17 is applied to the first clock input of the divider 48.
2.768 kHz). The output of the previous divider 48 is input to the clock input (C) of each divider 48, and the output Q14 of the final divider 48, which is the fourteenth divider, is connected to the clock input of the D-type flip-flop 49. Have been.
The data input (D) of the flip-flop 49 is connected to the high potential VDD, and the respective dividers 4
8 and the flip-flop 49 are reset by a signal (the output of the AND gate 43) in which the voltage from the voltage detection circuit 11 is established. Therefore, in this example, about 250 ms after 2 14 cycles after the voltage is established.
After ec, the flip-flop 49 outputs a reset signal. The flip-flop 49
Is connected to a buffer 50, and a reset (bar) signal is supplied to each processing unit.

This will be described in more detail with reference to the timing chart of FIG. The power supply voltage starts to rise at time t11, and when the voltage is established at time t12, the output of the voltage detection circuit 11 goes high, and at the same time, the reference clock signal is output from the oscillation frequency processing circuit 17. The divider 48 and the flip-flop 49 of the delay circuit 12 operate at time t1.
2 is reset and about 250 msec from time t12
The output Q15 of the flip-flop 49 at time t13 after c.
Becomes high level and a reset signal is output. As a result, each processing unit is reset about 250 msec after the reference clock signal is supplied to the operation clock supply unit 20, and starts operating. By starting the operation of the processing unit after a predetermined time has elapsed from the start of the supply of the reference clock signal, each processing unit can be operated in a state where the operation clock signal supplied to each processing unit is stable, Malfunctions and the like can be prevented beforehand.

FIG. 7 shows another example of the delay circuit 12.
FIG. 9 shows a timing chart of this circuit of FIG. In the delay circuit 12 of this example, instead of determining the delay time based on the reference clock signal supplied from the oscillation frequency processing circuit 17, a CR oscillation circuit 51 is provided in the delay circuit 12. That is, when the power supply voltage is established at time t12, C
The R oscillation circuit 51 generates a signal fC of a fixed cycle by CR oscillation.
LK is output. The ripple counter 52 outputs the signal fC
LK is divided to obtain a predetermined delay time, and at time t14,
The Qn output of the ripple counter 52 is the flip-flop 4
9 is supplied to a clock input 9 and outputs a reset signal.
Note that the output of the flip-flop 49 is output via the buffer 50 and a reset (bar) signal is supplied in the same manner as the delay circuit 12 shown in FIG. If an oscillation circuit is provided in the delay circuit 12 as in this example, the delay circuit 12 can be operated independently of the oscillation circuit for the RTC circuit 15.
Therefore, even if the establishment of the reference clock signal is delayed, the delay time can be independently measured and a reset signal can be output. Further, since the oscillation is performed by the CR circuit, there is an advantage that the user can freely set the delay time by exchanging these elements if a capacitor or a resistor is externally provided.

FIG. 9 summarizes the operation of the real-time clock module 10 of this embodiment. When the battery voltage VBAT is established at time t21, the oscillation circuit 14 starts operating and outputs a reference signal. This reference signal allows the RTC
The circuit continues to count time and calendar time. Further, when the external power supply voltage VDD is established at time t22, the output of the voltage detection circuit 11 becomes high level, and the oscillation frequency processing circuit 17 outputs the reference clock signal.
The reference clock signal is supplied to each operation clock supply unit 20 via a wiring, and an operation clock signal having a frequency suitable for a corresponding processing unit is supplied from the operation clock supply unit 20. At the same time as the output of the voltage detection circuit 11 goes high, the delay circuit 12 starts counting the delay time, and after a predetermined delay time from time t22, outputs a reset signal to each processing unit at time t23. Starts operation. In this example, since the delay signal from power-on is accurately controlled when the entire system is started up, the system can be started up accurately and reliably corresponding to high speed. Further, since the supply clock to the entire system can be performed at a low frequency and only when the information processing apparatus is operating, power consumption can be reduced.

FIG. 10 shows a configuration of a clock oscillator 18 that can supply a reference clock signal instead of the above-described real-time clock module. The clock oscillator 18 shown in FIG. 10A does not include an RTC circuit for measuring time and calendar, and the reference signal generated by the oscillation circuit 14 is used to generate a reference clock signal to be sent to the operation clock supply unit 20. Used only for Further, no delay circuit is provided, and the reset signal is supplied from a circuit different from the clock oscillator 18. FIG. 10 (b)
Is a clock oscillator 18 provided with a delay circuit 12 for supplying a reset signal. These clock oscillators 1
8 has the same configuration as that of the above-described real-time clock module except for the RTC circuit. Therefore, common portions are denoted by the same reference numerals and description thereof is omitted. Note that the oscillation frequency processing circuit 17 does not need to be installed depending on the frequency of the reference signal generated by the oscillation circuit 14, and is shown by a broken line in the drawing.

[Operation Clock Supply Unit] Configuration of Operation Clock Supply Unit FIG. 11 shows a schematic configuration of the operation clock supply unit of this embodiment. Operation clock supply unit 20 of this example
Is a clock input unit 21 for receiving a reference clock signal.
A synthesizer unit 22 that generates and outputs an operation clock signal of a predetermined frequency based on the reference clock signal,
And a control unit 23 for controlling the frequency of the operation clock signal generated by the synthesizer unit 22. The clock input unit 21, the synthesizer unit 22, and the control unit 23 are formed on a single semiconductor substrate, and are integrated into one chip so that the operation clock supply unit 20 can be mounted independently.

The synthesizer section 22 has a programmable divider (PD) 24 for dividing the reference clock signal supplied from the clock input section 21 and a phase for generating a high frequency signal by multiplying the divided reference clock signal. A synchronization (PLL) circuit 25, a PD 26 for dividing a signal generated by the PLL circuit 25, and an output unit 27 for outputting an operation clock signal whose frequency is determined by the PD 26 are provided. The PLL circuit 25 includes a signal supplied from the PD 24 and a voltage controlled oscillator (VCO) 63.
A phase comparator 61 for comparing the phase of the signal fed back from the controller, a low-pass filter 62 for cutting the high-frequency component of the output of the phase comparator 61 and supplying the cutoff to the VCO 63;
A VCO 63 that oscillates so that the phases of the two signals input to the phase comparator 61 match. The phase comparator 61 has a function of outputting a signal voltage according to the input phase difference, the low-pass filter 62 has a function of removing high-frequency components of the output, and the VCO 63 changes the frequency according to the input voltage. It has a function to make it work. VCO6
The output of No. 3 is fed back to the phase comparator 61 via the PD 65. The output of VCO 63 is N by PD 65
Since the frequency is divided, the signal input to the phase comparator 61 is divided by N
A signal of the multiplied cycle is output from the VCO 63. That is, the operation clock signal obtained by multiplying the reference clock signal is output from the PLL circuit 25 of this example.

As described above, a total of three PDs 24, 26, and 65 are used in the operation clock supply unit 20 of the present embodiment, and by appropriately setting the frequency dividing ratio of these PDs, a desired frequency can be obtained. Operation clock signal can be obtained. Figure 1 shows the values of these PDs.
It is shown in FIG. The PD 65 is an element for determining the frequency oscillated in the PLL circuit 25 as described above. On the other hand, the PD 24 on the input side is effective when the reference clock signal is too high or when the frequency adjustment pitch of the frequency of the operation clock signal supplied from the operation clock supply unit 20 is reduced. In this example, since the reference clock signal is 32.768 KHz, the set value of the PD 24 is 1. The output side PD 26 does not output the output from the VCO 63 as the operation clock signal as it is, but divides the output from the VCO 63 to improve the duty of the output waveform, and then outputs the output clock as the operation clock signal. Things. Therefore, the normal setting value is 2
It is. However, when an operation clock signal having a lower frequency than the output range of the VCO 63 is output, the frequency division ratio can be increased, and a function of improving the flexibility of the operation clock supply unit is provided.

In the operation clock supply unit 20 of this embodiment, fref is the frequency of the reference clock signal, N is the frequency division number of the PD 65 of the PLL circuit, M is the frequency division number of the input PD 24, and X is the frequency of the output PD 26. Assuming that the frequency is a frequency division number, an operation clock signal having a frequency f0 represented by the following equation can be output.

F0 = fref × N / M / X (1) As described above, in the synthesizer unit 22 of this embodiment,
By providing appropriate setting values to the three PDs, it is possible to generate an operation clock signal of an appropriate frequency from the reference clock signal and supply the generated operation clock signal to the processing unit. The control unit 23 of the present example includes a decoder 66 that decodes an external control signal, and three PDs 24 that set values based on a command from the decoder 66 from among the set values stored in advance.
PROM as a storage unit to be set to 65 and 26 respectively
67 is provided, and the synthesizer section can be controlled with an appropriate set value by the above method.

FIG. 13 is an enlarged view of the control section 23 of the present embodiment, and shows a part of the configuration of the PROM 67. Based on the setting values shown in FIG. 12, assuming that the setting value N can take a value of 1 to 8191, the setting value M can take a value of 1 to 3, and the setting value X can take a value of 1 to 31, the PROM 67 It is sufficient to prepare 19 bits, 2 bits for the set value M, and 5 bits for the set value X. In this example, 8
Since an operation clock signal of a predetermined frequency can be selected from operation clock signals of various types, the decoder 66 has 3-bit control input terminals S0 to S2.
Is prepared. For example, to oscillate an operation clock signal of 1.8432 MHz, a control signal of “000” is input to the control input terminal of the
The address line corresponding to “000” among the 67 address lines is activated. As a result, the "00"
In the address corresponding to “0”, binary data “0001110000100” (90 in decimal) is used for the set value N.
0), binary data "01" (1 in decimal) for set value M, binary data "10000" for set value X
Since (16 in decimal) is stored, these set values are set in each PD.

As shown in FIG. 13, when a mask ROM is used as the PROM, the set value can be stored by connecting the switch SW with an aluminum pattern.
Therefore, if the aluminum pattern is changed, the frequency of a group of operation clock signals that can be selected by the operation clock supply unit of the present example can be easily changed. Such a change of the frequency table is not limited to the change of the aluminum pattern, and can be performed by a method used in a normal IC manufacturing process such as a program method using contact holes or a program method using ion implantation.

As described above, the operation clock supply unit of the present embodiment is formed on a single chip, and can generate and supply an operation clock signal of a required frequency to the processing unit by setting the control input terminal. I have. Therefore, the user does not need to design or manufacture an operation clock supply unit for each processing unit. Further, an operation clock supply unit can be provided as a general-purpose product using a common IC chip, and these units need only be installed near a predetermined processing unit. In order to supply a clock signal of a necessary frequency to the processing unit, it is possible to install a unit set to the frequency in advance, or to adjust the setting of the control terminal of the installed operation clock supply unit. Is also good. Also, when changing the frequency of the operation clock signal, it is only necessary to change the setting of the control terminal, and there is no need to redesign from a processing unit such as a CPU or change wiring for supplying a clock signal. It is.

Further, the function of supplying the clock signal is 1
Since it is formed into a chip and is independent, it is easy to design in consideration of heat radiation from the PLL circuit and other conditions. Therefore, the operation clock supply unit of this example can be realized using a small and inexpensive IC chip.

The real-time clock module 1
Operating clock supply unit 20 regardless of the operating voltage of
Is designed in the range of 3 V to 5 V, a unit using the same components can correspond to the drive voltage of each processing unit. That is, the operation clock supply unit 20 can be used as a device driven by 3 V or a device driven by 5 V.
Compared with the conventional piezoelectric oscillator, in which a chip is newly created, the delivery time and development cost are very small. Further, it is possible to construct a clock supply system that can easily cope with a system in which a device driven by 3 V and a device driven by 5 V are mixed.

Control Method of Operation Clock Supply Unit The control method of the operation clock supply unit 20 used in the information processing apparatus 1 of this embodiment shown in FIG. 1 will be described in more detail. For example, the operation clock supply unit 20a corresponding to the CPU 2 includes 50, 66.6 and 80
Operating clock signal having any frequency of MHz
This is supplied to PU2.

FIG. 14 shows an operation clock supply unit 20f for supplying an operation clock signal to the VGA 6. The operation clock supply unit 20f includes two synthesizers 22a and 22b, and can simultaneously supply two operation clock signals having different frequencies. Therefore, the control unit 23 stores the set values for the two synthesizer units 22a and 22b,
The decoders 66a and 66b also have control terminals S0 respectively.
To S2 and S3 to S5 are prepared. Each of the control terminals S0 to S2 is pulled up to a high potential via a pull-up resistor 55 by wiring on the printed circuit board, and only a predetermined control terminal is set low by a dip switch 56 also arranged on the printed circuit board. The frequency of the clock signal can be set as the potential. In this example, the dip switch 56 is turned on / off / off sequentially from the terminal S0, a signal of “011” is applied to the control terminal, and a 24 MHz operation clock signal is output from the synthesizer unit 22a.

The control terminals S3 to S5 are connected to a three-pole type dip switch 57 disposed on a printed circuit board, and apply high-level, low-level, and low-level potentials sequentially from the terminal S3. is there. Therefore, the signal of “100” is applied to the control terminals S3 to S5, and the 40 MHz operation clock signal is output from the synthesizer 22b.

FIG. 15 shows a state in which an IC chip 71 having an operation clock supply unit is molded with a resin 70. An IC chip 71 including a PLL circuit and the like is mounted on the island section 72, and each pad of the IC chip 71 and a plurality of lead terminals surrounding four directions around the island section 72 are wired by Au wire lines 73. . An input / output terminal composed of a plurality of leads includes a gate terminal 74 to which a 32.768 KHz reference clock source is input, and respective S0 terminal 75, S1 terminal 76, and S2 terminal 77 to which an external frequency setting signal is input.
And a power down or output enable control terminal 78, and an OUT terminal 79, a VDD terminal 80, and a VSS terminal 81 for outputting a set frequency.

The control signals can be set at the terminals 75 to 77 for inputting the control signals by a dip switch as described above, or by short-circuiting the wiring on the printed circuit board with a jumper wire or the like. Further, for example, a control signal can be set by a method of controlling from the VGA 6 in order to change the display resolution of the display. Further, the pattern of the printed circuit board may be designed in advance so that a predetermined signal is applied to the control terminals 75 to 77.

By controlling the power down or output enable control terminal 78, the operation of the IC chip 71 is stopped, the power consumed by the operation clock supply unit and the processing unit is eliminated, and the current consumption of the entire information processing apparatus is reduced. Can be done. That is, when the power down control terminal 48 is at a high level,
The C chip 71 is operating, and when the state becomes a low level, the operation of the IC chip 71 stops, and the output of the operation clock signal stops. In FIG. 1, the operation clock supply unit 20f for the VGA unit 6 is controlled using the control terminal 78. When powering down the VGA unit 6, the power down control terminal 48 of the operation clock control unit 20f is connected to the VGA unit. By operating from step 6 and setting the level low, the output of the operation clock signal can be stopped.

The same control terminal 78 also has an output enable function. This function is a function for selecting whether the state of the output terminal 79 of the IC chip 71 is an output state or a high impedance state. For example, when the control terminal 78 is set to a high level, the output terminal 79 outputs a clock signal. When the control terminal 78 is at a low level, the output terminal 79 is in a high impedance state. The output enable or power down function can be controlled by a control signal from each processing unit.

In this example, the power down and output enable of the IC chip 71 are wired to the same terminal 78. In this case, the power down and output enable functions are controlled simultaneously. Of course, it is also possible to wire power down and output enable independently and control them independently. Using these functions, various controls are possible, such as shifting to a power saving mode for each processing unit receiving an operation clock signal from each operation clock supply unit.

FIG. 16 shows the configuration of an operation clock supply unit incorporating a resistor for pulling up the control terminals S0 to S2. This operation clock supply unit 20
A pull-up resistor group 69 is provided so that the control terminals S0 to S2 can be pulled up to a high potential inside the unit 20. When the operation clock supply unit as shown in FIG. 17 has a built-in pull-up resistor, the oscillation frequency of the operation clock supply unit can be determined by connecting the pad and the lead by the Au wiring 73 during molding. . For example, terminals S1 and S2
Is connected to the lead of VSS and the terminal S0 is left open, the control signal "100" is supplied to the decoder 66.
A unit that supplies an operation clock signal of MHz.
In such a unit 20, since the frequency of the output operation clock signal is fixed in advance, there is no need to change the board wiring when mounting each unit.
Since the design and assembly common to all units can be completed, the number of design steps can be significantly reduced. Since no DIP switch is required, the entire device including the operation clock supply unit and the arrangement of the board can be made compact.
The size of the device can be reduced.

FIG. 18 shows that the fuse RO
An operation clock supply unit 20 employing M68 is shown. The fuse ROM is a type of ROM in which the switch SW portion of the PROM is formed in advance of polysilicon, and a fuse made of polysilicon is cut in accordance with data to be stored to store data. To cut the fuse, irradiate the laser to the fuse part,
For example, a method such as flowing a current through the fuse portion is adopted. If a set value for generating the frequency of the operation clock signal supplied from the operation clock supply unit 20 is stored in such a ROM, the operation clock signal of that frequency is always supplied from the synthesizer unit 22.

Also in the operation clock supply unit 20 using the fuse ROM, the output frequency is selected and fixed, and a clock signal having a stable frequency can be obtained. The number of clock signals whose frequency can be set by the fuse ROM is not limited to one, and the present invention is of course applicable to the unit 20 that supplies clock signals of a plurality of frequencies as described above. In such a unit, since the frequency of the operation clock signal is fixed in advance, the substrate wiring of each unit is also common, and the design man-hour and the like can be significantly reduced. Further, the frequency of the clock signal can be determined by a simple method, and an inexpensive operation clock supply unit can be provided.

FIG. 19 shows an outline of an information processing apparatus employing a clock supply system arranged differently from the above-described clock supply system. The information processing apparatus 1 of the present example also includes one real-time clock module 10, and the distributed operation clock supply unit 20 uses the reference clock signal supplied from the real-time clock module 10 to transmit the operation clock to each processing unit. We use a supply system. Therefore, the same parts as those in the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted. Real-time clock module 1 of this example
In the case of No. 0, since a reference clock signal of 32.768 KHz can be directly obtained from the oscillation circuit 14, no oscillation frequency processing circuit is provided. Further, a delay circuit for the reset signal is not provided, and the reset signal is supplied from a unit different from the real-time clock module.

The operation clock supply unit 20a for supplying an operation clock signal to the CPU 2 supplies 50, 66.6 or 80 MHz. The 16 MHz operation clock signal is also supplied to the operation clock supply unit 2 for the CPU 2.
0h is provided so that it is supplied independently. VG
The A unit 6 is provided with two operation clock supply units 20f and 20i, and each unit supplies an operation clock signal of one frequency. As described above, in the clock supply system according to the present embodiment, one operation clock supply unit 20 is assigned to each processing unit and each frequency, and an inexpensive unit having a single structure is adopted as the operation clock supply unit 20. be able to.

The frequency that can be supplied from the operation clock supply unit is not limited to the above. Of course, it is possible to set a setting value other than the above frequency table, and further, by increasing the number of terminals for inputting the frequency setting signal to four terminals, it is possible to select 16 types of frequencies. As the 16 types of frequencies, for example, 1.843, 14.318, 16, 20, 22.1
1, 24, 25, 32, 33.3, 40, 48, 50,
There are 66.6, 75, 80, and 100 MHz combinations. These frequencies are frequencies generally used for clocks of computers and the like. In order to cover these frequencies with three terminals, the output frequency table may be changed. For this purpose, a plurality of masks for A1 wiring corresponding to a plurality of output frequency tables are prepared in advance. It is enough.

[0071]

As described above, the clock supply system according to the present invention comprises a reference clock supply unit such as a real-time clock module, a CPU and an FD.
An operation clock supply unit distributed and installed near a processing unit such as a D / HDD unit. The operation clock supply unit receives a low-frequency reference clock signal from the reference clock supply unit and performs processing. A high-frequency operation clock signal suitable for the unit can be supplied.

Further, since the reference clock signal supplied from the reference clock supply unit to each operation clock supply unit may have a low frequency (for example, 32.768 KHz), the reference clock signal is radiated to the outside even if the wiring on the substrate becomes long. EM
I radiation noise is very small. On the other hand, since a high-frequency operation clock can be stably supplied to each processing unit from the operation clock supply unit, the clock supply system is suitable for a recent information processing device or the like that has been operating at a higher speed.
In addition, since there is very little electromagnetic radiation to the outside, measures to block noise and the like are simple, and the clock supply system is suitable for information processing devices that are becoming lighter and smaller, and these devices can be configured at low cost. There is also a merit.

Further, when oscillating using a piezoelectric vibrator or the like, in the clock supply system according to the present invention, it is only necessary to prepare the piezoelectric vibrator in the reference clock supply unit. Further, the oscillation frequency of the piezoelectric vibrator may be low.
Accordingly, inexpensive low-frequency vibrators (for example, 32.768 KH) are used as piezoelectric vibrators required for the clock supply system.
Normally, only one z) needs to be installed, so that the cost of the entire apparatus can be reduced and the mounting density of the substrate and the like can be reduced. Therefore, the degree of freedom in mounting layout is increased.

The operation clock supply unit used in the present invention can be realized by using a common IC chip regardless of the frequency of the operation clock. Therefore, the operation clock supply unit can be provided as an independent and versatile semiconductor unit, and the unit itself can be provided in a small size and at low cost. In particular, the operation clock supply unit according to the present invention does not require a piezoelectric element such as a quartz oscillator or another type of oscillation circuit to be installed therein, so that it can be extremely miniaturized. Since the operation clock supply unit according to the present invention can be arranged on a printed circuit board or the like without being affected by the type of the processing unit, the design and assembly of the apparatus can be easily performed, and the change is easy. Also, from the processing unit side such as a CPU, these processing units can be designed, assembled, and mounted apart from the processing of the clock signal,
A method suitable for the processing unit can be adopted for measures against heat generation. In this way, by providing the operation clock supply unit as a single unit, it becomes possible to design, assemble, and manufacture the clock supply unit and the processing unit in a manner suitable for each unit. It can be manufactured and supplied at low cost.
By using these units, a small, high-performance, and inexpensive device can be realized.

Further, the operation clock supply unit can use the same input / output terminals regardless of the oscillation frequency, and the substrate wiring of each unit is common, so that the number of design steps can be reduced. And such an operation clock supply unit includes:
It can be manufactured as a standard part, and the manufacturing lead time can be greatly reduced as compared with the case of manufacturing after the output frequency is determined as in the conventional piezoelectric oscillator and multi-output oscillator. In the conventional multi-output oscillator, if even one frequency of the system is different, the IC chip of the multi-output oscillator must be changed. However, in the clock supply system according to the present invention, the operation clock supply unit side Since the frequency of the operation clock signal can be freely set and the versatility is high, the compatibility with various systems is very high. By changing the mask or the like for the A1 wiring of the IC chip, it is possible to easily cope with an operation clock having a wider frequency.

Further, since the reference clock signal may have a low frequency, power for supplying the clock signal can be suppressed, and heat generation from the unit can be suppressed. Further, the reference clock supply unit according to the present invention can stop supply of the reference clock signal until the power supply voltage is established, or reset and operate the processing units all at once after a predetermined time from the establishment of the voltage. This is a clock supply system that has functions and can achieve both power saving and stable high functionality.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an information processing apparatus using a clock supply system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a part of a circuit of a real-time clock module of the clock supply system illustrated in FIG. 1;

FIG. 3 is a timing chart illustrating an operation of the voltage detection circuit illustrated in FIG. 2;

FIG. 4 is a timing chart illustrating an operation of the voltage detection circuit illustrated in FIG. 2;

FIG. 5 is a block diagram illustrating a configuration of a delay circuit of the real-time clock module illustrated in FIG. 1;

FIG. 6 is a timing chart showing an operation of the delay circuit shown in FIG.

FIG. 7 is a block diagram showing a configuration of a different example of the delay circuit of the real-time clock module shown in FIG. 1;

8 is a timing chart showing an operation of the delay circuit shown in FIG.

FIG. 9 is a timing chart summarizing the operation of the real-time clock module shown in FIG. 1;

FIG. 10 Instead of a real-time clock module,
FIG. 3 is a block diagram illustrating a configuration of a clock oscillator that can supply a reference clock signal.

FIG. 11 is a block diagram showing a configuration of an operation clock supply unit shown in FIG. 1;

FIG. 12 is a table showing setting values used in an operation clock supply unit;

FIG. 13 is a block diagram illustrating a configuration of a control unit of the operation clock supply unit.

FIG. 14 is a block diagram illustrating a configuration of an operation clock supply unit and a method of setting control terminals.

FIG. 15 is a layout diagram showing a state in which the operation clock supply unit is resin-molded.

FIG. 16 is a block diagram showing a configuration of an operation clock supply unit incorporating a pull-up resistor.

17 is a layout view showing a state in which the operation clock supply unit shown in FIG. 16 is resin-molded.

FIG. 18 is a block diagram showing a configuration of an operation clock supply unit using a fuse ROM.

FIG. 19 is a block diagram showing a schematic configuration of an information processing apparatus using a different clock supply system according to the present invention.

FIG. 20 is a block diagram showing a system using a conventional clock oscillator.

FIG. 21 is a block diagram showing a system using a conventional multi-output oscillator.

FIG. 22 is a block diagram showing a system in which a clock signal generation circuit is built in a conventional processing unit.

[Explanation of symbols]

1. Information processing device 2. CPU 3. FDD / HDD unit 4. Bus control unit 5. Communication unit 6. VGA unit 7. Keyboard unit 10. Real time clock module 11. Voltage detection circuit 12, delay circuit 13, crystal oscillator 14, oscillation circuit 15, RTC circuit 16, switching circuit 17, oscillation frequency processing circuit 20, operation clock supply unit 21, clock input unit 22, 22a, 22b ··· Synthesizer unit 23 ··· Control unit 24, 26, 65 ··· Programmable divider (P
D) 25 PLL circuit 30 Main power supply 31 Backup power supply 61 Phase comparator 62 Low pass filter 63 VCO 66, 66a, 66b Decoder circuit 67, 67a, 67b PROM 71 IC chip 72 Island part 73 Au wire 74 Gate terminal 75 S0 terminal 76 S1 terminal 77 S2 terminal 78 Power down or output enable control terminal 79 OUT terminal 80 ・ ・ VDD terminal 81 ・ ・ VSS terminal

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toru Shiratori 3-3-5 Yamato, Suwa City, Nagano Prefecture Inside Seiko Epson Corporation (72) Inventor Masayuki Kikushima 3-3-5 Yamato, Suwa City, Nagano Prefecture (56) References JP-A-4-140812 (JP, A) JP-A-4-139964 (JP, A) JP-A-2-224104 (JP, A) JP-A-60-20223 (JP, A) JP-A-2-307112 (JP, A) JP-A-2-86207 (JP, A) JP-A-1-228006 (JP, A) JP-A-5-265595 (JP, A) Kaihei 4-70912 (JP, A) Japanese Utility Model Showa 64-27722 (JP, U) Japanese Utility Model Showa 57-191154 (JP, U) Tokuyo Sho 60-502274 (JP, A) (58) Fields surveyed (58) Int.Cl. ⁷ , DB name) G06F 1/04-1/10 G06F 1/28

Claims (11)

(57) [Claims] 1. A oscillation <br/> means to oscillate a reference signal of constant frequency, a reference clock supply means for supplying a reference clock signal based on the reference signal of this, at least the time and calendar by said reference signal Hands timing one
A real-time clock module comprising: a stage; and at least one operation clock having a function of independently supplying an operation clock signal of a predetermined frequency to at least one processing unit performing processing based on a clock signal. and a supply unit, the operation clock supply unit is supplied with the reference clock signal from the real time clock module, a frequency synthesizer means for generating said operational clock signal the reference clock signal by multiplying or dividing Control means for controlling the frequency of the operation clock signal generated by the frequency synthesizer means .
The real-time clock module comprises a main power supply and
Battery power, and the main power supply
Voltage against the battery power supply voltage and a specified voltage
Means, the voltage of the main power supply is the voltage of the battery power supply and
When the voltage is lower than any of the specified voltages, the reference clock
Means for stopping supply of a signal . 2. The operation clock supply unit according to claim 1, wherein the operation clock supply unit is disposed near the processing unit, and a distance between the operation clock supply unit and the processing unit is equal to the operation clock supply unit and the real-time clock. The operation clock supply unit supplies a high-frequency operation clock signal to the processing unit, and the real-time clock module supplies the operation clock to the processing clock. A clock supply system, wherein a low-frequency reference clock signal is supplied to a supply unit. 3. The real-time clock module according to claim 1 , wherein the voltage of the main power supply is higher than any of the voltage of the battery power supply and the specified voltage, or the voltage of the other is higher than any one of the voltages. A clock supply system comprising means capable of supplying a reset signal to the processing unit after a predetermined time has elapsed from the time when the clocks have become equal. 4. The frequency synthesizer according to claim 1, wherein the frequency synthesizer is capable of generating the operation clock signal having a different frequency by changing a set value thereof.
The clock supply system according to claim 1, wherein the control unit includes a setting unit that sets a set value for oscillating at a predetermined frequency from the plurality of set values in the frequency synthesizer unit. 5. The PLL circuit according to claim 4 , wherein said frequency synthesizer means compares a reference signal with an output signal oscillated by a voltage controlled oscillator by a phase comparator and supplies the output signal at a predetermined frequency. A clock supply system, further comprising an adjustment circuit for dividing the output signal by the set value and supplying the divided signal to the phase comparison circuit. 6. The control unit according to claim 4 , wherein the setting unit includes a storage unit that stores a plurality of set values, a control input unit that receives a control input supplied from outside the operation clock supply unit, And a decoding means for selecting a set value to be set in the frequency synthesizer means from the plurality of set values based on the plurality of set values. 7. A clock supply system according to claim 6 , wherein said control input means includes a plurality of input terminals and means for pulling up each of these input terminals. 8. The clock supply system according to claim 4 , wherein the setting unit includes a storage unit that stores only a set value set in the frequency synthesizer unit among the plurality of set values. . 9. A real-time clock module according to claim 1 or 3, the real-time clock module is configured to one of independent semiconductor substrate, further, the oscillating means includes a piezoelectric vibrator, real-time clock module, characterized in that it comprises an oscillation circuit for oscillating the <br/> piezoelectric vibrator. 10. A operation clock supply unit as claimed in any one of claims 4 to 8, one independent operation clock supply unit, characterized in that it is constituted on a semiconductor substrate. 11. An information processing apparatus characterized by having a clock supply system according to any one of claims 1 to 8.