JPH064169A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device capable of automatically changing the frequency of the CPU system clock of a semiconductor integrated circuit. CONSTITUTION:This device is comprised in such a manner that the frequency of the CPU system clock can be automatically changed by attaching a source voltage detection circuit 9 on the system clock generation circuit 8 of the semiconductor integrated circuit. By employing such configuration, it is possible to automatically change the frequency of the CPU system clock when the source voltage of the semiconductor integrated circuit is fluctuated and to provide the semiconductor device capable of preventing malfunction from occurring by controlling the operating speed of the semiconductor integrated circuit and with high reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a system clock generating circuit for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A conventional semiconductor device will be described below.

FIG. 2 is a block diagram of a system clock generating circuit of a conventional semiconductor integrated circuit. 1, 2 are capacitors, 3 are oscillators, 4 are original oscillator circuits, 5 are frequency dividing circuits, and 6 are
Is a multiplexer (hereinafter referred to as MPX), 7 is a register, and 8 is a CPU system clock generation circuit. The operation of the semiconductor device configured as described above will be described below. The original oscillation circuit 4 to which the capacitors 1 and 2 and the oscillator 3 are connected outputs an oscillation output according to the oscillation frequency of the oscillator 3 to the frequency dividing circuit 5. The frequency divider circuit 5 divides the output of the original oscillator circuit 4 and outputs several kinds of frequency division outputs to the MPX 6. Arbitrary data can be set in the register 7, and a signal according to the set data is output to the MPX 6. With this output, the MPX 6 controls which frequency division output from the frequency division circuit 5 is selected. The MPX 6 controlled by the output of the register 7 selects one of the frequency division outputs from the frequency division circuit 5 and outputs the selected signal to the CPU system clock generation circuit 8. The CPU system clock generation circuit 8 generates a system clock for the CPU based on the signal from the MPX6.

[0004]

However, the above-mentioned conventional configuration has a problem that the semiconductor integrated circuit malfunctions when the power supply voltage drops and becomes lower than a certain voltage. Semiconductor integrated circuits generally have a slow operation speed (that is, C
The lower the PU system clock frequency is, the lower the system voltage can operate. Therefore, in the above-described conventional configuration, when the power supply voltage drops, it is impossible to lower the CPU system clock frequency. If the frequency of the CPU system clock can be lowered, even if the power supply voltage drops, the semiconductor integrated circuit only slows down its operating speed and does not malfunction.

An object of the present invention is to solve the above-mentioned conventional problems, and an object thereof is to provide a semiconductor device capable of automatically changing a CPU system clock of a semiconductor integrated circuit in accordance with a drop in a power supply voltage.

[0006]

In order to achieve this object, a semiconductor device according to the present invention has a power supply voltage for automatically changing the frequency of a CPU system clock in a system clock generating circuit of a semiconductor integrated circuit. It has a configuration with a detection circuit added.

[0007]

With the above structure, the system clock automatically changes even when a power supply voltage drop occurs in the semiconductor integrated circuit, and the semiconductor integrated circuit does not malfunction.

[0008]

1 is a block diagram of a system clock generating circuit of a semiconductor device according to an embodiment of the present invention.
The same parts as those of the conventional example are denoted by the same reference numerals and the description thereof will be omitted. That is, a feature of the present invention is that the power supply voltage detection circuit 9 is added. The operation will be described below. The original oscillation circuit 4 to which the capacitors 1 and 2 and the oscillator 3 are connected outputs an oscillation output according to the oscillation frequency of the oscillator 3 to the frequency dividing circuit 5. The frequency divider circuit 5 divides the output of the original oscillator circuit 4 and outputs several kinds of frequency division outputs to the MPX 6. Arbitrary data can be set in the register 7, and a signal according to the set data is output to the MPX 6. This output causes MPX6
Controls which frequency division output from the frequency division circuit 5 is selected. The power supply voltage detection circuit 9 constantly monitors the power supply voltage, and when the power supply voltage drops, outputs a signal according to the power supply voltage to the MPX 6. This output causes the MPX 6 to change the selection of the output from the frequency dividing circuit 5 (when the power supply voltage drops, an output signal with a low frequency is selected, and when the power supply voltage returns to the original output signal, Select). MPX6
Is controlled by the output signals of the register 7 and the power supply voltage detection circuit 9, but is preferentially controlled by the output signal of the power supply voltage detection circuit 9. The MPX 6 controlled by the output of the power supply voltage detection circuit 9 and the register 7 selects one of the frequency division outputs from the frequency division circuit 5 and outputs the selection signal to the CPU system clock generation circuit 8. The CPU system clock generation circuit 8 generates a system clock for the CPU based on the signal from the MPX6. At this time, if the power supply voltage drops for some reason, the MPX 6 changes the selection of the output from the frequency dividing circuit 5 and selects an output signal with a low frequency. Then, the CPU system clock generation circuit 8 generates a CPU system clock having a frequency lower than that before the power supply voltage drop, reduces the operation speed of the semiconductor integrated circuit, and prevents malfunction. As described above, according to this embodiment, it is possible to automatically change the frequency of the CPU system clock when the power supply voltage of the semiconductor integrated circuit changes.

[0009]

As is apparent from the above embodiments, the present invention has a configuration in which a power supply voltage detection circuit for automatically changing the frequency of the CPU system clock is added, so that the power supply voltage of the semiconductor integrated circuit is increased. Can change the frequency of the CPU system clock automatically, and can control the operating speed of the semiconductor integrated circuit to prevent malfunction and provide a highly reliable semiconductor device.

[Brief description of drawings]

FIG. 1 is a block diagram of a system clock generation circuit of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a system clock generation circuit of a conventional semiconductor device.

[Explanation of symbols]

 1, 2 Capacitor 3 Oscillator 4 Original oscillator circuit 5 Dividing circuit 6 Multiplexer (MPX) 7 Register 8 CPU system clock generation circuit 9 Power supply voltage detection circuit

Claims (1)

[Claims] 1. A semiconductor device, wherein a power supply voltage detection circuit for automatically changing the frequency of a CPU system clock is added to a system clock generation circuit of a semiconductor integrated circuit.