JPH0763146B2 - Standby circuit - Google Patents

Description

The present invention relates to a semiconductor circuit capable of starting and stopping an operation of a circuit including an oscillation circuit with one input terminal, and more particularly to a standby circuit for controlling an operation / stop state.

As for the standby circuit, conventionally, in a semiconductor integrated circuit with a built-in oscillation circuit, the start and stop of oscillation is controlled by a dedicated input terminal, or the oscillation circuit itself starts its operation at the same time when the power is turned on and an operation start signal from the outside. There is known a method such as applying a gate so that the internal circuit starts to operate. However, there are drawbacks such as the need for a dedicated input terminal and the large current consumption because the oscillator circuit is operating.

The present invention eliminates such drawbacks, an oscillation circuit, and a frequency dividing circuit for dividing and outputting an oscillation signal from the oscillation circuit,
In a semiconductor circuit having an internal circuit for inputting a signal obtained based on oscillation of the oscillation circuit, the oscillation circuit,
An input terminal for inputting a signal for switching the operation / stop state of the frequency dividing circuit and the internal circuit, and the oscillation circuit, the frequency dividing circuit, and the input circuit when a first signal is input to the input terminal. When it is detected that the internal circuit is in an operating state, the second signal is input to the input terminal, and the frequency dividing circuit is in the operating state, the oscillator circuit, the frequency dividing circuit, and the internal circuit And a control circuit that brings the device into a stopped state.

Hereinafter, the present invention will be described in detail based on examples. FIG. 1 shows an embodiment of the present invention, in which A and B are oscillation terminals, C is an operation start / stop control input terminal, 1 is a frequency divider circuit, 2 is a 1/2 frequency flip-flop, and 3 is An internal circuit of the semiconductor integrated circuit, 4 is a D-type flip-flop, 5 is an RS flip-flop, and 6 is an oscillation circuit. When the power is turned on, a signal that changes from "L" level to "H" level is supplied to the signal line H. The signal K becomes "H" level and the RS flip-flop 5 stores the "H" level. Further, the signal M becomes the "L" level, the frequency dividing circuit 1, 1/2 the frequency of the flip-flop 2, and the D-type flip-flop 4 are reset. The signal I is at the "L" level, the signal J is at the "H" level, L becomes "H" level and fixed. On the other hand, the clock P supplied to the frequency dividing circuit 1 is fixed to the "L" level while the operation of the oscillation circuit 6 is stopped. Internal circuit 3 of semiconductor integrated circuit
, The operation is stopped because the output signal J of the flip-flop 2 of the 1/2 frequency division is fixed to the "H" level.

When the signal having the waveform shown in the time chart C in FIG. 2 is input to the operation start / stop control input terminal C (hereinafter referred to as the input terminal C), the signal N is at the "H" level at the first rising of the signal. become. Since the output signal I of the frequency dividing circuit 1 is at "L" level, the signal O is at "H" level.

Since the signal H is also at "H" level, the signal K is at "L" level. Therefore, the signal M becomes "H" level and the oscillation circuit 6 starts oscillation and supplies the clock P to the frequency dividing circuit 1.
The frequency divider circuits 1, 1/2 frequency division flip-flops 2, and D-type flip-flops 4 are released from reset and start operating. As shown in the time chart of FIG. 2, when the output signal I of the frequency dividing circuit 1 becomes "H" level, the input terminal C becomes "L".
Since it is at level, the signal O becomes "L" level and the signal K becomes "H" level.

Therefore, the signal M becomes "L" level, and the frequency dividing circuit is 1/2.
Dividing flip-flop 2 and D-type flip-flop 4
Is reset again. The oscillator circuit 6 also stops oscillation.

Next, when the signal having the waveform shown in the time chart C in FIG. 3 is input to the input terminal C, the signal N becomes "H" level at the first rising edge of the signal. At this time, the signal O becomes "H" level because the output signal I of the frequency dividing circuit 1 is at "L" level, and the signal K becomes "L" level. Therefore, the signal M becomes "H" level, the oscillation circuit 6 starts the oscillation, and the frequency dividing circuits 1, 2 and the frequency dividing circuit 2 and the D-type flip-flop 4 are released from reset and start the operation. When the output I of the frequency divider 1 goes to "H" level, the input terminal C is already stable at "H" level, so the signal O remains at H level. In other words, when the frequency dividing circuit 1 starts oscillating and the signal I is set to "H", the signal at the input terminal C is stable at "H" level, so that the signal O is not affected by chattering. Of.

When the signal I changes from "H" level to "L" level, the signal J
Becomes "H" level, a clock signal is supplied to the internal circuit 3 of the semiconductor integrated circuit, and the operation is started. At this time, the output signal L of the D-type flip-flop 4 becomes "L" level.
When the input terminal C becomes "L" level and the signal I becomes "H" level, the signal O becomes "L" level and the signal K becomes "H" level. Next, when the signal J changes from "H" level to "L" level, the signal L becomes "H" level and the signal M becomes "L" level. The oscillating circuit 6 stops oscillating, and the frequency dividing circuits 1, 2 and the flip-flop 2 and the D-type flip-flop 4 are reset. The output signal J of the flip-flop, which is divided by half, is fixed to the "H" level, so that the internal circuit 3 of the semiconductor integrated circuit stops its operation.

The present invention has an excellent effect that the start / stop of oscillation and the start / stop of the operation of the internal circuit of the semiconductor integrated circuit can be controlled by one input terminal, and the consumption current of the input terminal can be reduced.

Further, according to the present invention, chattering of the input terminal can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a standby circuit of the present invention, and FIGS. 2 and 3 are time charts for explaining the same. 1-dividing circuit 2-1 / 2 dividing flip-flop 3-internal circuit of semiconductor integrated circuit 4--D-type flip-flop 5-RS RS flip-flop 6-oscillating circuit A, B-oscillating terminal C ...... Operation start / stop control input terminals

Claims (1)

[Claims] 1. A semiconductor circuit having an oscillation circuit, a frequency dividing circuit for dividing and outputting an oscillation signal from the oscillation circuit, and an internal circuit for inputting a signal obtained based on oscillation of the oscillation circuit, Operation of oscillator circuit, frequency divider circuit and internal circuit
An input terminal for inputting a signal for switching a stop state; and when the first signal is input to the input terminal, activates the oscillation circuit, the frequency dividing circuit, and the internal circuit, and the input terminal And a control circuit that puts the oscillation circuit, the frequency dividing circuit, and the internal circuit into a stopped state when a second signal is input to and the frequency dividing circuit detects that the frequency dividing circuit is in an operating state. A semiconductor circuit characterized by the above.