JPH0662562A - Charge pump circuit - Google Patents

Abstract

PURPOSE:To prevent the increased amount of electric power from being consumed by an excessive upthrust. CONSTITUTION:A clock signal inputted into an upthrusting capacitor of a charge pump 2 can be selected by a clock switching circuit 3, and hence the upthrusting speed of the charge pump 2 is increased. Also, after upthrusting by the charge pump 2 has been completed once, excessive upthrusting is prevented by inputting a clock signal having a low frequency, whereby electric power to be consumed can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit, and more particularly to a power consumption reduction circuit for a charge pump circuit.

[0002]

2. Description of the Related Art In FIG. 4, a conventional charge pump circuit according to the present invention includes N-channel transistors N1 to N1.
N6, the inverter I1, the capacitors C1 and C2,
It is provided with P-chan transistors P1 and P2.

As shown in FIG. 4, the conventional charge pump circuit has capacitors C1 and C2 for pushing up the clock φ.
Are typing in. When the clock φ is at a high level, the capacity of the capacitor C1 pushes up the voltage at the point B, and when the clock φ is at a low level, the capacity of the capacitor C2 pushes up the voltage at the point C. .

By this operation, the level at the OUT point is pushed up. In addition, in order to increase the speed of increasing the level at the OUT point, the clock φ
It uses a higher frequency or uses multiple boost capacitors. In FIG. 4, two capacitors C1 and C2 for pushing up are used. N-chan transistor N5, N
6 is for preventing the level at the OUT point from becoming higher than a certain arbitrary level. When the level becomes higher than the set level, the transistors N5 and N6 are turned on, and a current is supplied to the power supply VCC, thereby the level at the OUT point. Is preventing the rise of.

[0005]

In such a conventional charge pump circuit, the clock frequency is increased or a plurality of boosting capacitors C1 and C2 are used in order to ensure the speed of boosting the voltage. is doing. In fact, in order to stabilize the voltage of the line that was pushed up,
It boosts the voltage above the required level, allowing the excess to escape. Providing a high frequency is effective in increasing the speed of pushing up the voltage, but once the level is raised, considering that the voltage level hardly decreases, it is sufficient to give a low frequency and a high frequency. Continuing to give the voltage increases the surplus voltage, which causes a problem of increasing the power consumption.

An object of the present invention is to solve the above problems and to provide a charge pump circuit which does not increase power consumption.

[0007]

A charge pump circuit according to the present invention has a clock switching circuit for inputting a plurality of clocks having different frequencies and selecting and outputting the clock, and the clock switching circuit. It is characterized in that the output level of the charge pump is pushed up by the output clock from.

[0008]

1 is a block diagram showing a control circuit of a charge pump circuit according to a first embodiment of the present invention. In FIG. 1, the charge pump control circuit of the present embodiment inputs a charge pump operation start signal 7 to the counter 4, and after the charge pump 2 completes pushing up, the signal from the counter 4 is sent to the clock switching circuit 3. It is configured to be input.

With this configuration, the pushing speed is secured by the clock (φ1) 5 before the pushing is completed, and after the pushing is completed once, the clock (φ2) 6 having a lower frequency than the clock (φ1) 5 is used. The power consumption can be reduced.

FIG. 2 is a block diagram showing a second embodiment of the present invention. In FIG. 2, this embodiment is an embodiment in which the clock input to the boosting capacitor of the charge pump is generated by the frequency dividing circuit 12.

A counter 11 to which a start signal 14 is input,
The charge pump 9 and the like are the same as in FIG.

The frequency dividing circuit 12 to which the clock (φ) 13 is input generates a plurality of clocks having different frequencies, and the clock switching circuit 10 selects the clock to be input to the boosting capacitor of the charge pump.

Here, by analyzing the evaluation result of the device and selecting the frequency required for starting the charge pump and the minimum frequency required for maintaining the level of the output line by the clock switching circuit 10. , The optimum frequency combination can be realized.

FIG. 3 is a timing diagram of the charge pump of FIG. In FIG. 3, the clock input to the push-up capacitor and the level of the output line are shown. First, the clock has a high frequency in order to speed up the pushing up by the charge pump 2. After that, when the output line 1 of the charge pump 2 rises above a required level, the clock is switched to a low clock. VC is a limit voltage for preventing an excessive rise in voltage, and a portion above this VC is released, which is an increase in power consumption. Therefore, the power consumption can be reduced by lowering the clock frequency. Also in FIG. 2, power consumption can be reduced as in FIG.

[0015]

As described above, according to the present invention, by switching the clock input to the boosting capacitor of the charge pump, the speed of pushing up the output line is ensured, and after the push-up is completed, there is an excess. There is an effect that the power consumption can be reduced by reducing the push-up.

[Brief description of drawings]

FIG. 1 is a block diagram showing a charge pump circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a timing chart of the charge pump of the present embodiment.

FIG. 4 is a circuit diagram of a conventional charge pump.

[Explanation of symbols]

 1,8 Charge pump output line 2,9 Charge pump 3,10 Clock switching circuit 4,11 Counter 5,6,13 Clock 7,14 Charge pump operation start signal 12 Divider circuit

Claims (2)

[Claims] 1. A clock switching circuit for inputting a plurality of clocks having different frequencies and selecting and outputting the plurality of clocks, wherein the output level of the charge pump is adjusted by the clock output from the clock switching circuit. A charge pump circuit characterized by being pushed up. 2. The charge pump circuit according to claim 1, wherein the plurality of clocks include a basic clock and a divided clock obtained by dividing the basic clock.