JPS5912826Y2 - oscillator - Google Patents

Description

[Detailed explanation of the idea] The present invention relates to an oscillator.

For example, a magnetic recording/reproducing device employs a self-clocking recording method, and generates a clock signal from input data.

In addition, clock signals are also generated from human data in data demodulation systems and the like.

In this case, a phase synchronization system is required to generate the clock signal, and this phase synchronization system includes a PLL.
A closed-loop control circuit technique called a (Phase-Lock-Loop) circuit is widely used.

As is well known, this PLL circuit compares the phase of a signal obtained by a voltage controlled oscillator with an input synchronizing signal, and changes the input control voltage of the voltage controlled oscillator according to the phase difference. It is something.

However, when a clock signal is generated from input data in a magnetic recording/reproducing device, for example, special operating conditions are placed on the voltage-controlled oscillator of the PLL circuit that constitutes the phase synchronization system.

One of these conditions is that the oscillation of the voltage controlled oscillator must be temporarily stopped in order to resynchronize with the input synchronization signal, and the other is that the oscillation of the voltage controlled oscillator must be temporarily stopped in order to resynchronize with the input synchronization signal. When restarting the oscillation, the oscillation must be started at a predetermined phase.

SUMMARY OF THE INVENTION The object of the present invention is to propose a so-called start-stop oscillator that can satisfy the above two operating conditions.

In accordance with the above objectives, the present invention uses an emitter capacitively coupled astable multivibrator circuit as a voltage controlled oscillator,
The oscillation is stopped by clamping one of a pair of Schmitt circuits constituting the circuit to a predetermined potential, and the oscillation is restarted by releasing the clamp.

The present invention will be explained below according to the drawings.

FIG. 1 is a block diagram showing a phase synchronization system including a voltage controlled oscillator to which the present invention is applied.

In this figure, blocks 11, 12 and 13 are conventional parts, and block 11 is a phase difference detector,
Block 12 is a loop filter, and block 13 is a voltage controlled oscillator.

The phase difference detector 11 receives an input synchronizing signal Sin and a feedback output synchronizing signal S from the oscillator 13.

ut and detect the phase difference.

The voltage corresponding to this phase difference is band-limited by a loop filter 12, and the output of the loop filter 12 is used as an oscillation control input for an oscillator 13.

In FIG. 1, block 14 is a clamp circuit;
This is a part added based on the present invention.

The clamp circuit 14 receives the input synchronization signal S.

and an oscillation start/stop command signal S5, and controls the oscillation start and oscillation stop of the oscillator 13, that is, the phase synchronization system 10, by the control output q.

FIG. 2 shows blocks 13 and 14 in FIG. 1 in more detail.

The portions surrounded by solid lines 13 and 14 in FIG. 2 are the oscillator and clamp circuit described above.

First, regarding the oscillator 13, the transistor Q1 is connected to the power supply Vcc through a load resistor Rc1, and the transistor Q2 is connected to the power supply Vcc through a load resistor Rc2.

In addition, a capacitor C is connected between both emitters of the transistors Q1 and Q2, and constant current sources S1 and S2 that linearly discharge the capacitor C have an oscillating same wave number control voltage V
C is connected to each of the emitters.

Transistor Q3. Q4 and constant current source S3 constitute a differential input constant current switch circuit.

Also, the transistor Q constituting the differential input current switch
3. Q4 on the other hand respectively transistors Q1. Q
2 to form a Schmitt circuit.

Output of one Schmitt circuit is fed back to the other Schmitt circuit through a capacitor C, and an emitter capacitive coupling type is formed. Operation as an oscillator consisting of astable multi-byte breaks is realized.

When stopping and starting oscillation for the oscillator 13 shown in FIG. 2, the capacitor C may be charged abnormally or not charged at all. , the phase at which the oscillation started was completely random, which was a serious problem for a phase-locked system.

For this reason, it has been common practice not to apply oscillation stop or oscillation start to the oscillator 13.

Therefore, in the present invention, the initial value of the charging voltage of the capacitor C after the oscillation is stopped, that is, before the oscillation is started, is clamped to a constant value.

If the next oscillation is started from this clamped charging state of the capacitor C, the first oscillation frequency will start at the same frequency as the previous oscillation frequency.

As the clamping means, the present invention uses a transistor Q3.
The base level of is maintained at a constant level.

In this case, it must be clamped at a level that does not saturate transistor Q0.

By not saturating the transistor Q1, the discharge current value of the capacitor C is suppressed to a small value, and the current switch Q3. Q4
stops its switching operation, transistor Q3 is turned on, transistor Q4 is turned off, this state is maintained, and oscillation is stopped.

As a result, the base of transistor Q1 is fixed at H level and the base of transistor Q2 is fixed at L level.

Thereafter, when the emitter level of the transistor Q2 falls to the point where it turns on, the current flow to the capacitor C is stopped, and the charged state of the capacitor C is maintained in this state.

This state of charge is always constant, and the initial activation cycle is also constant.

In FIG. 2, a clamp circuit 14 performs the aforementioned clamping operation.

The clamp circuit 14 includes, for example, a transistor Q5, a resistor R5, and a flip-flop circuit FF that controls switching of the transistor Q5. Turn on transistor Q5 and set the base level of transistor Q3 to resistor R.
Clamp to the value divided by c0 and R8.

On the other hand, when the oscillation start/stop command signal C5 instructs to start oscillation and the input synchronization signal Sln is received, oscillation is started at the timing of this reception.

Figure 3 shows the on/off state of transistor Q5 and the output O
It is a time chart showing the waveforms of 0UT1 and 0UT2 in UT, and the period T1 when transistor Q5 is on.
In this case, both 0UT1 and 0UT2 have stopped outputting (oscillation non-operation), and in period T2 when transistor Q5 is off, 0U
T1 and 0UT2 are output in the relationship shown (oscillation operation).

As shown in the figure, the period is constant from the first period at the start of oscillation of 0UT1 (OUT2).

In Figure 2, a flip-flop circuit F is used as a clamp circuit.
Although the configuration of F and the transistor Q5 is shown, the configuration is not limited to this example, and can also be realized by combining a diode connected in series at the anode to the resistor R8, and a TTL circuit connected in series to the diode and its cathode.

In this case, if cc (FIG. 2) is set to +5, the diode is cut off and oscillation starts when the output of the TTL circuit is at H level.

When the output of the TTL circuit is at L level, the base of transistor Q3 is clamped to a predetermined level and oscillation is stopped.

Finally, the oscillation operation of the oscillator 13 in FIG. 2 will be explained.

First, transistor Q3 is turned on and transistor Q4 is turned off.

Since the transistor Q3 is on, the current from the constant current source S3 flows to the transistor Q3 side.

Therefore, the base level of transistor Q1 is at H level, and the base level of transistor Q2 is at L level.

This L level is the ground level.

Assuming that capacitor C is not charged at all in the initial state, both emitter potentials of transistors Q1 and Q2 are at the same level.

Therefore, the emitter potential of transistor Q2 is the same as the emitter potential of transistor Q1 whose base is currently at H level, and since the base of transistor Q2 is at L level, transistor Q2 is turned off.

Oscillation operation starts from this point.

Since transistor Q2 is off, constant current I2 flows through capacitor C.

As a result, the capacitor C is charged, and the potential on the transistor Q2 side of the capacitor C, that is, the emitter potential of the transistor Q2, falls linearly. (FIG. 4 II shows the waveforms of the emitter potential QE2 of the transistor Q2.)

The linear descent is caused by constant current drive (
This is because the current I2) is applied.

The emitter potential QE2 continues to fall linearly to a level that turns on the transistor Q2 even if the base of the transistor Q2 is at the L level.

Finally, at time t1, transistor Q2 is also inverted from off to on.

Until now, the base of transistor Q4 was
2 is off, it was at the H level, which is the same as the Vcc level.

On the other hand, the base of transistor Q3 was at L level since transistor Q1 was on.

Thus, transistor Q3 is on and transistor Q4 is on.
The state of OFF was maintained stably.

Since the transistor Q2 has now been inverted from off to on, the base level of the transistor Q4 falls, and on the other hand, the current that has been supplied to the capacitor C through the transistor Q1 decreases.

Therefore, the base level of transistor Q3 begins to rise,
After the base level VB3 of the transistor Q3 and the base level VB4 of the transistor Q4 become almost the same level, the transistor Q3 is turned off and the transistor Q4 is turned on.

Since transistor Q4 is turned on, transistor Q
The base of 2 becomes H level.

At this time, the base of transistor Q1 becomes L level.

Thus, the emitter potential of transistor Q2 becomes H level.

However, since the voltage across the capacitor C cannot change rapidly, the emitter potential of the transistor Q1 is raised to the high level of the capacitor C (tl in Figure 4).
.

Therefore, the transistor Q1 suddenly becomes cut off, and accordingly, the base level of the transistor Q3 also becomes H level, and the transistor Q3 becomes cut off.

As a result, the current to be applied to the capacitor C is supplied as a constant current I2 through the transistor Q2.

Therefore, the base level of the transistor Q4 further decreases, and the transistor Q3 becomes stable in the opposite state as described above, with the transistor Q3 turned off and the transistor Q4 turned on.

From now on, the capacitor C will be linearly discharged by the constant current 11 via the transistor Q2 (see partial waveform ① in FIG. 4I).

After the voltage across capacitor C becomes zero at time t2,
This time, the capacitor C is charged in the opposite direction to that described above (see partial waveform ① in FIG. 4I).

As a result, the potential on the side of the transistor Q1 of the capacitor C reaches an emitter potential that turns on the transistor Q1 even when the base of the transistor Q1 is at the L level.

Here, the transistor Q1 is turned on again, and the same inversion as described above occurs at time t3, and the same operation is repeated thereafter, and an oscillation output is output from the output terminal OUT.

As explained above, according to the present invention, an oscillator that can temporarily stop oscillation and start oscillation at a predetermined phase is realized.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a phase synchronization system including an oscillator to which the present invention is applied, Fig. 2 is a circuit diagram showing blocks 13 and 14 shown in Fig. 1 in detail, and Fig. 3 is the operation of Fig. 2. The time chart used in the explanation and FIG. 4 are waveform diagrams used in explaining the operation of the oscillator 13 in FIG. In the figure, 13 is an oscillator, 14 is a clamp circuit, and R8
is a clamping resistor, and Q5 is a switching transistor.

Claims (1)

[Claims for Utility Model Registration] ■ A pair of transistors Q1 and Q2; a capacitor C connected between the emitters of the pair of transistors Q1 and Q2; and a capacitor C connected to each emitter of the pair of transistors Q1 and Q2; a pair of constant current sources S1 and S2 controlled by the oscillation frequency control voltage Vc; a transistor Q3 connected to form a first Schmitt circuit together with the transistor Q1; and the transistor Q2
transistor Q4 connected together to form a second Schmitt circuit, and transistors Q3 and Q
a differential input constant current switch circuit constituted by a constant current source S3 with reference numeral 4 as a differential input current switch; the collector of the transistor Q1 and a power source (2); the load resistor Rc1 connected between; and the transistor Q
2, and a load resistor Rc2 connected between the collector of VCE and the power supply Vce, and a resistor R5 connected in series.
and an oscillator, characterized in that a switching means is inserted between the base of the transistor Q3 and the ground, and the switching means is made conductive and non-conductive in response to oscillation stop and oscillation start. 2. The oscillator according to claim 1, wherein the switching means comprises a transistor Q5. 3. The oscillator according to claim 1, wherein the switching means is a diode.