JPS6110367A - Vertical deflection synchronizing circuit - Google Patents

Abstract

PURPOSE:To discriminate accurately the presence of a vertical synchronizing signal by providing a timer circuit and detecting its output signal if it does not exist even after a prescribed period or over and applying a drive pulse to generate a pseudo sawtooth waveform at the same time. CONSTITUTION:A signal fed to an input terminal 13 of a vertical synchronizing signal is inputted to the timer circuit 15 through a gate circuit 14. An output of the timer circuit 15 is inputted to the timer circuit 15 through a gate circuit 14. The output of the timer circuit 15 enters the base of a transistor (TR)17 through a resistor 16. A collector of the TR17 is connected to a charge capacitor 18 and a constant current source 19 generating a sawtooth wave. The output of the timer circuit 15 is fed to a TR23 through resistors 21, 22. A timing resistor 24 and a capacitor 25 are connected to the collector of the TR23 and a connecting point between the resistor 24 and the collector is connected to an inverter 26. An output terminal of the inverter 26 is connected to other input terminals of the gate circuit 14.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vertical deflection synchronization circuit used for vertical deflection in CRT (cathode ray tube) display monitors and the like.

Conventional configuration and its problems FIG. 1 shows a conventional vertical deflection synchronization circuit.

The configuration of this conventional example will be explained below with reference to FIG. 1. In FIG. 1, reference numeral 1 denotes an input terminal to which a vertical synchronizing signal is input, and this vertical synchronizing signal input terminal 1 is connected to the base of a transistor 3 via a resistor 2. resistance 4
and capacitor 5 are connected to the collector of transistor 3 and further connected to the base of transistor 7 via coupling capacitor 6. 8 is a resistor, this resistor 8
is connected to the base of transistor 7 and provides a bias current from the 10V power supply. A resistor 9 is connected to the collector of the transistor 7 and further connected to the base of the transistor 3 via a coupling capacitor 10. 11 is a variable resistor connected to the base of the transistor 3, and 12 is an output terminal.

Next, the operation of the above example will be explained. In Figure 1,
Transistors 3 and 7 are connected to each other by a coupling capacitor 10.6 and form a multivibrator.

The sawtooth wave is obtained from the collector of transistor 3, and transistor 7 has the function of amplifying it. General Vc
The Fi transistor 7 can be considered as a vertical deflection output stage. The variable resistor 11 determines the bias point of the transistor 3, and at the same time determines the oscillation frequency of the multivibrator constituted by the transistors 3 and 7. This oscillation frequency is adjusted to a value slightly longer than the vertical synchronization signal that enters input terminal 1, and when the synchronization signal is input, the base potential of transistor 3 is raised by this signal, and the multivibrator oscillates, so-called A synchronized state is obtained.

However, the above conventional example uses a feedback circuit to oscillate,
Furthermore, since synchronization and asynchrony are detected based on changes in the base voltage of the transistor, there is a drawback that it is susceptible to the effects of temperature, element variations, etc.

Purpose of the Invention The present invention eliminates the drawbacks of the conventional example described above, and aims to accurately determine the presence or absence of a vertical synchronization signal without being affected by temperature, element variations, etc. .

Structure of the Invention In order to achieve the above object, the Himi aA has a timer circuit, which detects when this output signal does not exist after a certain period of time and generates a pseudo sawtooth wave at the same time. It supplies driving pulses.

DESCRIPTION OF THE EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings.

In FIG. 2, 13 is the input terminal of the vertical synchronization signal,
The signal applied to this input terminal 13 is input to the timer circuit 15 through the gate circuit 14.

The output of timer circuit 15 enters the base of transistor 17 through resistor 16. The collector of transistor J7 is connected to a charge capacitor 18 and a constant current source 19 that generate a sawtooth wave. 2o is the output end of the sawtooth wave signal. Further, the output of the timer circuit 15 is applied to the transistor 23 through resistors 21 and 22. transistor 2
3 has a timing resistor 24 and a capacitor 2 at its collector.
5 is connected, and the connection point between the resistor 24 and the collector is connected to an inverter 26. Inverter 26
The output terminal of is connected to the other input terminal of the gate circuit 14.

Next, the operation of the above embodiment will be explained. When the vertical synchronization signal is input as in the third rotation, the timer circuit 15 outputs a pulse (FIG. 3(B)) having a fixed time width T with the rise of the synchronization signal as the starting point. The time width T of this pulse, the resistance 27 of the timer circuit 15. determined by capacitor 28.

Conopulse Q3)K makes transistor l7 0N-
When OFPL is ON, it absorbs the discharge current of the capacitor 18 and the current of the constant current source 19.

When OFF, the current ■ from the constant current source 19 flows through the capacitor 18.
is charged, and a sawtooth wave is generated at the output terminal 20 (Fig. 3 (Q)
is obtained. ■ The peak value of the sawtooth wave.

Then, the following relationship holds: r=cvp/Tt. Further, +TI corresponds to the retrace period of vertical deflection.

At the other end of the gate circuit 14 to which the synchronization signal is not connected, as long as the timer circuit 15 outputs a pulse with a constant period that matches the synchronization signal, the collector of the transistor 23 is at the LOW level as shown in FIG. 3 (Q). By setting the time constants of the resistor 24 and the capacitor 25 so that the voltage becomes high (that is, a value that does not exceed the threshold hold potential of the inverter 26), the output of the inverter 26 can be set to High level and the vertical synchronizing signal can be passed.

On the other hand, if there is no synchronization signal, the timer circuit 15 does not output a pulse and maintains the LOW level. At this time, the transistor 23 is in the OFF state, and the collector voltage is Vc=V(tz-r) :τ-C, 2X RT2
It goes up. Here, if the threshold hold level of the inverter 26 is VTR, then the resistor 24. If the capacitor 25 is selected, it becomes possible to detect the absence of a vertical synchronizing signal by extending T2 to T3. At the same time, immediately after T, inverter 2
6 (FIG. 3 CB)) becomes a low level and is input to the gate circuit 14, and the timer circuit 15 generates a positive direction pulse of time width T, as if a vertical synchronizing signal had been input. As long as there is no vertical synchronization signal, the pulses shown in FIG. 3CD> are repeated at a period of (TI+T3), and the sawtooth wave signal for vertical deflection can continue to be generated.

Effects of the Invention The present invention has the above-described configuration, and provides the following effects.

(a) The presence or absence of a vertical synchronization signal can be determined without being affected by temperature, element variations, etc.

(b) Since the presence or absence of the vertical synchronization signal is directly determined based on the time width of the pulse, reliable determination is possible.

(Vertical deflection is possible even in the absence of the C1 vertical synchronizing signal, and a bright spot bright line condition does not occur at one point or on the -water line, and therefore the probability of burning the CRT is drastically reduced.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram of a conventional vertical deflection synchronization circuit, FIG. 2 is an electric circuit diagram of a vertical deflection synchronization circuit according to an embodiment of the present invention, and FIG. 3 is a diagram showing waveforms of various parts of the circuit. . 13...Input end, 14...Gate circuit, 15...
Timer circuit, 16...Resistor, 17...Transistor, 18...Capacitor, 19・Constant current source, 20・
Output end, 21.22...Resistor, 23...Transistor,
24... Resistor, 25... Capacitor, 26... Inverter, 27... Resistor, 28 Capacitor. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3

Claims (1)

[Claims] A timer circuit that generates a pulse having a fixed time width from the rising or falling portion of a vertical synchronization signal, a first transistor that is switched by the output of this timer circuit, and a vertical deflection controlled by this first transistor. an integrator circuit that generates a sawtooth wave; a signal generation circuit that generates a sawtooth wave that is controlled by a second transistor switched by the output of the timer circuit; and an inverter to which the output of the signal generation circuit is applied. and a gate circuit to which the output of the inverter and the vertical synchronization signal are applied, and the output of the gate circuit is applied to the timer circuit.