JPH0526825Y2 - - Google Patents

Description

[Detailed description of the invention] [Field of industrial application] The present invention relates to a clock generation circuit, and particularly to a clock generation circuit that can manually stop clock pulses or generate an arbitrary number of clock pulses. It is.

[Conventional technology]

Conventionally, as this type of clock generation circuit, a circuit as shown in FIG. 2 has been used. In Figure 2, NPN transistor 1 and NPN transistor 2
Connect the emitters to constant current 9 in common,
The base of the NPN transistor 1 is connected to GND through a resistor 10, to GND through a capacitor 8, and to the first emitter of an NPN transistor 4 through a resistor 15, and the collector of the NPN transistor 1 is connected to a constant voltage source 6. The base of the NPN transistor 2 is connected to GND through the resistor 13, the constant voltage source 5 through the resistor 12, and the second emitter of the NPN transistor 4 through the resistor 11.
It is connected to the first collector and base of transistor 3. The emitter of PNP transistor 3 is
It is connected to a constant voltage source 6, and the second collector of the PNP transistor 3 is connected to the base of an NPN transistor 4. The third of NPN transistor 4
The emitter of the NPN transistor 4 is connected to the output terminal 7 and to GND through the resistor 14, and the collector of the NPN transistor 4 is connected to the constant voltage source 5.
This circuit includes a resistor 15 as a means for flowing a charging current into a capacitor 8, a resistor 10 as a means for discharging the charge of the capacitor 8, a Schmitt circuit, and a means for turning on and off the charging current according to the output state of the Schmitt circuit. It can be said that this is a combination of transistors 4 as shown in FIG.

In the circuit shown in Figure 2, when the constant voltage sources 5 and 6 are turned on, the capacitor 8 is discharged, so
NPN transistor 1 is turned off and NPN transistor 2 is turned on. NPN transistor 2 at this time
The base potential of is V _A , and the resistance value of resistor 12 is
R ₁₂ , the resistance value of the resistor 13 is R ₁₃ , and the constant voltage source 5
When the potential of the constant voltage source 6 is V _BB and the voltage of the constant voltage source 6 is V _CC , V _CC >V _BB and V _A =R ₁₃ /R ₁₂ +R ₁₃ ·V _BB (1). As a result, PNP transistor 3 is turned on, and then NPN transistor 4 is turned on. Therefore, the second emitter current of NPN transistor 4
I _E2 is connected to NPN transistor 2 through resistor 11.
flows to the base of , raising its potential.
The base potential of NPN transistor 2 at this time is V _B
If the resistance value of the resistor 11 is R ₁₁ , then the voltage V _BB of the constant voltage source 5 and the saturation voltage V _CESat of the NPN transistor 4 can be ignored. V _B = R _B /R ₁₃ + (R ₁₁ /R ₁₂ )・V _BB …(2).

By the way, as capacitor 8 is being charged,
When the base potential of NPN transistor 1 becomes higher than V _B , NPN transistor 1 turns on,
NPN transistor 2 turns off. As a result,
PNP transistor 3 is turned off, NPN transistor 4 is also turned off, and the base potential of NPN transistor 2 becomes V _A. Therefore, the electric charge charged in the capacitor 8 is discharged via the resistor 10. When the charge in the capacitor 8 is discharged and the base potential of the NPN transistor 1 decreases and becomes lower than V _A ,
It returns to its initial state and starts charging again. In the circuit shown in FIG. 2, the above operation is repeated and a clock pulse is generated from the output terminal 7.

[Problem that the invention attempts to solve]

The conventional clock generation circuit described above has a circuit configuration as shown in Figure 2, so when the constant voltage source is turned on, clock pulses are generated continuously.
The clock pulses will not stop unless the constant voltage source is turned off. Also, it is not possible to generate an arbitrary number of clock pulses. Another disadvantage is that when the clock pulse is stopped, for example, if a flip-flop circuit is provided after the clock generating circuit, a pulse cannot be generated to set the initial state of the flip-flop circuit.

[Means for solving the problem]

The clock generation circuit of the present invention includes a charging means for passing a charging current through a capacitor, a discharging means for discharging the capacitor, and a first reference voltage and a voltage input from the first reference voltage using the potential of the capacitor as input. a Schmitt circuit having a high second reference voltage; and control means for controlling on/off of the charging means according to the output state of the Schmitt circuit, the potential of the capacitor being set to the first and second reference voltages. In a clock generating circuit configured to be repeatedly charged and discharged between voltages, a first switch means for making the potential of the capacitor higher than the second reference voltage when in an on state; a second switching means for lowering the reference voltage than the first reference voltage; and a third switching means for one input.
a comparator circuit that receives a reference voltage and outputs a pulse corresponding to a period in which the input voltage supplied to the other input exceeds the third reference voltage; further comprising means for supplying, as the input signal, a differential signal whose peak value exceeds the third reference voltage to the other input of the comparator circuit, the pulses from the comparator circuit being set to the initial state of the system. It is characterized in that it is obtained as a setting signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The emitters of NPN transistor 1 and NPN transistor 2 are connected to a constant current source 9 in common, and the base of NPN transistor 1 is connected to GND through a resistor 10.
connected to the first emitter of the NPN transistor 4 through a resistor 15, and connected to the constant voltage source 5 through a series of a resistor 16 and a first switch 18;
Through the resistor 17 and the second switch 19 in series
It is connected to GND and to the base of the NPN transistor 21, and the collector of the NPN transistor 1 is connected to the constant voltage source 6. The base of NPN transistor 2 is connected to GND through resistor 13,
It is connected to the second emitter of the NPN transistor 4 through the constant voltage source 5 and the resistor 11 through the resistor 12, and the collector of the NPN transistor 2 is connected to the PNP
It is connected to the first collector and base of transistor 3. The emitter of PNP transistor 3 is
It is connected to a constant voltage source 6, and the second collector of the PNP transistor 3 is connected to the base of an NPN transistor 4. The third of NPN transistor 4
The emitter of NPN transistor 4 is connected to output terminal 7 and to GND through resistor 14, and the collector of NPN transistor 4 is connected to constant voltage source 5.
The emitter of the NPN transistor 21 and the emitter of the NPN transistor 22 are connected to the constant current source 24.
The collector of the NPN transistor 21 is connected to
Connected to the base and first collector of the PNP transistor 23. The base of the NPN transistor 22 is connected to the constant voltage source 25, and the base of the NPN transistor 22 is connected to the constant voltage source 25.
The collector of No. 2 is connected to a constant voltage source 6.
A second collector of the NPN transistor 23 is connected to the output terminal 26 and to GND via a resistor 27.
The emitter of the PNP transistor 23 is the constant voltage source 6
It is connected to the.

Next, the operation will be explained. As mentioned above, the first
When the first switch 18 and the second switch 19 are off, clock pulses are continuously generated from the first output terminal 7. Here, the resistance value of the resistor 16 is
If the base potential of NPN transistor 1 is set to be higher than V _B obtained by equation (2) when first switch 18 is turned on, the charge stored in capacitor 8 will be transferred to NPN transistor 1 when it is turned on. Despite this, it does not discharge, and as a result,
The output terminal 7 remains at a low level and no clock pulse is output. By the way, the timing from off to on of the first switch 18 is changed to the third switch.
If it is done as shown in the figure a, the NPN transistor 21
The base potential of , as shown in FIG. here,
When the potential of the constant voltage source 25 is set to V ₂₅ and the potential is set as shown in b in FIG. 3, a waveform as shown in c in FIG.

Next, while keeping the first switch 18 on, when the second switch 19 is pressed, the resistor 17 is set so that the base potential of the NPN transistor 1 becomes lower than V _A calculated by equation (1). When the second switch 19 is turned on, the charge stored in the capacitor 8 is transferred to the resistor 10 and the resistor 17.
, so that NPN transistor 1 is turned off and NPN transistor 2 is turned on. Therefore, the output terminal 7 outputs a high level. Next, when the second switch 19 is turned off, the state returns to the above-mentioned state, and from the output terminal 7,
One clock pulse will be output.

[Effect of idea]

As explained above, the present invention adds the resistor 16, resistor 17, capacitor 20, first switch 18, second switch 19, and comparator circuit to the conventional clock generation circuit.
The clock generation can be manually stopped without turning off the constant voltage source, and at the same time, the initial setting pulse can be generated, and an arbitrary number of clock pulses can be generated.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the clock generation circuit of the present invention, FIG. 2 is a diagram showing an example of the conventional clock generation circuit, and FIG. 3 is a diagram showing the input/output voltage of the comparator of the present invention. It is a diagram. 1, 2, 3, 4, 21, 22, 23...transistor, 5, 6, 25...constant voltage source, 7, 26...
...Output end, 8, 20...Capacitor, 9, 24...
... Constant voltage source, 10, 11, 12, 13, 14, 1
5, 16, 17, 27...Resistance, 18, 19...
Switch.

Claims (1)

[Scope of utility model registration request] It has a charging means for passing a charging current through the capacitor, a discharging means for discharging the capacitor, a first reference voltage that receives the potential of the capacitor, and a second reference voltage that is higher than the first reference voltage. The capacitor includes a Schmitt circuit and a control means for controlling on/off of the charging means according to an output state of the Schmitt circuit, and the potential of the capacitor is repeatedly charged and discharged between the first and second reference voltages. In a clock generation circuit designed to
The on-state changes the potential of the capacitor to the second
a first switch means for making the potential of the capacitor higher than the first reference voltage when in an on state, and a third switch means for receiving a third reference voltage at one input; a comparator circuit that outputs a pulse corresponding to a period in which the input voltage supplied to the other input exceeds the third reference voltage; and a comparator circuit that outputs a pulse corresponding to a period in which the input voltage supplied to the other input exceeds the third reference voltage; further comprising means for supplying a differential signal exceeding the third reference voltage as the input signal to the other input of the comparator circuit, and obtaining the pulse from the comparator circuit as an initial state setting signal of the system. A clock generation circuit featuring: