JP2623890B2 - Sawtooth wave generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sawtooth wave generating circuit having a pulse input terminal and generating a sawtooth wave by charging and discharging a capacitor.

2. Description of the Related Art A conventional sawtooth wave generating circuit has a configuration as shown in FIG. In FIG. 3, 1 is a power supply terminal, 2 is a pulse input terminal, 3, 5, 36 are resistors, 4, 35 are NPN transistors, 26 is a constant current source, 32 is a capacitor, and 33 is a sawtooth wave output terminal. . 4 (a) to 4 (c) show waveforms at respective points in FIG.

Hereinafter, the operation of the circuit of FIG. 3 will be described with reference to these drawings. Now the pulse waveform V ₁ as shown in FIG. 4 (a) to the pulse input terminal 2 is input, the pulse waveform V ₁
Is applied to the base of transistor 4 through resistor 3. During the pulse duration T _1, the transistor 4 is a cutoff state, the transistor 35 becomes conductive. When the resistances of the resistors 5 and 36 are set to appropriate values, the transistor 35 becomes saturated. At this time, the current value I _R36 flowing through the resistor 36 is obtained by setting the voltage of the sawtooth output terminal 33 to V ₃₃ and the saturation voltage V of the transistor 35.
_35Sat, the resistance value of the resistor 36 when the R _36, Indicated by

At this time an amount corresponding discharge s stream of the difference between the current I ₂₆ and the current I _R36 through the resistor 36 by the constant current source 26 flows through the capacitor 32. Assuming that the discharge current at this time is I _C3 , I _C3 = I _R36 −I ₂₆ (2)

Meanwhile pulse duration T ₁ remaining period, i.e. the period T ₀ of the pulse
During the period (period T ₀ −T ₁ ) excluding the pulse period T ₁ , the transistor 4 is turned on, the transistor 35 is turned off, and the capacitor 32 receives the current I by the constant current source 26.
₂₆ flows as the charging flow. Therefore, the voltage waveform of the sawtooth wave output terminal 33 is as shown in V ₆ shown in Figure 4 (c).

Considering Figure 4 voltage V ₀₆ of V ₆ at the fall of the input pulse V ₁ shown in (a) Here, since the same amount of charge by the charge and discharge of the capacitor 32 I ₂₆ is a constant current, and considering equation (2), Becomes

Where I _R36 is And Equation (1), the result is that V ₀₆ is Becomes

Next considering the case where the pulse waveform V ₂ as shown in FIG. 4 (b) to the pulse input terminal 2 is input, pulse input V ₁ as shown in FIG. 4 described previously (a) is input Similarly considered and if, to discharge the capacitor 32 in the period T _2, the period
Since the capacitor 32 is charged between T _{0 and} T ₂ , the voltage becomes V ₇ shown in FIG. 4C. In V _7, given the initial voltage V _07, equation (2) Becomes

When T ₂ > T ₁ , V ₀₇ <V ₀₆ from the equations (6) and (7).

Problems to be Solved by the Invention In such a conventional configuration, signal waveforms having constant periods and different pulse widths, such as the waveforms of V ₁ and V ₂ shown in FIGS. Pulse input terminal 2 shown in FIG.
, The voltage waveform of the sawtooth wave output terminal 33 becomes the waveform of V ₆ and V ₇ shown in FIG.
The disadvantage is that the falling period of the sawtooth wave and the DC voltage are not kept constant.

The present invention solves such a problem, and provides a saw-tooth wave generating circuit capable of outputting a saw-tooth wave having a constant falling time and a constant DC voltage.

Means for Solving the Problems A saw-tooth wave generating circuit according to the present invention solves the above-mentioned problem, compares a pulse input with a voltage of a reference voltage source (34), and responds to a start edge of the pulse input. A first comparator (37) for outputting a first constant current, a first current mirror circuit (40) for mirror-inverting the first constant current and outputting a second constant current, A second current mirror circuit (41) for mirror-inverting the second constant current to output a third constant current, and a fourth constant current from a constant current source (26) for constantly outputting a constant current. A means for charging and discharging the capacitor (32) with a current having a difference from the third constant current is compared with a terminal voltage of the capacitor and a first reference voltage (Vref1). When the voltage becomes equal to or lower than the reference voltage, the operation of the first comparator is stopped and the second current Second comparator for interrupting the output current of the error circuit (3
9) and a second reference voltage (V
ref2) is compared with the terminal voltage of the capacitor. When the terminal voltage of the capacitor becomes equal to or lower than the second reference voltage, a third comparison for inhibiting pulse input to the first comparator is performed. (38).

Operation With this configuration, the terminal voltage of the capacitor becomes the second voltage.
Is higher than the reference voltage, the inhibition of the pulse input to the first comparator is released by the third comparator, and when the pulse input is input to the first comparator, the first comparator Outputs a first constant current and discharges the capacitor with the third current transmitted. When the terminal voltage of the capacitor becomes equal to or lower than the second reference voltage, the operation of the third comparator causes the first comparator to operate.
Of the pulse input to the comparator of FIG. Further, when the terminal voltage of the capacitor decreases to reach the first reference voltage, the second comparator operates, interrupts the operation of the first comparator, and outputs the output voltage of the first comparator (the first comparator). The third constant current obtained by transmitting the first constant current is stopped. And the fourth, which is constantly supplied at a constant
Charge the capacitor with the constant current of the capacitor, and the terminal voltage of the capacitor rises. Then, at the next pulse input, the first comparator outputs the first constant current again, and repeats the same operation. Thereby, the present invention can keep the falling period of the sawtooth wave and the DC voltage constant at all times.

Embodiment FIGS. 1 and 2 are a circuit diagram of a sawtooth wave generating circuit according to an embodiment of the present invention and a voltage waveform diagram of a main part thereof. In FIG. 1, parts having the same functions as in FIG. 3 are given the same reference numerals as in FIG. 3, and description thereof is omitted. In FIG. 1, 7, 8, 9, 10, 11, 28, 30, 31 are NPN transistors, 13, 14, 1
5, 19, 20, 23, 24 are PNP transistors, 12, 21, 25, 26 are constant current sources, 37, 38, 39 are comparators, 40, 41 are current mirror circuits, 34 is a reference power supply, 16, 17 , 18,22,27,29 are resistors.
FIGS. 2A to 2E show waveforms at respective points in FIG.

The operation of the circuit shown in FIG. 1 will be described below with reference to these drawings. In Figure 1, when the pulse waveform V ₁ as shown in Figure 2 of the pulse input terminal 2 (a) is input,
The pulse waveform V ₁ is applied to the base of the transistor 4 through the resistor 3. As a result, during the pulse period T _1, the transistor 4 becomes off. At this time, the voltage of the sawtooth wave output pins shown in FIG. 2 (c) and V _03. Where V
₀₃ is assumed to be V ₀₃ > V _{ref 2} when V _{ref 2} is the base voltage of the transistor 19 constituting the comparator 38 (this base voltage is determined by the resistors 16, 17, and 18). At this time, the comparator 38
Since the transistor 20 is turned off, the transistor 8 is also in an unauthorized state, thereby prohibiting the inhibition of the pulse input to the base of the transistor 7. Therefore, the pulse input is transmitted to the base of the transistor 7,
The transistor 7 becomes saturated.

The comparator 37 has a predetermined reference voltage applied to the base of the transistor 11.
When the base potential of the transistor 10 decreases, the transistor 11 becomes conductive, and outputs a current (first constant current) corresponding to the current I ₀ of the constant current source 12 from the collector. This current I ₀ is input to the current mirror circuit 40 and output from the respective collectors of the transistors 14 and 15. These currents are referred to as I ₁ and I ₂ , respectively. The collector current I ₁ of transistor 14 flows to the base of the resistor 29 and the transistor 9, transistor 9 is saturated. On the other hand, the collector current I ₂ of transistor 15 is input to the current mirror circuit 41, is mirrored by transistors 31 and 30, is output as the collector current of the transistor 30. Wherein the voltage of the sawtooth wave output terminal 33, as indicated by V ₃ of FIG. 2 (c), and the current discharging the capacitor 32 and I _c1, the gradient is lowered by I _c1 / C . Here, the current of the interruption current source 26 is I ₂₆
Then, I _c1 = I ₂ −I ₂₆ > ₀ , and since I ₂ and I ₂₆ are both constant currents, I _c1 is also a constant current.

Next, when the pulse period T ₁ shown in FIG. 2 (a) is completed, but the transistor 7 because the transistor 4 is saturated becomes the cut-off state, the transistor 9 is saturated, the current I ₀ through the transistor 11 Keep flowing. If the base voltage of the transistor 23 of the comparator 39 is V _{ref 1} and the voltage of the sawtooth output terminal 33 is going to fall below V _{ref 1} as shown by V ₃ in FIG. 24 switches from the cutoff state to the active state, the current of the constant current source 25 flows through the transistor 24 to the resistor 27 and the base of the transistor 28, and the transistor 28 saturates. Shows the voltage at the collector of the transistor 28 V ₄ of FIG. 2 (d). When the transistor 28 is saturated, the transistor 9 is turned off, so that the base of the transistor 10 of the comparator 37 is connected to the power supply terminal 1 by the resistor 6, so that no current flows through the transistor 11 and the transistor of the current mirror circuit 41 No current flows through 30. At this time, the discharge of the capacitor 32 is stopped, and the charging of the constant current source by 26 is started. At this time, sawtooth wave output terminal
The voltage at 33 rises with a slope of I ₂₆ / C. The rising voltage of the sawtooth wave is V _{ref 1} , and the falling voltage V ₀₃ is (here It is. ).

Next, when the pulse waveform V ₂ as shown by the 2 (b) to the pulse input terminal 2 is considered when the inputted, discharges from falling point of the pulse capacitor 32 at I _c1 = I ₁ -I ₂₆ It is given, and therefore description same as when the pulse V ₁ is inputted of FIG. 2 (a) is omitted. Lowers the voltage of the sawtooth wave output terminal 33, drops below the base voltage V _re f ₂ of the transistor 19 of comparator 38, transistor 20 is switched from the disconnected state to the active state, the current of the constant current source 21 is the resistance through the transistor 20 Then, the base potential of the transistor 8 is increased, the transistor 8 is saturated, and the transistor 7 is turned off. This inhibits the pulse input from the input terminal 2 from being transmitted to the base of the transistor 10 of the comparator 37. Therefore, even if a pulse input having a large pulse width is input, the operation is performed without being affected by the magnitude of the pulse width. FIG. 2E shows a voltage waveform at the base of the transistor 8. In this state, the sawtooth wave output terminal 33
Is higher than Vref ₁ , the transistor 9 is in a saturated state, and the collector current (third current) of the transistor 30 that has transmitted the output current of the transistor 11 of the comparator 73 is used as the capacitor. 32 are being discharged. When the voltage of the saw-tooth wave output terminal 33 is about to fall below Vref ₁ , the operation of the comparator 39 switches the transistor 9 from the saturated state to the cut-off state.
The base potential of 10 rises and switches from discharging the capacitor to charging. In other words, even if the pulse period of the pulse input is shorter or longer than the predetermined falling period of the sawtooth wave, a constant falling period and a sawtooth wave of DC voltage are output even if the pulse period is long.

As described above, according to the present invention, by using two or more comparators, a sawtooth wave having a constant falling voltage and a constant DC voltage can be generated regardless of the pulse input period. The effect that it can occur is obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a sawtooth wave generating circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing voltages at respective points in the circuit of FIG. 1, and FIG. 3 is a conventional sawtooth wave generating circuit. FIG. 4 is a waveform diagram showing voltages at respective points in the circuit of FIG. 1 ... Power supply terminal, 2 ... Pulse input terminal, 3,5,6,16,17,
18,20,27,29,36 …… resistance, 4,7,8,9,10,11,28,30,31,35
…… NPN transistor, 12,21,25,26 …… Constant current source, 13,1
4,15,19,20,23,24 …… PNP transistor, 32 …… Capacitor, 33… Sawtooth wave output terminal, 34 …… Reference power supply, 37,3
8,39 ... Comparator, 40,41 ... Current mirror circuit.

Claims (1)

(57) [Claims] The pulse input is compared with a voltage of a reference voltage source,
A first comparator that outputs a first constant current in response to a start edge of the pulse input; a first current mirror circuit that mirror-inverts the first constant current and outputs a second constant current A second current mirror circuit that mirror-inverts the second constant current and outputs a third constant current; a fourth constant current from a constant current source that constantly outputs a constant current; Means for charging and discharging the capacitor with a current having a difference from the constant current, and comparing the terminal voltage of the capacitor with a first reference voltage, and when the terminal voltage of the capacitor becomes equal to or lower than the first reference voltage, A second comparator for stopping the operation of the first comparator and cutting off an output current of the second current mirror circuit, a second reference voltage higher than the first reference voltage, and a terminal voltage of the capacitor And the terminal voltage of the capacitor is When it is 2 less than the reference voltage, a third sawtooth generating circuit; and a comparator for inhibiting the pulse input inputted to the first comparator.