JP3281811B2 - Pulse expansion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse expansion circuit for expanding a pulse width of an input signal, and more particularly to a pulse expansion circuit suitable for accurately producing a plurality of expanded pulses with a small number of elements. About.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional pulse expansion circuit. The input signal of FIG. 3A is applied to the input terminal (1) of FIG. The pulse of FIG. 3B is generated at the collector of the transistor (2) in response to the input signal of FIG. When the pulse in FIG. 3B becomes the “L” level, the transistor (3) turns off and the transistor Q1 turns on. When the transistor Q1 is turned on, the time constant circuit (4) including the resistor R and the capacitor C becomes the transistor Q1.
Discharge immediately via. Due to this discharge, the collector voltage of the transistor Q1 changes from the power supply voltage (+ Vcc) to the saturation voltage (Vsat) of the transistor Q1 as shown in FIG.
It drops rapidly.

On the other hand, since the reference voltage VR of the reference power supply (6) of the comparator (5) is set to the level shown by the dotted line in FIG. 3 (d), the output signal of the comparator (5) is shown in FIG. As shown in FIG. When the output signal of the comparator (5) goes to the “H” level, the transistor Q2 turns on, and the voltage in FIG. 3C goes to the “L” level. Since this operation is performed instantaneously, FIG.
The voltage shown in FIG.

When the voltage shown in FIG. 3C becomes "L" level, the transistor Q1 is turned off, and a charging current flows from the resistor R to the capacitor C. Then, the collector voltage of the transistor Q1 increases as shown in FIG. 3D, and becomes higher than the reference voltage VR of the reference power supply (6) of the comparator (5). Then, the output signal of the comparator (5) is
As shown in FIG. 3 (e), the level becomes “L” level, and the transistor Q2 is turned off.

As a result, the output terminal (7) is connected to FIG.
A signal in which the pulse of FIG. To adjust the pulse width in FIG. 3E, the time constant may be changed by adjusting the values of the resistor R and the capacitor C in the time constant circuit (4).

[0006]

However, the apparatus shown in FIG. 2 has a problem that a plurality of expanded pulses cannot be created. In order to generate a plurality of expanded pulses in the apparatus shown in FIG. 2, it is conceivable to prepare a plurality of apparatuses shown in FIG. However, in such a case, when the number of elements increases and the pulse width of the expanding pulse is close, the pulse width may be reversed. That is, if the value of the reference voltage VR of the reference power supply (6) in FIG. 2 or the value of the resistor R and the capacitor C of the time constant circuit (4) fluctuates, the pulse width easily fluctuates.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a first flip-flop that inverts according to an input signal, and a time constant circuit according to an output signal of the first flip-flop. Control means for charging or discharging
A reference voltage generation circuit for generating a reference voltage, and comparing the output voltage of the time constant circuit with the first reference voltage from the reference voltage generation circuit, and inverting the first flip-flop according to the comparison result. A comparator, a counter for generating a delayed pulse that counts a clock signal by using an output signal of the first flip-flop as a trigger, and generates a pulse delayed to a timing close to one cycle of the input signal; And a third flip-flop that inverts in response to the pulse and the output signal of the first flip-flop, wherein an output signal is obtained from an output terminal of the third flip-flop.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a pulse expansion circuit according to the present invention. (8) is an input terminal to which an input signal is applied, and (9) and (10) are on / off according to the input signal. (11) is a first flip-flop set according to an input signal, and (12) is a control for charging or discharging the time constant circuit (4) according to an output signal of the first flip-flop (11). A transistor operating as a means; (13) a second flip-flop that inverts according to an output signal of the first flip-flop (11) and a collector signal of the transistor (9); (14)
Is a transistor that operates as a prohibiting means for prohibiting an input signal from being applied to the first flip-flop (11) in response to an output signal of the second flip-flop (13). The reference voltage generating circuit (16) compares the output voltage of the time constant circuit (4) with the first reference voltage from the reference voltage generating circuit (15), and determines the first voltage according to the comparison result. A first comparator for inverting the flip-flop (11); (17) a second comparator for comparing an output voltage of the time constant circuit (4) with a second reference voltage from the reference voltage generation circuit (15); 18) a clock signal source for generating a clock signal, and 19) counting the clock signal by using the output signal of the first flip-flop as a trigger (reset release) and performing the input signal A counter for generating a delayed pulse which generates a pulse delayed to a timing close to one cycle, (20) is reset by the pulse from the counter (19), and an output signal of the first flip-flop (11) is clocked. D-FF type third applied as
A flip-flop (21) is a fourth flip-flop that inverts according to the output signal of the counter (19) and the output signal of the second comparator (17).

In FIG. 1, the same circuit blocks as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. The input signal of FIG. 4A is applied to the input terminal (8) of FIG. The transistor (9) is turned on and the transistor (10) is turned off in response to the input signal of FIG.
When the collector potential of the transistor (10) becomes "H", the first flip-flop (11) is set and its Q
The output becomes "H" as shown in FIG.

Since the Q inverted output of the first flip-flop (11) becomes "L", the transistor (12) is turned off, and the time constant circuit (4) is charged. On the other hand, when the first flip-flop (11) is set, its Q output sets the second flip-flop (13), and its Q output turns on the transistor (14).

The transistor (14) is a transistor which operates as a prohibiting means for prohibiting an input signal from being applied to the first flip-flop (11). When the transistor (14) is turned on, the first flip-flop (1)
Since the set input of 1) is at the "L" level, the reset input R is ready to be accepted. That is, the first flip-flop (11) immediately resets the "H" to "L" when the set input S becomes "H", so that the first flip-flop (11) can be reset immediately, and the width of the first output from the Q output is reduced. Can output short pulses.

A time constant circuit (4) comprising a resistor R and a capacitor C is charged as shown in FIG. By this charging, the collector voltage of the transistor (12) increases from the saturation voltage (Vsat) to the power supply voltage (+ VCC). On the other hand, the reference voltage V1 of the first comparator (16)
Is set to the level indicated by the dotted line in FIG.
The reference voltage V2 of the comparator (17) is set to the level indicated by the dotted line in FIG.

At time t1, the output signal of the second comparator (17) becomes "H" level as shown in FIG. When the output signal of the second comparator (17) becomes "H" level, the fourth flip-flop (21) is reset, and its Q output falls as shown in FIG. 4 (g). FIG. 4 (e)
The pulse width of the pulse is slightly longer than that of the pulse of FIG.

When the time t1 has passed and the time t2 has been reached,
This time, the output signal of the first comparator (16) becomes "H" level, and the first flip-flop (11) is reset. When the first flip-flop (11) is reset and its Q inverted output becomes "H", the transistor (12) is turned on and the time constant circuit (4) discharges rapidly as shown in FIG. 4 (b). When the time constant circuit (4) discharges, the output signal of the first comparator (16) returns to "L".

When the Q output of the first flip-flop (11) falls at time t2 as shown in FIG. 4 (c), the reset of the counter (19) is released and the clock signal source (1) is released.
8) count the clock signal. 4C at time t2 is applied as a clock signal to the third flip-flop (20) and its Q inverted output is
Fall as shown in (e).

When the counter (19) counts until time t3, it generates a pulse P1 shown in FIG. 4 (d).
The pulse F1 resets the third flip-flop (20) and sets the fourth flip-flop (21). As a result, the signal of FIG.
4 (g) is generated at the terminal (23).

The pulse width of the signal shown in FIG. 4E is extended before and after the signal shown in FIG. 4A. Also, the signal of FIG. 4 (g) has a pulse width that extends before and after the signal of FIG. The setting of the earlier time can be arbitrarily set by setting the reference voltages of the first and second comparators (16) and (17).

At time t1, the signal in FIG. 4A is still at the "L" level. However, even when this is at the “H” level, the circuit of FIG. 1 can operate similarly. This is attributable to the operation of the second flip-flop (13).
Thus, the circuit of FIG. 1 operates according to the rising pulse of FIG. 4A, and has nothing to do with the falling. For this reason, the falling edges of FIGS.
It is possible to make the timing earlier or later than the fall timing of (a).

The reference voltages of the first and second comparators (16) and (17) are both reference voltage generation circuits (1).
5), and the reference voltage generation circuit (15) is divided by resistors. Therefore, the relative values of the reference voltages V1 and V2 do not change even if the absolute values change. Therefore, the pulse widths shown in FIGS. 4E and 4G are not interchanged due to the reference voltages V1 and V2. Also, since only one time constant circuit (4) is used, there is no problem of time constant error or increase in the number of elements.

[0020]

As described above, according to the present invention, the reference voltages of the first and second comparators are both generated from one reference voltage generation circuit, and the reference voltage generation circuit generates the voltage by resistance division. Creating. Therefore, the relative values of the two reference voltages do not change even if the absolute values change. Therefore, the pulse widths of the two pulses do not interchange. Further, since only one time constant circuit is used, there is no problem of an error in the time constant or an increase in the number of elements.

Further, according to the present invention, a counter for generating a delayed pulse which counts a clock signal by using an output signal of a first flip-flop as a trigger and generates a pulse delayed to a timing close to one cycle of an input signal is provided. Since it is used, a pulse whose pulse width before and after the input signal is widened can be created.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a pulse stretching circuit of the present invention.

FIG. 2 is a block diagram showing a conventional pulse expansion circuit.

FIG. 3 is a waveform diagram for explaining FIG. 2;

FIG. 4 is a waveform chart for explaining FIG. 1;

[Explanation of symbols]

 (11) First flip-flop (12) Transistor (16) First comparator (13) Second flip-flop (17) Second comparator (19) Counter (20) Third flip-flop (21) Fourth flip-flop

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 5/04

Claims (4)

(57) [Claims] 1. A first flip-flop that inverts according to an input signal, control means that charges or discharges a time constant circuit according to an output signal of the first flip-flop, and a reference voltage generation circuit that generates a reference voltage A first comparator for comparing an output voltage of the time constant circuit with a first reference voltage from the reference voltage generation circuit, and inverting the first flip-flop according to a result of the comparison; A counter for generating a delayed pulse which counts a clock signal by using the output signal of the above as a trigger and generates a pulse delayed to a timing close to one cycle of the input signal; the pulse from the counter and the first flip-flop And a third flip-flop that inverts in response to the output signal of the third flip-flop. Pulse stretcher circuit, characterized in that it has obtained manner. 2. A first flip-flop that inverts according to an input signal, control means that charges or discharges a time constant circuit according to an output signal of the first flip-flop, and a reference voltage generation circuit that generates a reference voltage A first comparator for comparing an output voltage of the time constant circuit with a first reference voltage from the reference voltage generation circuit, and inverting the first flip-flop according to a result of the comparison; A second flip-flop that inverts according to the output signal of the second flip-flop and the input signal; prohibiting means that prohibits the input signal from being applied to the first flip-flop according to the output signal of the second flip-flop; The clock signal is counted by using the output signal of the first flip-flop as a trigger, and the clock signal is delayed to a timing close to one cycle of the input signal. A counter for generating a delayed pulse, and a third flip-flop that inverts the pulse from the counter and an output signal of the first flip-flop. A pulse expansion circuit characterized in that an output signal is obtained. 3. A first flip-flop that inverts according to an input signal, control means that charges or discharges a time constant circuit according to an output signal of the first flip-flop, and a reference voltage generation circuit that generates a reference voltage A second comparator that compares an output voltage of the time constant circuit with a second reference voltage from the reference voltage generation circuit; counts a clock signal using an output signal of the first flip-flop as a trigger, and executes the input signal. And a fourth flip-flop that inverts according to an output signal of the counter and an output signal of the second comparator. A pulse expansion circuit wherein an output signal is obtained from an output terminal of a fourth flip-flop. 4. A first flip-flop that inverts according to an input signal, control means that charges or discharges a time constant circuit according to an output signal of the first flip-flop, and a reference voltage generation circuit that generates a reference voltage A first comparator for comparing an output voltage of the time constant circuit with a first reference voltage from the reference voltage generation circuit, and inverting the first flip-flop according to a result of the comparison; A second comparator that compares an output voltage with a second reference voltage from the reference voltage generation circuit; counts a clock signal by using an output signal of the first flip-flop as a trigger; and at a timing close to one cycle of the input signal. A counter for generating a delayed pulse that generates a pulse delayed until the output of the pulse and the first flip-flop from the counter. A third flip-flop that inverts according to a force signal; and a fourth flip-flop that inverts according to an output signal of the counter and an output signal of the second comparator.
An output signal is obtained from the output terminals of the third and fourth flip-flops.