JPH0212752Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a pulse generation circuit used in a sampling circuit or the like.

Conventionally, there has been a pulse generation circuit that uses a step recovery diode (hereinafter referred to as SRD) to generate short-time pulses (Japanese Patent Laid-Open No. 57
-Refer to No. 118428). In the pulse generating circuit, when the pulse width of the rectangular wave input signal fluctuates, the voltage value of the output pulse fluctuates and the frequency characteristics also deteriorate. Therefore, to prevent this, SRD
is used in the saturation region, and has the disadvantage of extremely high power consumption.

The present invention was developed in view of the above drawbacks, and by shaping the rectangular wave input signal into a predetermined waveform,
Eliminates the influence of pulse width fluctuations of square wave input signals,
The purpose of the present invention is to provide a pulse generation circuit with low power consumption and wide band.

The pulse generation circuit of the present invention includes a waveform shaping circuit that receives a rectangular wave input signal and outputs a rectangular wave output signal with a predetermined pulse width, and a pulse generator that has an SRD and generates a pulse in response to the rectangular wave output signal. It is composed of.

The present invention will be described in detail below using examples.

FIG. 1 is a block diagram showing an embodiment of the pulse generating circuit of the present invention.

In FIG. 1, a waveform shaping circuit 1 is connected to a pulse generator 2. In FIG. Pulse generator 2 is made by JP-A-Sho.
This circuit is similar to the pulse generating circuit disclosed in No. 57-118428, and is composed of a constant voltage source 3, a constant current source 4, a differentiating circuit 5, and an SRD 6. The operation of the pulse generating circuit shown in FIG. 1 constructed in this manner will be described below.

The waveform shaping circuit 1 shapes the waveform of a rectangular wave input signal _Vi , converts its pulse width into a predetermined width, and then outputs a rectangular wave output signal _V1 . The rectangular wave output signal V ₁ is introduced into a constant voltage source 3 and a constant current source 4 . Constant voltage source 3
and constant current source 4 operate complementarily. For example, when the rectangular wave output signal _V1 is at a high level, the constant current source 4 operates, and the constant voltage source 3 stops operating. In this case, charging current i _C flows in the SRD 6 in the forward direction. Since the pulse width of the square wave output signal V ₁ is constant, SRD
The accumulated charge of 6 becomes constant at a value corresponding to the pulse width of the rectangular wave output signal _V1 .

When the rectangular wave output signal _V1 is at a low level, the constant current source 4 stops operating, and the constant voltage source 3 operates. At this time, the accumulated charge in the SRD 6 is discharged by the discharge current _iD . The voltage across the SRD 6 is differentiated by a differentiating circuit 5 to obtain an output pulse V ₀ .

FIG. 2 is a detailed circuit diagram of the waveform shaping circuit 1 of FIG. 1. The same parts as in FIG. 1 are given the same reference numerals.

In FIG. 2, the Q output terminal of the D-flip-flop 7 is connected to a capacitor 9, a variable resistor 10, and an input of an inverting circuit 8. The output of the inverting circuit 8 is connected to the set terminal S of the D-flip-flop 7. One end of the capacitor 9 is connected to a positive power supply (+Vcc), and the other end is connected to a variable resistor 10. Capacitor 9 and variable resistor 10 constitute a time constant circuit. or,
The terminal D of the D-flip-flop is grounded, and the clock terminal C receives a square wave input signal _Vi .

FIG. 3 is an explanatory diagram of the operation of the waveform shaping circuit of FIG. 2. The operation will be explained below with reference to FIGS. 2 and 3.

Assume that the rectangular wave input signal V _i is at a low level in the initial state (time t ₀ ).

In this state, the output voltage of terminal Q is at a high level.
The output voltage of the terminal, ie the square wave output signal _V1 , is at a low level. The node potential V ₂ of the node 11 remains at a potential determined by the output voltage of the Q terminal and the positive power supply (+Vcc). Further, the output voltage V ₃ of the inverting circuit 8 is at a low level. At time t ₁ ,
When the rectangular wave input signal V _i becomes high level, the output of the Q terminal becomes low level and the output of the terminal, that is, the rectangular wave output signal V ₁ becomes high level. At the same time, node 11
The node potential V ₂ is the capacitor 9 and the variable resistor 1.
It decreases with a slope determined by the time constant with respect to 0. When the node potential V ₂ crosses the threshold voltage V _th of the inversion circuit 8 at time t ₂ , the output voltage V ₃ of the inversion circuit 8 becomes high level and the D-flip-flop 7 is set. As a result, the output voltage of the terminal Q becomes a high level, and the output voltage of the terminal, that is, the rectangular wave output signal _V1 becomes a low level. Therefore, the square wave output signal V ₁ is the time constant and threshold voltage of the capacitor 9 and the variable resistor 10.
This is a signal with a constant pulse width determined by the relationship between the voltage values of V _th . Next, the node potential V ₂ rises and when it crosses the threshold voltage V _th again, the output voltage V ₃ becomes low level. At time _t3 , the rectangular wave input signal V _i becomes low level. Square wave output signal
V ₁ is fed to the pulse generator 2 of FIG. 1, resulting in a narrow output pulse V ₀ . As described above, the pulse generation circuit of the present invention is equipped with a waveform shaping circuit that shapes the rectangular wave input signal and outputs a rectangular wave output signal with a constant pulse width, so that the pulse width of the rectangular wave input signal varies. The pulse generator can be driven by a signal with a constant pulse width regardless of the SRD.
There is no need to drive the device to saturation, and power consumption is extremely low. In particular, the pulse generation circuit of the present invention is very effective when the rectangular wave input signal ranges from a relatively low frequency to a wide range. Further, by changing the time constant or threshold voltage value of the time constant circuit, the pulse width of the rectangular wave output signal can be freely set.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the pulse generation circuit of the present invention. FIG. 2 is a detailed circuit diagram of a waveform shaping circuit used in the pulse generation circuit of FIG. 1. FIG. 3 is an explanatory diagram of the operation of the waveform shaping circuit of FIG. 2. 1: Waveform shaping circuit, 2: Pulse generator, 6:
SRD, 7: D-flip-flop, 8: Inverting circuit.

Claims (1)

[Claims for Utility Model Registration] A constant current source and a constant voltage source that operate complementary to each other and a constant voltage source, a step recovery diode connected to the constant current source and the constant voltage source, and differentiating the output signal of the step recovery diode. A pulse generating circuit comprising a differentiating circuit comprising: a waveform shaping means for adjusting the pulse width of the input signal to the constant current source and the constant voltage source so as not to saturate the step recovery diode. .