JPH0335854B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a monostable multivibrator widely used in electronic equipment and the like.

(Prior Art) Fig. 4 is a circuit diagram showing a specific configuration example of a conventionally used monostable multivibrator, and Fig. 5 is for explaining the operation of the monostable multivibrator shown in Fig. 4. FIG. In the monostable multivibrator shown in FIG. 4, 1 is a signal input terminal to which an input trigger pulse a (a in FIG. 5) is supplied, and 2 is an output signal h of the monostable multivibrator (a in FIG. 5). 3 is a reset flip-flop, 4 is a time constant circuit composed of a resistor R1 and a capacitor C1, 5 is a comparator, 9 is an inverter, and Q1 is a time constant circuit. Capacitor C in 4
The transistor Vref that discharges the accumulated charge of 1 is a reference voltage source applied to the inverting input terminal of the comparator 5, and the signal input terminal 1 is connected to the set terminal S of the set reset flip-flop 3. Further, the Q-bar terminal of the above-mentioned set-reset flip-flop 3 is connected to the input side of the inverter 9 and the base of the transistor Q1.

The emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected to the non-ground terminal of the capacitor C1 of the time constant circuit 4 and the non-inverting input terminal of the comparator 5. The output of the comparator 5 described above is connected to the reset terminal of the reset flip-flop 3 described above. The output terminal 2 is connected to the output side of the inverter 9 described above.

The operation of the monostable multivibrator shown in FIG. 4 constructed as described above is as follows.
When an input trigger pulse a is supplied to the signal input terminal 1 at time t1 shown in a in FIG. , the output signal g at the Q-bar terminal changes from a high level state to a low level state at time t1, as shown in g in FIG.

As a result, the transistor Q1 to which the output signal g of the Q-bar terminal of the set-reset flip-flop 3 is applied changes from the conductive state to the non-conductive state at time t1, so that the time constant circuit The capacitor C1 of No. 4 starts charging through the resistor R1 from time t1, and the terminal voltage Vc of the capacitor C1 gradually rises from time t1 according to the time constant of the time constant circuit 4.

Further, the output signal h of the inverter 9 to which the output signal g of the Q-bar terminal of the set-reset flip-flop 3 is applied changes from the low level state to the high level state at time t1. . As mentioned above, the capacitor C1 of the time constant circuit 4 gradually increases after time t1.
The terminal voltage Vc (Vc in Fig. 5) is the reference voltage applied to the inverting input terminal of the comparator 5 at time t2.
When Vref is reached, the comparator 5 outputs a high-level output signal i (i in FIG. 5) at time t2, which is applied to the reset terminal R of the reset flip-flop 3. , the reset flip-flop 3 is reset at time t2.

Therefore, the output signal g of the Q-bar terminal of the reset flip-flop 3 changes from a low level state to a high level state at time t2, as shown in g in FIG. The transistor Q1 to which the output signal g from the Q-bar terminal of the set-reset flip-flop 3 is applied changes from the non-conductive state to the conductive state at time t2, so that the capacitor of the time constant circuit 4 The non-grounded terminal side of C1 is connected to ground between the collector and emitter of transistor Q1 at time t2, and the terminal voltage Vc of capacitor C1 is brought to approximately the ground potential from time t2.

Further, the output signal h of the inverter 9 to which the output signal g of the Q-bar terminal of the set-reset flip-flop 3 is applied changes from the high level state to the low level state at time t2. . The above operation is performed in the same way when the input trigger pulse a is supplied to the signal input terminal 1 at time t3, so the monostable multivibrator shown in FIG. On the other hand, by performing the above-described operation every time the input trigger pulse a is supplied, an output signal h having a predetermined pulse width is sent to the output terminal 2.

(Problems to be Solved by the Invention) By the way, the pulse width of the output signal of the conventional monostable multivibrator having the configuration shown in FIG.
From the time when the input trigger pulse a is supplied to the signal input terminal 1 and the transistor Q1 changes from a conductive state to a non-conductive state, the terminal voltage Vc of the capacitor C1 in the time constant circuit 4 becomes the reference voltage of the comparator 5.
It corresponds to the period up to the point when Vref is reached. However, when the transistor Q1 is conducting, the capacitor C of the time constant circuit 4
1 terminal voltage Vc is not the ground potential, but the saturation voltage that appears between the collector and emitter of transistor Q1, which is in a conductive state, and is also the point at which transistor Q1 actually changes from a conductive state to a non-conductive state. is delayed by the accumulation time of the minority carriers of the transistor, but since the saturation voltage and the accumulation time of the minority carriers change as the temperature changes, the monostable multivibrator with the conventional configuration shown in Figure 4 The pulse width of the output signal will change with changes in temperature.
Therefore, it has been desired to realize a monostable multivibrator that can generate an output signal whose pulse width does not change even when the temperature changes.

(Means for Solving the Problems) The present invention includes a time constant circuit and an inverting input terminal which is supplied with the output voltage of the time constant circuit described above, and a non-inverting input terminal which is supplied with a reference voltage V1. The output voltage of the time constant circuit described above is applied to the first comparator and the non-inverting input terminal, and the inverting input terminal has V2<V1.
A second comparator is provided with a reference voltage V2 having a relationship of a set-reset flip-flop, means for resetting a time constant circuit based on the output signal of the first set-reset flip-flop; A second set-reset flip-flop is reset by the output of a logic circuit to which the output of the comparator is applied, and an output signal is obtained from the output terminal of the second set-reset flip-flop. The present invention provides a monostable multivibrator comprising means.

(Example) Hereinafter, specific contents of the monostable multivibrator of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block circuit diagram of an embodiment of the monostable multivibrator of the present invention. In the monostable multivibrator shown in FIG. )
2 is the output terminal of the monostable multivibrator output signal f (FIG. 2 f), 3 is the first set-reset flip-flop, and 4 is the second set-reset flip-flop. 5 is a first comparator, 6 is a second comparator, 7 is a time constant circuit constituted by a resistor R1 and a capacitor C1, and Q1 is a capacitor C1 in the time constant circuit 7. V1 and V2 are reference voltage sources, G1 is a NOR gate, and G2 is an AND gate.

The input trigger pulse a supplied to the signal input terminal 1 is supplied to the set terminals S of the first and second reset flip-flops 3 and 4, and is also supplied to the NOR gate G1 as one input thereof. Supplied. Further, the output signal b (b in FIG. 2) from the Q terminal of the first reset flip-flop 3 is supplied to the base of the transistor Q1 and also as one input of the NOR circuit G1. There is. Further, the Q terminal of the second reset flip-flop 4 mentioned above is connected to the output terminal 2 of the output signal.

The emitter of the transistor Q1 described above is grounded, and the collector of the transistor Q1 is connected to the connection point between the non-grounded terminal of the capacitor C1 of the time constant circuit 7 and the resistor R1, and the non-inverting terminal of the first comparator 5. It is connected to the input terminal and the non-inverting input terminal of the second comparator 6.

Further, the reference voltage V1 is supplied from the reference voltage source V1 to the non-inverting input terminal of the first comparator 5, and the first comparator 5 has the above-mentioned capacitor supplied to its inverting input terminal. C1 terminal voltage
A comparison output between Vc and the aforementioned reference voltage V1, ie, an output signal c as shown in FIG.

The reference voltage V2 is supplied from the reference voltage source V2 to the inverting input terminal of the second comparator 6, and the reference voltage V2 is supplied to the non-inverting input terminal of the second comparator 6. Terminal voltage Vc
and the reference voltage V2 mentioned above, that is, the output signal d as shown in d of FIG.
is supplied to AND gate G2 as one of its input signals.

The output signal of the NOR gate G1 described above is supplied as the other input of the AND gate G2, and the output signal e (e in FIG. 2) from the AND gate G2 is used to reset the second reset flip-flop 4. Supplied to terminal R.

The voltage value V of each of the reference voltage sources V1 and V2 described above
1 and V2 are set so as to satisfy the relationship V2>V1. Note that it is natural that the voltage Vcc of the power supply Vcc is higher than the reference voltage V2 described above.

The operation of the monostable multivibrator shown in FIG. 1 constructed as described above is as follows.
The first and second reset flip-flops 3 and 4 are reset before time t1 when the input trigger pulse a shown in a in FIG. 2 is supplied to the signal input terminal 1. Since the output signal b of the Q terminal of the first reset flip-flop 3 is at a low level as shown in FIG. 2b, the transistor Q1 is rendered non-conductive. Therefore, time constant circuit 7
The capacitor C1 in is connected from the power supply Vcc to the resistor R
1, and the terminal voltage Vc of the capacitor C1 is the voltage value Vcc of the power supply Vcc, as shown by Vc in FIG.

In addition, in this state, the inverting input terminal of the first comparator 5 is supplied with the terminal voltage Vc=Vcc of the capacitor C1, which has a relationship of Vcc>V1 with respect to the reference voltage V1 applied to the non-inverting input terminal. Therefore, the output signal c of the first comparator 5 is at a low level as shown in FIG. 2c, and therefore the first reset flip-flop 3 is in the reset state. is held.

In addition, in the state before time t1, the non-inverting input terminal of the second comparator 6 has a terminal voltage Vc of the capacitor C1 which has a relationship of Vcc>V2 with respect to the reference voltage V2 applied to the inverting input terminal. =Vcc
is supplied, the output signal d of the second comparator 6 is in a high level state as shown in d of FIG. 2, and the output signal d of the NOR gate G1 is in the state before time t1. Since both inputs are at low level, the output of NOR gate G1 is at high level, and AND gate G2
The output e of the flip-flop 4 is at a high level as shown in FIG. is at a low level as shown at f in FIG.

When the input trigger pulse a is supplied to the signal input terminal 1 at time t1, the first reset flip-flop 3 is set and its Q
The output signal b from the terminal becomes high level, changing the transistor Q1 from a non-conducting state to a conducting state, and changing the output of the NOR gate G1 from a high level state to a low level state.

As mentioned above, the low level signal appearing on the output side of the NOR gate G1 causes the AND gate G2 to
The output side of the reset flip-flop 4 changes from a high level state to a low level state, and the reset of the second set reset flip-flop 4 is released. Set by the trigger pulse a, the output signal f at its Q terminal changes from a low level state to a high level state at time t1, as shown at f in FIG.

By supplying the output signal b of the first reset flip-flop 3 which has changed from the low level state to the high level state at time t1 as described above, the reset state is changed from the low level state to the high level state at time t1 as described above. Transistor Q1 changed from non-conducting state to conducting state
quickly discharges the accumulated charge in the capacitor C1 of the time constant circuit 7, so that the terminal voltage of the capacitor C1 rapidly decreases as shown by Vc in FIG.

The terminal voltage Vc of the capacitor C1 supplied to the non-inverting input terminal of the second comparator 6 is the reference voltage V supplied to the inverting input terminal of the second comparator 6.
2, the output signal d of the second comparator 6 changes from a high level state to a low level state, as shown in d of FIG.

Next, the terminal voltage Vc of the capacitor C1 supplied to the inverting input terminal of the first comparator 5 is
At time t3 when the reference voltage V1 supplied to the inverting input terminal of the first comparator 5 is reached, the output signal c of the first comparator 5 becomes a low level state as shown in c of FIG. changes from to a high level state,
As a result, the first set-reset flip-flop 3 is reset at time t3, and the output signal b of the first set-reset flip-flop 3 changes from a high level state to a low level state, and the transistor Q1 The state changes from a conductive state to a non-conductive state, and the capacitor C1 in the time constant circuit 7 receives a signal at time t.
3, charging is started via the resistor R1, and the terminal voltage Vc of the capacitor C1 starts to rise from time t3 according to the time constant set in the time constant circuit 7.

Next, at time t4, when the terminal voltage Vc of the capacitor C1 supplied to the non-inverting input terminal of the second comparator 6 reaches the reference voltage V2 supplied to the inverting input terminal of the second comparator 6, the 2 comparator 6
The output signal d changes from a low level state to a high level state as shown in d of FIG. At this time t4, Noah Gate G1
Since the two inputs of AND gate G2 are both at low level, the two inputs of AND gate G2 are both at high level at time t4, and therefore, the output signal e of AND gate G2 is as shown in e of FIG. The second reset flip-flop 4 is reset at time t4, and the output signal sent from its Q terminal to the output terminal 2 changes from a low level state to a high level state at time t4. As shown in f in FIG. 2, f changes from a high level state to a low level state at time t4.

As described above, the monostable multivibrator shown in the first diagram has an input trigger pulse a at the signal input terminal 1.
The output terminal 2 operates to send out an output signal f having a predetermined pulse width to the output terminal 2 each time it is supplied.

FIG. 3 shows the first reset flip-flop 3, the first comparator 5, and the reference voltage source V in the monostable multivibrator shown in FIG.
3 is a circuit diagram showing a specific example of the configuration of each part such as transistors Q4 to Q7, resistors R7 to R9, R11, etc. in FIG. The circuit layout consisting of transistors Q4 to Q7, resistors R7 to R9, R11, etc. in FIG. 3 corresponds to the first set-reset flip-flop 3 in FIG.

That is, in FIG. 3, the first reset flip-flop 3 has transistors Q5 and Q6 whose bases and collectors are cross-connected via resistors R9 and R11, and whose emitters are grounded. , a transistor Q4 whose collector is connected to the collector of the transistor Q5 described above, whose emitter is grounded and whose base serves as a set input terminal, and whose collector is connected to the collector of the transistor Q6 described above. and a transistor Q7 whose emitter is grounded and whose base serves as a reset input terminal, and the transistor Q described above.
4, a collector load R8 connected between the commonly connected collectors of Q5 and the power supply Vcc, and a configuration in which the commonly connected collectors of the transistors Q6 and Q7 described above are used as output terminals. It is said that

In addition, the components in FIG. 3 that correspond to the first comparator 5 shown in FIG.
The above two transistors Q in a differential amplifier in which a current source I is connected between the commonly connected emitters of the transistors Q8 and Q9 and the power supply Vcc.
8. The base of one transistor Q8 in Q9 is set as a non-inverting input terminal so that the reference voltage V1 is supplied to it, and the base of the other transistor Q9 in the two transistors Q8, Q9 is set as an inverting input terminal. , a clamp circuit (transistor Q10) is connected thereto so that the output signal of the time constant circuit 7 is supplied thereto, and the voltage at the inverting input terminal does not fall below the reference voltage V1. , a diode D1 serving as a load is connected between the collector of the transistor Q9 and the ground, and
An output signal is obtained from the collector of the transistor Q9, and the above-mentioned transistor Q
The collector of the reset flip-flop 3 is connected to the output side of the first reset flip-flop 3.

An input trigger pulse is supplied to the base of the transistor Q4 through a resistor R7, and the output signal of the first reset flip-flop 3 is connected to the collectors of the transistors Q6 and Q7 and the transistor Q8.
From the connection point between the collector of and resistor R9, resistor R10
It is supplied to the base of transistor Q1 via line 1, and to a NOR gate G1 (not shown) via line l.

The collector of the transistor Q9 described above is connected to the base of the transistor Q7, and the base of the transistor Q9 is connected to the connection point between the emitter of the transistor Q10, the collector of the transistor Q1, and the capacitor C1 and resistor R1 of the time constant circuit 7. It is connected. Further, the collector of the transistor Q10 described above is connected to the power supply Vcc,
Further, its base is connected to the base of the transistor Q3 and the connection point between the resistor R5 and the resistor R4 in a voltage dividing network consisting of resistors R3 to R5.

Resistor R in the voltage divider network consisting of the above-mentioned resistors R3 to R5 configured between the power supply Vcc and ground
The voltage generated at the connection point between 5 and resistor R4 is applied to the transistor Q, which constitutes an emitter follower stage by the transistor Q3 and resistor R6.
The voltage appearing as a reference voltage V1 at the emitter of No. 3 and generated at the connection point between resistor R3 and resistor R4 in the voltage dividing network consisting of resistors R3 to R5 described above is generated by transistor Q2 and resistor R2. It appears as a reference voltage V2 at the emitter of transistor Q2 constituting the emitter follower stage.

As mentioned above, the reference voltages V1 and V2 used as the reference voltages of the first and second comparators 5 and 6 are as follows:
Since it is determined by the resistance ratio of the voltage dividing circuit, the differential voltage V2-V1 does not change even if the temperature changes.

Further, since the voltage generated at the connection point between the resistor R5 and the resistor R4 in the voltage dividing network consisting of the resistors R3 to R5 described above is supplied to the base of the transistor Q10 described above, the transistor Q1
Transistor Q9 to which the emitter of 0 is connected
The voltage of the base circuit of is set so as not to drop below the reference voltage V1.

In other words, the transistor Q10 described above controls the terminal voltage of the capacitor C1 in the time constant circuit 7.
It is non-conductive when Vc is higher than the reference voltage V1, but becomes conductive when the voltage Vc and V1 become equal, and the lower limit of the terminal voltage Vc of the capacitor C1 in the time constant circuit 7 is set to V1. It is clamped to.

Thereby, a complete loop for making the transistor Q1 non-conductive, that is, a complete loop consisting of the first comparator 5 -> the first reset flip-flop 3 -> the transistor Q1 -> the first comparator 5. By compensating for the time delay in the response of the loop, the terminal voltage Vc of the capacitor C1 in the time constant circuit 7 is
The timing at which the terminal voltage Vc of the capacitor C1 generated by the time constant circuit 7 starts rising from the voltage value corresponding to the reference voltage V1 is determined accurately. Therefore, the above-mentioned differential voltage V2-
The pulse width of the output signal determined by V1 is not affected by circuit variations, and the pulse width of the output signal does not change even if the temperature changes.

(Effects) As is clear from the detailed explanation above, the monostable multivibrator circuit of the present invention includes a time constant circuit, and an inverting input terminal in which the output voltage of the time constant circuit is applied to the inverting input terminal, and a non-inverting input terminal. The input terminal of the first comparator is supplied with the reference voltage V1, the non-inverting input terminal is supplied with the output voltage of the time constant circuit described above, and the inverting input terminal is supplied with V2<V1. A second comparator is provided with a reference voltage V2 having a relationship of a set-reset flip-flop, means for resetting a time constant circuit based on the output signal of the first set-reset flip-flop;
a second set-reset flip-flop which is reset by the output of a logic circuit to which the output of the comparator is applied; and an output signal is obtained from the output terminal of the second set-reset flip-flop. Therefore, in the monostable multivibrator of the present invention, the output voltage Vc from the time constant circuit is
It is obtained as a voltage value between the reference voltage V1/V2, so that the transistor Q1 does not saturate, and there is no temperature characteristic between the reference voltages that determine the pulse width of the output signal, and the circuit Since it is not affected by element delays, it is possible to provide an extremely stable monostable multivibrator whose output signal pulse width does not change even with changes in temperature.

[Brief explanation of drawings]

Fig. 1 is a block circuit diagram of an embodiment of the monostable multivibrator of the present invention, Fig. 2 is a waveform diagram for explaining the operation of the monostable multivibrator shown in Fig. 1,
Figure 3 is a circuit diagram of a partial configuration example of the monostable multivibrator shown in Figure 1, Figure 4 is a block circuit diagram of a configuration example of a conventional monostable multivibrator, and Figure 5 is a circuit diagram of a part of the monostable multivibrator shown in Figure 4. FIG. 3 is a waveform diagram for explaining the operation of the multivibrator. DESCRIPTION OF SYMBOLS 1... A signal input terminal to which an input trigger pulse is supplied, 2... An output terminal for an output signal of a monostable multivibrator, 3... A first set-reset flip-flop, 4... A second set-reset flip-flop, A time constant circuit constituted by a resistor R1 and a capacitor C1, 5... a first comparator, 6...
Second comparator, 7... Time constant circuit constituted by resistor R1 and capacitor C1, 9... Inverter, Q1... Capacitor C in time constant circuit 7
A transistor that discharges the accumulated charge of 1, V1, V
2... Reference voltage source, G1... NOR gate, G2... AND gate.

Claims (1)

[Claims] 1. A time constant circuit; a comparator; and a second comparison, in which the output voltage of the time constant circuit described above is applied to the non-inverting input terminal, and the reference voltage V2 having a relationship of V2<V1 is applied to the inverting input terminal. a first set-reset flip-flop set by the input trigger pulse and reset by the output of the first comparator; means for resetting the time constant circuit based on the output signal of the second comparator; 1. A monostable multivibrator comprising: a set-reset flip-flop; and means for obtaining an output signal from the output terminal of said second set-reset flip-flop. 2 The first set-reset flip-flop includes first and second transistors whose bases and collectors are cross-connected via a resistor and whose emitters are grounded, and the first transistor described above. The collector is connected to the collector of , and the emitter is grounded, and
A third transistor whose base is used as a set input terminal, and a third transistor whose collector is connected to the collector of the second transistor described above, whose emitter is grounded, and whose base is used as a reset input terminal. 4 transistors,
A collector load is connected between the commonly-connected collectors of the first and third transistors described above and a power supply, and the commonly-connected collector sides of the second and fourth transistors are used as an output terminal. A monostable multivibrator according to claim 1, which uses a monostable multivibrator configured as follows. 3 As the first comparator, connect the base of one of the two transistors described above to the non-inverting input terminal in a differential amplifier in which a current source is connected between the commonly connected emitters of the two transistors and the power supply. In addition, the base of the other of the two transistors described above is set as an inverting input terminal, and the output signal of the time constant circuit is supplied to it, and the inverting input Connect a clamp circuit to prevent the terminal voltage from dropping below the reference voltage V1, and
A diode serving as a load is connected between the collector of the other transistor described above and the ground, and an output signal is obtained from the collector,
2. The monostable multivibrator according to claim 1, further comprising one transistor whose collector is connected to the output side of the first set-reset flip-flop.