JPS6349824U - - Google Patents
Info
- Publication number
- JPS6349824U JPS6349824U JP14366786U JP14366786U JPS6349824U JP S6349824 U JPS6349824 U JP S6349824U JP 14366786 U JP14366786 U JP 14366786U JP 14366786 U JP14366786 U JP 14366786U JP S6349824 U JPS6349824 U JP S6349824U
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- voltage
- reference voltage
- potential
- charge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000007599 discharging Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は、本考案のクロツク発生回路の一例を
示す図、第２図は、従来のクロツク発生回路の一
例を示す図、及び第３図は、本考案中のコンパレ
ータの入出力電圧を示す図である。
１，２，３，４，２１，２２，２３……トラン
ジスタ、５，６，２５……定電圧源、７，２６…
…出力端、８，２０……コンデンサ、９，２４…
…定電流源、１０，１１，１２，１３，１４，１
５，１６，１７，２７……抵抗、１８，１９……
スイツチ。
FIG. 1 is a diagram showing an example of the clock generation circuit of the present invention, FIG. 2 is a diagram showing an example of the conventional clock generation circuit, and FIG. 3 is a diagram showing the input/output voltage of the comparator of the present invention. It is a diagram. 1, 2, 3, 4, 21, 22, 23...transistor, 5, 6, 25...constant voltage source, 7, 26...
...Output end, 8, 20...Capacitor, 9, 24...
...constant current source, 10, 11, 12, 13, 14, 1
5, 16, 17, 27...Resistance, 18, 19...
Switch.
Claims (1)
かるコンデンサの電荷を放電するための手段と、
かかるコンデンサの電位を入力とし、第１の基準
電圧と前記第１の基準電圧より高い第２の基準電
圧を有するシユミツト回路と、前記シユミツト回
路の出力状態により前記コンデンサへの充電をオ
ン・オフする第１のスイツチ手段により構成され
、前記コンデンサの電位が前記第１と第２の基準
電圧の間でくり返し充放電されるようにしたクロ
ツク発生回路において、前記コンデンサの電位を
前記第１の基準電圧より低い電圧に固定する第２
のスイツチ手段と前記第２の基準電圧より高い電
圧に固定する第３のスイツチ手段を有し、前記第
２もしくは第３のスイツチの動作により生ずる前
記コンデンサの電位の変化を微分して得られたパ
ルスでシステムの初期状態の設定を行えるように
したことを特徴とするクロツク発生回路。 means for passing a current of charge through a capacitor; and means for discharging the charge on such a capacitor;
A Schmitt circuit that inputs the potential of the capacitor and has a first reference voltage and a second reference voltage higher than the first reference voltage, and turns on/off charging of the capacitor depending on the output state of the Schmitt circuit. In a clock generating circuit configured by a first switch means, the potential of the capacitor is repeatedly charged and discharged between the first and second reference voltages, the potential of the capacitor is set to the first reference voltage. The second fixing to a lower voltage
and a third switch means for fixing the voltage to a voltage higher than the second reference voltage, and the voltage is obtained by differentiating a change in the potential of the capacitor caused by the operation of the second or third switch. A clock generation circuit characterized in that the initial state of the system can be set using pulses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14366786U JPH0526825Y2 (en) | 1986-09-19 | 1986-09-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14366786U JPH0526825Y2 (en) | 1986-09-19 | 1986-09-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6349824U true JPS6349824U (en) | 1988-04-04 |
| JPH0526825Y2 JPH0526825Y2 (en) | 1993-07-07 |
Family
ID=31053563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14366786U Expired - Lifetime JPH0526825Y2 (en) | 1986-09-19 | 1986-09-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0526825Y2 (en) |
-
1986
- 1986-09-19 JP JP14366786U patent/JPH0526825Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0526825Y2 (en) | 1993-07-07 |
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