JPS6355627U - - Google Patents
Info
- Publication number
- JPS6355627U JPS6355627U JP15024486U JP15024486U JPS6355627U JP S6355627 U JPS6355627 U JP S6355627U JP 15024486 U JP15024486 U JP 15024486U JP 15024486 U JP15024486 U JP 15024486U JP S6355627 U JPS6355627 U JP S6355627U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- capacitor
- reference voltage
- potential
- generation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 6
- 238000007599 discharging Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は、本考案のクロツク発生回路の一例を
示す図、第２図は、従来のクロツク発生回路の一
例を示す図である。
１，２，３，４……トランジスタ、５，６……
定電圧源、７……出力端、８……コンデンサ、９
……定電流源、１０，１１，１２，１３，１４，
１５，１６，１７……抵抗、１８，１９……スイ
ツチ。
FIG. 1 is a diagram showing an example of a clock generation circuit according to the present invention, and FIG. 2 is a diagram showing an example of a conventional clock generation circuit. 1, 2, 3, 4...transistor, 5, 6...
Constant voltage source, 7... Output end, 8... Capacitor, 9
...constant current source, 10, 11, 12, 13, 14,
15, 16, 17...resistance, 18, 19...switch.
Claims (1)
かるコンデンサの電荷を放電するための手段と、
かかるコンデンサの電位を入力とし第１の基準電
圧と前記第１の基準電圧より高い第２の基準電圧
を有するシユミツト回路と、前記シユミツト回路
の出力状態により前記コンデンサへの充電をオン
・オフする第１のスイツチ手段により、構成され
、前記コンデンサの電位が前記第１と第２の基準
電圧の間でくり返し充放電されるようにしたクロ
ツク発生回路において、前記コンデンサの電位を
前記第１の基準電圧より低い電圧に固定する第２
のスイツチ手段と、前記第２の基準電圧より高い
電圧に固定する第３のスイツチ手段を有すること
を特徴とするクロツク発生回路。 means for passing a current of charge through a capacitor; and means for discharging the charge on such a capacitor;
a Schmitt circuit which inputs the potential of the capacitor and has a first reference voltage and a second reference voltage higher than the first reference voltage; In the clock generation circuit, the clock generation circuit is configured by a switch means in which the potential of the capacitor is repeatedly charged and discharged between the first and second reference voltages, the potential of the capacitor is set to the first reference voltage. The second fixing to a lower voltage
1. A clock generation circuit comprising: switch means for switching the clock voltage to a voltage higher than the second reference voltage; and a third switch means for fixing the voltage to a voltage higher than the second reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15024486U JPH057778Y2 (en) | 1986-09-29 | 1986-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15024486U JPH057778Y2 (en) | 1986-09-29 | 1986-09-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6355627U true JPS6355627U (en) | 1988-04-14 |
| JPH057778Y2 JPH057778Y2 (en) | 1993-02-26 |
Family
ID=31066211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15024486U Expired - Lifetime JPH057778Y2 (en) | 1986-09-29 | 1986-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH057778Y2 (en) |
-
1986
- 1986-09-29 JP JP15024486U patent/JPH057778Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH057778Y2 (en) | 1993-02-26 |
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