JPH02103915U - - Google Patents
Info
- Publication number
- JPH02103915U JPH02103915U JP1133489U JP1133489U JPH02103915U JP H02103915 U JPH02103915 U JP H02103915U JP 1133489 U JP1133489 U JP 1133489U JP 1133489 U JP1133489 U JP 1133489U JP H02103915 U JPH02103915 U JP H02103915U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- power
- field effect
- polarity
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
Landscapes
- Amplifiers (AREA)
Description
第１図はこの考案の一実施例によるＢＳコンバ
ータの高周波増幅回路の構成を示す回路図、第２
図は従来のＢＳコンバータの高周波増幅回路の構
成を示す回路図である。
２……電界効果トランジスタ（ＦＥＴ）、６…
…極性変換回路（負電圧発生回路）、７……スイ
ツチ用トランジスタ、８……ツエナダイオード、
Ｔ３……入力端子（直流供給端子）。
Fig. 1 is a circuit diagram showing the configuration of a high frequency amplification circuit of a BS converter according to an embodiment of this invention;
The figure is a circuit diagram showing the configuration of a high frequency amplification circuit of a conventional BS converter. 2... Field effect transistor (FET), 6...
...Polarity conversion circuit (negative voltage generation circuit), 7...Switch transistor, 8...Zena diode,
T3...Input terminal (DC supply terminal).
Claims (1)
から入力して正負いずれか他方の極性の直流電力
を出力する極性変換回路を有し、前記入力端子か
ら入力した電力と前記極性変換回路の出力電力と
によつて電界効果トランジスタを駆動する電界効
果トランジスタ用電源回路において、 前記電界効果トランジスタのドレインと前記入
力端子との間に直列に介装されたスイツチ用トラ
ンジスタと、前記極性変換回路の出力端と前記ス
イツチ用トランジスタのベースとの間に接続され
たツエナダイオードとを備えたことを特徴とする
電界効果トランジスタ用電源回路。[Claims for Utility Model Registration] A polarity conversion circuit that inputs DC power of either positive or negative polarity from an input terminal and outputs DC power of the other polarity, either positive or negative, and the power input from the input terminal. and a switch transistor interposed in series between the drain of the field effect transistor and the input terminal; and a switch transistor interposed in series between the drain of the field effect transistor and the input terminal. . A power supply circuit for a field effect transistor, comprising: a Zener diode connected between an output end of the polarity conversion circuit and a base of the switch transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1133489U JPH02103915U (en) | 1989-02-01 | 1989-02-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1133489U JPH02103915U (en) | 1989-02-01 | 1989-02-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02103915U true JPH02103915U (en) | 1990-08-17 |
Family
ID=31219800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1133489U Pending JPH02103915U (en) | 1989-02-01 | 1989-02-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02103915U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008227921A (en) * | 2007-03-13 | 2008-09-25 | Fujitsu Ltd | Method and apparatus for turning on off fet to be used in amplifier |
| JP2009514473A (en) * | 2005-11-01 | 2009-04-02 | ゼテックス・セミコンダクターズ・パブリック・リミテッド・カンパニー | Monolithic LNA support IC |
-
1989
- 1989-02-01 JP JP1133489U patent/JPH02103915U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009514473A (en) * | 2005-11-01 | 2009-04-02 | ゼテックス・セミコンダクターズ・パブリック・リミテッド・カンパニー | Monolithic LNA support IC |
| JP2008227921A (en) * | 2007-03-13 | 2008-09-25 | Fujitsu Ltd | Method and apparatus for turning on off fet to be used in amplifier |
| JP4685820B2 (en) * | 2007-03-13 | 2011-05-18 | 富士通株式会社 | Method and apparatus for powering on and off FETs used in amplifiers |