JPH0321991U - - Google Patents
Info
- Publication number
- JPH0321991U JPH0321991U JP8286189U JP8286189U JPH0321991U JP H0321991 U JPH0321991 U JP H0321991U JP 8286189 U JP8286189 U JP 8286189U JP 8286189 U JP8286189 U JP 8286189U JP H0321991 U JPH0321991 U JP H0321991U
- Authority
- JP
- Japan
- Prior art keywords
- switching means
- diode
- capacitor
- parallel
- snubber circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 7
- 238000004804 winding Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 1
Landscapes
- Protection Of Static Devices (AREA)
Description
第1図は本考案の第1実施例を示す図、第2図
は各波形を示す図、第3図は本考案の第2実施例
を示す図、第4図は本考案の第3実施例を示す図
、第5図は本考案の第4実施例を示す図、第6図
A,BはMOSFETを示す図、第7図は従来例
を示す図、第8図は本考案をシングルフオワード
方式に用いる方法を示す図である。
図中、11……入力電源、12……出力トラン
スの1次巻線、13……インバータトランジスタ
(第1のスイツチ手段)、14……スナバ用コン
デンサ、15……スナバ用ダイオード、16……
インバータトランジスタ(第2のスイツチング手
段)、17……スナバ回路、18,19……ドラ
イブ回路、20……制御回路、21……N型MO
SFETの内蔵ダイオード、22……N型MOS
FET、23……P型MOSFETの内蔵ダイオ
ード、24……P型MOSFET。
Fig. 1 is a diagram showing the first embodiment of the invention, Fig. 2 is a diagram showing each waveform, Fig. 3 is a diagram showing the second embodiment of the invention, and Fig. 4 is a diagram showing the third embodiment of the invention. Figure 5 is a diagram showing the fourth embodiment of the present invention, Figure 6 A and B are diagrams showing MOSFET, Figure 7 is a diagram showing a conventional example, and Figure 8 is a diagram showing the present invention in a single It is a figure which shows the method used for a forward system. In the figure, 11... input power supply, 12... primary winding of output transformer, 13... inverter transistor (first switching means), 14... snubber capacitor, 15... snubber diode, 16...
Inverter transistor (second switching means), 17... Snubber circuit, 18, 19... Drive circuit, 20... Control circuit, 21... N-type MO
Built-in diode of SFET, 22...N-type MOS
FET, 23...Built-in diode of P-type MOSFET, 24...P-type MOSFET.
Claims (1)
トランスの1次巻線に接続される第1のスイツチ
ング手段にコンデンサおよびアノード側が前記ス
イツチング手段にカソード側が前記コンデンサに
直列に接続されるダイオードを並列に接続し、該
ダイオードに第2のスイツチング手段を並列に接
続したことを特徴とするインバータのスナバ回路
。 (2) 前記ダイオードのカソード側を前記第1の
スイツチング手段に、前記ダイオードのアノード
側を前記コンデンサに接続したことを特徴とする
前記請求項第1項記載のインバータのスナバ回路
。 (3) 一端が入力電源のプラス側に他端が出力ト
ランスの1次巻線に接続される第1のスイツチン
グ手段にコンデンサおよびアノード側が前記第1
のスイツチング手段にカソード側が前記コンデン
サに直列に接続されるダイオードを並列に接続し
、該ダイオードに第2のスイツチング手段を並列
に接続したことを特徴とするインバータのスナバ
回路。 (4) 前記第2のスイツチング手段および前記ダ
イオードを前記第1のスイツチング手段と並列に
接続するとともに、第1のスイツチンク手段と第
2のスイツチング手段との間に前記コンデンサを
接続したことを特徴とする前記請求項3記載のイ
ンバータのスナバ回路。[Claims for Utility Model Registration] (1) A capacitor connected to the first switching means having one end connected to the negative side of the input power source and the other end connected to the primary winding of the output transformer, and the anode side connected to the switching means and the cathode side connected to the first switching means. 1. A snubber circuit for an inverter, characterized in that a diode connected in series to a capacitor is connected in parallel, and a second switching means is connected in parallel to the diode. (2) The snubber circuit for an inverter according to claim 1, wherein the cathode side of the diode is connected to the first switching means, and the anode side of the diode is connected to the capacitor. (3) The first switching means has one end connected to the positive side of the input power supply and the other end connected to the primary winding of the output transformer, and the capacitor and the anode side connected to the first switching means.
A snubber circuit for an inverter, characterized in that a diode whose cathode side is connected in series to the capacitor is connected in parallel to the switching means, and a second switching means is connected in parallel to the diode. (4) The second switching means and the diode are connected in parallel with the first switching means, and the capacitor is connected between the first switching means and the second switching means. The snubber circuit for an inverter according to claim 3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8286189U JPH0321991U (en) | 1989-07-14 | 1989-07-14 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8286189U JPH0321991U (en) | 1989-07-14 | 1989-07-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0321991U true JPH0321991U (en) | 1991-03-06 |
Family
ID=31630044
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8286189U Pending JPH0321991U (en) | 1989-07-14 | 1989-07-14 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0321991U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58172979A (en) * | 1982-04-02 | 1983-10-11 | Hitachi Ltd | Inverter circuit |
JPH0197175A (en) * | 1987-10-06 | 1989-04-14 | Fuji Electric Co Ltd | Energy recovery circuit for inverter |
-
1989
- 1989-07-14 JP JP8286189U patent/JPH0321991U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58172979A (en) * | 1982-04-02 | 1983-10-11 | Hitachi Ltd | Inverter circuit |
JPH0197175A (en) * | 1987-10-06 | 1989-04-14 | Fuji Electric Co Ltd | Energy recovery circuit for inverter |
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