JPS61206327U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is an electric circuit diagram showing an embodiment of the gate circuit of a field effect transistor according to the present invention, Fig. 2 is a waveform diagram of each part when the input voltage is low, and Fig. 3 is a waveform diagram of each part when the input voltage is high. FIG. 4 is a conventional gate circuit diagram, and FIG. 5 is a waveform diagram of various parts in the conventional circuit. 1...DC input power supply, 2...Transformer, 4...FET,
8... IC for pulse width control, 9... Pulse transformer,
12...Primary winding, 13...Secondary winding, 14, 15,
33...Resistor, 16...Capacitor, 17...First rectifier, 18...Transistor, 19...Second rectifier.

Claims (1)

[Claims for Utility Model Registration] (1) In a gate control circuit formed by coupling the secondary winding of a pulse transformer controlled by a pulse width control IC to the gate and source of a field effect transistor, A capacitor and a first rectifier are inserted in series between the gate of the effect transistor and the positive side of the secondary winding of the pulse transformer; a transistor is inserted between the gate and source of the field effect transistor; A second rectifier is coupled between the negative side of the secondary winding and a connection point between the capacitor and the first rectifier, and the cathode of the second rectifier is coupled to the base of the transistor. gate control circuit for field effect transistors. (2) Insert a resistor between the gate of the field effect transistor and the emitter of the transistor, insert a resistor between the positive side of the secondary winding of the pulse transformer and the capacitor, and insert a resistor in parallel with this capacitor. A gate control circuit for a field effect transistor according to claim 1 of the utility model registration claim.