JPS6241390U

JPS6241390U -

Info

Publication number: JPS6241390U
Application number: JP13106285U
Authority: JP
Priority date: 1985-08-28
Filing date: 1985-08-28
Publication date: 1987-03-12

Description

[Brief explanation of the drawing]

第１図はこの考案の実施例を示す回路図、第２
図は第１図の実施例の各部の動作波形図、第３図
は第１図で使用しているスイツチ回路の回路図、
第４図はスイツチ回路の他の構成を示す回路図、
第５図はスイツチ回路のスイツチ素子の変形例を
示す回路図、第６図Ａ，Ｂはそれぞれスイツチ回
路の変形例を示す回路図、第７図は従来のインバ
ータの回路図、第８図は第７図のインバータの各
部の動作波形図、第９図は従来のｎ相交流を出力
するインバータの回路図、第１０図は提案された
インバータのクロツク遅延回路を示す回路図、第
１１図は提案されたインバータの各部の動作波形
図である。１，２，３，４：出力トランジスタ、５，１３
：直流電源、７：負荷、８，８_１，８_２………８
ｎ：駆動トランス、９，９_１，９_２………９_ｎ：
駆動回路、１０，１０′：クロツク発生器、１１
，１２，３７：トランジスタ、１４，２５：否定
回路、２０：きよし状波発生器、２１：比較器、
２２，２３：アンドゲート、２４：基準電池、２
６，２６_１，２６_２………２６_ｎ：クロツク遅延
回路、２９_１ａ，２９_１ｂ，２９_２ａ，２９_２ｂ………２９_ｎａ，２９_ｎｂ：スイツチ回路、３０
：スイツチ素子、３１：制限抵抗器、３２：逆方
向ダイオード、３３：コンデンサ、３４：順方向
ダイオード、３５：ベース用抵抗器、３６：スピ
ードアツプ用トランジスタ、３８：抵抗器、３９
，４１：ダイオード、４０：フオトカプラ、５０
_１，５０_２………５０_ｎ：出力トランジスタの直
列接続回路。 Figure 1 is a circuit diagram showing an embodiment of this invention, Figure 2 is a circuit diagram showing an embodiment of this invention.
The figure is an operating waveform diagram of each part of the embodiment in Figure 1, Figure 3 is a circuit diagram of the switch circuit used in Figure 1,
FIG. 4 is a circuit diagram showing another configuration of the switch circuit,
FIG. 5 is a circuit diagram showing a modification of the switch element of the switch circuit, FIGS. 6A and B are circuit diagrams showing modifications of the switch circuit, FIG. 7 is a circuit diagram of a conventional inverter, and FIG. Figure 7 is an operating waveform diagram of each part of the inverter, Figure 9 is a circuit diagram of a conventional inverter that outputs n-phase AC, Figure 10 is a circuit diagram showing the clock delay circuit of the proposed inverter, and Figure 11 is a circuit diagram of a conventional inverter that outputs n-phase AC. FIG. 3 is an operation waveform diagram of each part of the proposed inverter. 1, 2, 3, 4: Output transistor, 5, 13
: DC power supply, 7: Load, 8, 8 ₁ , 8 ₂ ......8
n: Drive transformer, 9, 9 ₁ , 9 ₂ ......9 _n :
Drive circuit, 10, 10': clock generator, 11
, 12, 37: transistor, 14, 25: inverting circuit, 20: clean wave generator, 21: comparator,
22, 23: AND gate, 24: Reference battery, 2
6, 26 ₁ , 26 ₂ ......26 _n : Clock delay circuit, 29 _1a , 29 _1b , 29 _2a , 29 _2b ......29 _na , 29 _nb : switch circuit, 30
: Switch element, 31: Limiting resistor, 32: Reverse diode, 33: Capacitor, 34: Forward diode, 35: Base resistor, 36: Speed-up transistor, 38: Resistor, 39
, 41: Diode, 40: Photocoupler, 50
_1,502 ...... _50n : Series connection circuit of output _transistors .

Claims

[Claims for Utility Model Registration] A plurality of series-connected circuits of first and second output transistors that are controlled to be turned on and off alternately are connected to a common DC power supply, and the first and second transistors of these series-connected circuits are connected to a common DC power source. The mutual connection points are connected to the load,
Transistor drive voltages of opposite polarity are applied from the first and second secondary windings of the drive transformer between the base and emitter of the first and second transistors of each of these series-connected circuits, respectively. In the inverter, the first and second output transistors are alternately turned on and off to convert the power of the DC power source into AC power and supply the AC power to the load, the base and emitter of each of the first and second output transistors and the 1st and 2nd drive transformer
First and second switch circuits are respectively provided between the next winding and each of the switch circuits has a switch element and a limiting resistor for limiting the base current in a path through which the base current of the output transistor circulates. A reverse diode is inserted in parallel with the switch element and in a direction opposite to the direction in which the base current circulates, and a forward diode is connected in parallel with the limiting resistor and in the forward direction of the base current that circulates. A series circuit consisting of a capacitor and a capacitor is connected with the capacitor placed on the output transistor side, and the base-emitter of the speed-up transistor and the base resistor are connected in parallel with the forward diode and in opposite directions to each other. A cascade circuit is connected, the collector of which is connected to the base or emitter of the output transistor to which the limiting resistor is not connected, and transmits the basic pulse from the pulse generator to the clock delay circuit for controlling the switching element on and off. A control signal is obtained by delaying the leading edge of the fundamental pulse by Δ time, and this control signal is applied to the switch elements of the first and second switch circuits, respectively, and the control signal is applied to the first and second output transistors. alternately,
An inverter characterized in that the base current is supplied at intervals of Δ time.