JPS62143334U - - Google Patents
Info
- Publication number
- JPS62143334U JPS62143334U JP3098086U JP3098086U JPS62143334U JP S62143334 U JPS62143334 U JP S62143334U JP 3098086 U JP3098086 U JP 3098086U JP 3098086 U JP3098086 U JP 3098086U JP S62143334 U JPS62143334 U JP S62143334U
- Authority
- JP
- Japan
- Prior art keywords
- series circuit
- drain
- field effect
- effect transistor
- switching element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004804 winding Methods 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electronic Switches (AREA)
Description
第１図ないし第３図はこの考案のスイツチング
素子の駆動回路の実施例を示し、第１図は１実施
例の結線図、第２図ａ〜ｃは第１図の動作説明用
タイミングチヤート、第３図は他の実施例の結線
図、第４図は従来例の結線図、第５図ａ〜ｃおよ
び第６図ａ〜ｃはそれぞれ第４図の動作説明用タ
イミングチヤートである。
１…直流電源、２…パルストランス、２ａ，２
ｃ…１次、２次巻線、４，１３，１５，１７…Ｆ
ＥＴ、１１…主ＦＥＴ、１４，１６…ダイオード
。
1 to 3 show an embodiment of the switching element drive circuit of this invention, FIG. 1 is a wiring diagram of one embodiment, and FIGS. 2 a to 3 are timing charts for explaining the operation of FIG. 1. FIG. 3 is a wiring diagram of another embodiment, FIG. 4 is a wiring diagram of a conventional example, and FIGS. 5 a to 6 c and 6 a to c are timing charts for explaining the operation of FIG. 4, respectively. 1...DC power supply, 2...Pulse transformer, 2a, 2
c...Primary, secondary winding, 4, 13, 15, 17...F
ET, 11... Main FET, 14, 16... Diode.
Claims (1)
１次巻線および第１の電界効果トランジスタ（以
下電界効果トランジスタをＦＥＴという）のドレ
イン、ソースの直列回路と、前記１次巻線に並列
に接続された第２のＦＥＴのソース、ドレインお
よびダイオードの直列回路と、出力端子が前記両
ＦＥＴのゲートに接続されたゲートパルス発生部
と、制御端子が前記パルストランスの２次巻線に
接続されたスイツチング素子とを備えたスイツチ
ング素子の駆動回路。 A series circuit of a primary winding of a pulse transformer connected in parallel to a DC power supply and a drain and source of a first field effect transistor (hereinafter referred to as a field effect transistor), and a series circuit connected in parallel to the primary winding. a series circuit of the source, drain, and diode of the second FET, a gate pulse generator whose output terminal is connected to the gates of both FETs, and a switching circuit whose control terminal is connected to the secondary winding of the pulse transformer. A switching element drive circuit comprising a switching element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3098086U JPH054347Y2 (en) | 1986-03-04 | 1986-03-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3098086U JPH054347Y2 (en) | 1986-03-04 | 1986-03-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62143334U true JPS62143334U (en) | 1987-09-10 |
| JPH054347Y2 JPH054347Y2 (en) | 1993-02-03 |
Family
ID=30836287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3098086U Expired - Lifetime JPH054347Y2 (en) | 1986-03-04 | 1986-03-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH054347Y2 (en) |
-
1986
- 1986-03-04 JP JP3098086U patent/JPH054347Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH054347Y2 (en) | 1993-02-03 |
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