JPH01124718U - - Google Patents
Info
- Publication number
- JPH01124718U JPH01124718U JP2056788U JP2056788U JPH01124718U JP H01124718 U JPH01124718 U JP H01124718U JP 2056788 U JP2056788 U JP 2056788U JP 2056788 U JP2056788 U JP 2056788U JP H01124718 U JPH01124718 U JP H01124718U
- Authority
- JP
- Japan
- Prior art keywords
- fet
- gate
- power supply
- controller
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Description
第１図はこの考案による実施例の構成図、第２
図は従来技術によるの構成図、第３図はＦＥＴの
説明図である。
１……電源、２……ダイオード、２Ａ……ＦＥ
Ｔ、３……ＦＥＴ、４……制御器、５……ドライ
バ、６……電源、７……出力、８……寄生ダイオ
ード、１１……電源、１２……ダイオード、１２
Ａ……ＦＥＴ、１３……ＦＥＴ、１５……ダイオ
ード。
Figure 1 is a configuration diagram of an embodiment according to this invention, Figure 2
The figure is a block diagram of a conventional technology, and FIG. 3 is an explanatory diagram of an FET. 1...Power supply, 2...Diode, 2A...FE
T, 3... FET, 4... Controller, 5... Driver, 6... Power supply, 7... Output, 8... Parasitic diode, 11... Power supply, 12... Diode, 12
A...FET, 13...FET, 15...diode.
Claims (1)
を使用する電源切換回路において、 第１の電源１に第１のＦＥＴ２Ａのソースを接
続し、 第１のＦＥＴ２Ａのドレインを第２のＦＥＴ３
のドレインに接続し、 第２のＦＥＴ３のソースを出力７に接続し、 第２の電源１１に第３のＦＥＴ１２Ａのソース
を接続し、 第３のＦＥＴ１２Ａのドレインを第４のＦＥＴ
１３のドレインに接続し、 第４のＦＥＴ１３のソースを出力７に接続し、 第１のＦＥＴ２Ａのゲートと第２のＦＥＴ３の
ゲートに制御器４の第１の端子４Ａからの制御信
号「１」を加え、第３のＦＥＴ１２Ａのゲートと
第４のＦＥＴ１３のゲートに制御器４の第２の端
子４Ｂからの制御信号「０」を加えて第１の電源
１を出力７に導き、 第３のＦＥＴ１２Ａのゲートと第４のＦＥＴ１
３のゲートに制御器４の第２の端子４Ｂからの制
御信号「１」を加え、第１のＦＥＴ２Ａのゲート
と第２のＦＥＴ３のゲートに制御器４の第１の端
子４Ａからの制御信号「０」を加えて第２の電源
１１を出力７に導くことを特徴とする電源切換回
路。[Scope of utility model registration claims] Power MOS FET (hereinafter referred to as FET)
In a power supply switching circuit that uses
The source of the second FET 3 is connected to the output 7, the source of the third FET 12A is connected to the second power supply 11, and the drain of the third FET 12A is connected to the fourth FET 12A.
The source of the fourth FET 13 is connected to the output 7, and the control signal "1" from the first terminal 4A of the controller 4 is connected to the gate of the first FET 2A and the gate of the second FET 3. and the control signal "0" from the second terminal 4B of the controller 4 is applied to the gate of the third FET 12A and the gate of the fourth FET 13 to lead the first power supply 1 to the output 7, Gate of FET12A and fourth FET1
A control signal "1" from the second terminal 4B of the controller 4 is applied to the gate of FET 3, and a control signal "1" from the first terminal 4A of the controller 4 is applied to the gate of the first FET 2A and the gate of the second FET 3. A power supply switching circuit characterized in that the second power supply 11 is guided to the output 7 by adding "0".
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2056788U JPH01124718U (en) | 1988-02-18 | 1988-02-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2056788U JPH01124718U (en) | 1988-02-18 | 1988-02-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01124718U true JPH01124718U (en) | 1989-08-24 |
Family
ID=31237048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2056788U Pending JPH01124718U (en) | 1988-02-18 | 1988-02-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01124718U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002111464A (en) * | 2000-09-29 | 2002-04-12 | Mitsumi Electric Co Ltd | Voltage switching circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5650555A (en) * | 1979-10-01 | 1981-05-07 | Hitachi Ltd | Switching circuit formed in semiconductor integrated circuit device and multilevel voltage generation circuit using the same |
| JPS56111320A (en) * | 1980-02-08 | 1981-09-03 | Nec Corp | Voltage switching control circuit |
-
1988
- 1988-02-18 JP JP2056788U patent/JPH01124718U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5650555A (en) * | 1979-10-01 | 1981-05-07 | Hitachi Ltd | Switching circuit formed in semiconductor integrated circuit device and multilevel voltage generation circuit using the same |
| JPS56111320A (en) * | 1980-02-08 | 1981-09-03 | Nec Corp | Voltage switching control circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002111464A (en) * | 2000-09-29 | 2002-04-12 | Mitsumi Electric Co Ltd | Voltage switching circuit |
| JP4552304B2 (en) * | 2000-09-29 | 2010-09-29 | ミツミ電機株式会社 | Voltage switching circuit |