JPS55102927A - Chattering removal circuit - Google Patents

Chattering removal circuit

Info

Publication number
JPS55102927A
JPS55102927A JP999679A JP999679A JPS55102927A JP S55102927 A JPS55102927 A JP S55102927A JP 999679 A JP999679 A JP 999679A JP 999679 A JP999679 A JP 999679A JP S55102927 A JPS55102927 A JP S55102927A
Authority
JP
Japan
Prior art keywords
signal
output
chattering
inverted
fall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP999679A
Other languages
Japanese (ja)
Other versions
JPH0113655B2 (en
Inventor
Toshiaki Nozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP999679A priority Critical patent/JPS55102927A/en
Publication of JPS55102927A publication Critical patent/JPS55102927A/en
Publication of JPH0113655B2 publication Critical patent/JPH0113655B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H03K5/1254—Suppression or limitation of noise or interference specially adapted for pulses generated by closure of switches, i.e. anti-bouncing devices

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To make it possible to remove the chattering occurring at a halfway point by intermitting the output of 1st FF by inverting FF, and then by feeding the output of 2nd FF back by inverting again the 1st FF at the fall of a next clock signal. CONSTITUTION:Once input signal IN with chattering is supplied, FF21 is inverted at the rise of clock signal CL arriving first after the chattering is removed. Then, FF24 is inverted at the fall of next signal CL and output OUT rises. Here, if chattering Ch2 occurs to signal IN at a halfway point, FF21 is inverted immediately, and in consequence its output Q is intermitted, so that it will be inverted again at the next fall of signal CL. However, since the output of FF24 is fed back by way of gates 22 and 23, it is never inverted until next signal CL falls even if the output of FF21 is intermitted. Consequently, the chattering occurring at the halfway point can be removed in addition to those at the head and tail of signal IN.
JP999679A 1979-01-31 1979-01-31 Chattering removal circuit Granted JPS55102927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP999679A JPS55102927A (en) 1979-01-31 1979-01-31 Chattering removal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP999679A JPS55102927A (en) 1979-01-31 1979-01-31 Chattering removal circuit

Publications (2)

Publication Number Publication Date
JPS55102927A true JPS55102927A (en) 1980-08-06
JPH0113655B2 JPH0113655B2 (en) 1989-03-07

Family

ID=11735455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP999679A Granted JPS55102927A (en) 1979-01-31 1979-01-31 Chattering removal circuit

Country Status (1)

Country Link
JP (1) JPS55102927A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6018020A (en) * 1983-07-12 1985-01-30 Seiko Epson Corp Stand-by circuit
US5168181A (en) * 1990-05-25 1992-12-01 Sgs-Thomson Microelectronics S.R.L. Spike filtering circuit for logic signals

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4928206A (en) * 1972-07-08 1974-03-13
JPS5169974A (en) * 1974-12-16 1976-06-17 Oki Electric Ind Co Ltd KIKANKEIRITO KUSEIGYOKAIRO
JPS5329265U (en) * 1976-08-20 1978-03-13

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5329265B2 (en) * 1972-09-20 1978-08-19

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4928206A (en) * 1972-07-08 1974-03-13
JPS5169974A (en) * 1974-12-16 1976-06-17 Oki Electric Ind Co Ltd KIKANKEIRITO KUSEIGYOKAIRO
JPS5329265U (en) * 1976-08-20 1978-03-13

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6018020A (en) * 1983-07-12 1985-01-30 Seiko Epson Corp Stand-by circuit
US5168181A (en) * 1990-05-25 1992-12-01 Sgs-Thomson Microelectronics S.R.L. Spike filtering circuit for logic signals

Also Published As

Publication number Publication date
JPH0113655B2 (en) 1989-03-07

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