JPS56143018A - Noise rejecting circuit - Google Patents
Noise rejecting circuitInfo
- Publication number
- JPS56143018A JPS56143018A JP4462880A JP4462880A JPS56143018A JP S56143018 A JPS56143018 A JP S56143018A JP 4462880 A JP4462880 A JP 4462880A JP 4462880 A JP4462880 A JP 4462880A JP S56143018 A JPS56143018 A JP S56143018A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- output
- level
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/24—Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing noise
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Control Of Velocity Or Acceleration (AREA)
- Control Of Electric Motors In General (AREA)
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To reject the noise produced in the leading and trailing of the rotating detection pulse signal and to make the circuit suitable for the servo circuit by digital signal processing, by constituting of R-FF, T-FF, coincidence circuit and counter circuit. CONSTITUTION:When a pulse signal 16 overlapping noise at leading and trailing is input at the input terminal 8, if the output 18 of T-FF11 is at H level, the output of a coincidence circuit 9 is at H level, and an R-FF10 is set. This output signal 19 and the reference clock signal 17 are fed to the counter circuit 14. When the output 21 of the circuit 14 is fed as the reset signal of FF10 and the clock signal of FF11, FF10 is reset and the output signal 19 is at L level. In this case, the circuit 14 is reset with the inverting signal Q' of the output signal 19. Thus, the counter output 21 is again at L level. On the other hand, the output 18 of T-FF11 is triggered with the said output signal 21 and inverted into L level. The coincidence with the L level at the trailing timing of the input signal 16 is detected at the circuit 9 and FF10 is again set.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4462880A JPS56143018A (en) | 1980-04-07 | 1980-04-07 | Noise rejecting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4462880A JPS56143018A (en) | 1980-04-07 | 1980-04-07 | Noise rejecting circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56143018A true JPS56143018A (en) | 1981-11-07 |
JPS6236571B2 JPS6236571B2 (en) | 1987-08-07 |
Family
ID=12696682
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4462880A Granted JPS56143018A (en) | 1980-04-07 | 1980-04-07 | Noise rejecting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56143018A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6477312A (en) * | 1987-09-18 | 1989-03-23 | Aisin Seiki | Noise removing circuit |
JPH01105205A (en) * | 1987-07-30 | 1989-04-21 | Mitsubishi Rayon Co Ltd | Clad material for optical fiber |
JPH02307382A (en) * | 1989-05-19 | 1990-12-20 | Sanyo Electric Co Ltd | Circuit for controlling motor speed |
EP2037580A1 (en) * | 2006-07-03 | 2009-03-18 | Toshiba Kikai Kabushiki Kaisha | Digital filter device, phase detection device, position detection device, ad conversion device, zero cross detection device, and digital filter program |
JP2010130550A (en) * | 2008-11-28 | 2010-06-10 | Seiko Epson Corp | Clock generating apparatus, and jitter reducing method in the same |
JP2010141499A (en) * | 2008-12-10 | 2010-06-24 | Toshiba Corp | Trigger signal detection apparatus |
JP2011004072A (en) * | 2009-06-17 | 2011-01-06 | Renesas Electronics Corp | Digital noise filter circuit |
JP2011097138A (en) * | 2009-10-27 | 2011-05-12 | Renesas Electronics Corp | Noise reduction circuit and semiconductor device provided with noise reduction circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS524158A (en) * | 1975-06-24 | 1977-01-13 | Hitachi Ltd | Noise eliminator |
JPS5313086A (en) * | 1976-07-21 | 1978-02-06 | Matsushita Electric Ind Co Ltd | Digital speed control sys tem |
-
1980
- 1980-04-07 JP JP4462880A patent/JPS56143018A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS524158A (en) * | 1975-06-24 | 1977-01-13 | Hitachi Ltd | Noise eliminator |
JPS5313086A (en) * | 1976-07-21 | 1978-02-06 | Matsushita Electric Ind Co Ltd | Digital speed control sys tem |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01105205A (en) * | 1987-07-30 | 1989-04-21 | Mitsubishi Rayon Co Ltd | Clad material for optical fiber |
JPS6477312A (en) * | 1987-09-18 | 1989-03-23 | Aisin Seiki | Noise removing circuit |
JPH02307382A (en) * | 1989-05-19 | 1990-12-20 | Sanyo Electric Co Ltd | Circuit for controlling motor speed |
EP2037580A1 (en) * | 2006-07-03 | 2009-03-18 | Toshiba Kikai Kabushiki Kaisha | Digital filter device, phase detection device, position detection device, ad conversion device, zero cross detection device, and digital filter program |
EP2037580A4 (en) * | 2006-07-03 | 2014-02-19 | Toshiba Machine Co Ltd | Digital filter device, phase detection device, position detection device, ad conversion device, zero cross detection device, and digital filter program |
JP2010130550A (en) * | 2008-11-28 | 2010-06-10 | Seiko Epson Corp | Clock generating apparatus, and jitter reducing method in the same |
US8339160B2 (en) | 2008-11-28 | 2012-12-25 | Seiko Epson Corporation | Clock generating device and jitter reducing method in the clock generating device |
JP2010141499A (en) * | 2008-12-10 | 2010-06-24 | Toshiba Corp | Trigger signal detection apparatus |
JP2011004072A (en) * | 2009-06-17 | 2011-01-06 | Renesas Electronics Corp | Digital noise filter circuit |
JP2011097138A (en) * | 2009-10-27 | 2011-05-12 | Renesas Electronics Corp | Noise reduction circuit and semiconductor device provided with noise reduction circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6236571B2 (en) | 1987-08-07 |
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