JPS55112059A - Clock extracting circuit - Google Patents

Abstract

PURPOSE:To secure generation of the clock signal although the input digital signal is cut off due to the fault of the digital circuit at the higher-rank station, thus avoiding the fault of the original closed circuit via the clock signal mentioned above. CONSTITUTION:The input digital signal received the conversion at signal converter circuit 3 is supplied to selection circuit 7 and detection circuit 6. The clock signal sent from amplitude limiting circuit 5 is supplied to one input of circuit 7 via delay circuit 8. Circuit 6 detects the presence or absence of the input digital signal and features a simple constitution with the monostable circuit. And in case the input digital signal exists, the proper logic level is delivered to output terminal 62. Then the contol is given so that the clock signal supplied to terminal 72 with the delay given may be selected to terminal 74 of circuit 7. In such case, the closed circuit comprising tuning circuit 4, circuit 5 pluse circuits 8 and 7 forms the positive feedback loop. For the delay amount of circuit 8, the clock signal is produced by circuit 8 itself by adjusting the delay amount of the closed loop to one cycle of the clock signal.