JPS567520A - Chattering rejection circuit - Google Patents

Chattering rejection circuit

Info

Publication number
JPS567520A
JPS567520A JP8457779A JP8457779A JPS567520A JP S567520 A JPS567520 A JP S567520A JP 8457779 A JP8457779 A JP 8457779A JP 8457779 A JP8457779 A JP 8457779A JP S567520 A JPS567520 A JP S567520A
Authority
JP
Japan
Prior art keywords
chattering
fed
input terminal
output
time limit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8457779A
Other languages
Japanese (ja)
Inventor
Norio Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8457779A priority Critical patent/JPS567520A/en
Publication of JPS567520A publication Critical patent/JPS567520A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Abstract

PURPOSE:To reject chattering from a single contact signal without delay, by providing two FFs of R-S type in series connection of two stages. CONSTITUTION:The contact signal 3a having chattering is fed to the set input terminal of FF3 of the first R-S type, and the set output 3b of FF3 is fed to the set input terminal of the second FF4 of R-S type and the time limit element 5 in series connection of the inverters 5-1, 5-2 and 5-3. Further, the set output 4a of FF4 is the output signal of this circuit unit and fed to the reset input terminal via the time limit circuit 6 of the same constitution as the time limit element 5. Further, the reset output 4b of FF4 is fed to the reset input terminal of FF3.
JP8457779A 1979-07-02 1979-07-02 Chattering rejection circuit Pending JPS567520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8457779A JPS567520A (en) 1979-07-02 1979-07-02 Chattering rejection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8457779A JPS567520A (en) 1979-07-02 1979-07-02 Chattering rejection circuit

Publications (1)

Publication Number Publication Date
JPS567520A true JPS567520A (en) 1981-01-26

Family

ID=13834519

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8457779A Pending JPS567520A (en) 1979-07-02 1979-07-02 Chattering rejection circuit

Country Status (1)

Country Link
JP (1) JPS567520A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0320711A2 (en) * 1987-12-14 1989-06-21 STMicroelectronics S.r.l. Antibounce circuit for digital circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0320711A2 (en) * 1987-12-14 1989-06-21 STMicroelectronics S.r.l. Antibounce circuit for digital circuits

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