JPS58173470A - Frequency detecting circuit - Google Patents

Abstract

PURPOSE:To reduce the size of a chip, by substituting two flip-flops for the fourth counter in a frequency detecting circuit. CONSTITUTION:Instead of the fourth counter C4, a flip-flop 9 (FF4) and 10 (DF5) for operating the third counter C3 two times and an NOR circuit 11 are provided. When an output Q2 of the counter C2 falls, the FF4 is set and the DF5 is reset. The NOR circuit 11 which is in ''H'' before that time becomes ''L'', and starts the first counting. Subsequently, after a prescribed time, the counting ends, the DF5 becomes ''H'' by an output Q3, and the counter C3 starts the second counting. Subsequently, in the same way, the counting ends, the output of the NOR circuit 11 becomes ''H'', and the counter C3 stops its operation. In this way, the number of internal elements is reduced, and the size of a chip can be made small.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency detection circuit, for example,
This invention relates to an improvement in a circuit that detects when the output frequency of an FG (frequency generator), etc. attached to a motor etc. reaches a certain level when starting the motor.

A conventional series of such circuits is shown in FIG. In Fig. 1, 1 is a counter C4, which starts counting clock pulses CK by inputting an output signal F such as FG, counts a preset value, stops its operation, and changes to 01 during counting. T, yields an output at a time of T. This operation is shown in d and b in Figure 2.
Shown below.

2 is a counter C2 which starts counting clock pulses CK at the rising edge of the output of the counter C4, and produces an output Q2 for a time T2 as shown in FIG. 2C.

The counter C3 of 3 and the counter C4 of 4 performs the same operation as the above-mentioned counter, but produces an output of the time TO/, as shown in FIG. 2d and e. Here T=
T, 10T2.

In this circuit, output Q, and A1 of C4 (D times fo
The ratio of the frequency σ9 of the signal F to is fF/f02/to+
It becomes 2.

Similarly, the AND circuit 8 of the output Q3 and the output Q1 can detect a frequency where fF/fo=+1.

Therefore, in ff1llH of a motor, etc., the FG frequency due to the set rotation is +1°k/k
It is detected that the +2 frequency has been reached.

However, in this circuit, 21 counters of C3 and C4 are used for the above-mentioned frequency detection.
The size of the counter was thick (there were drawbacks such as an increase in the step size due to the inability to use an IC).

The present invention aims to eliminate the above-mentioned drawbacks. Third
The figure is a block diagram showing an embodiment of the present invention, and FIG. 4 is an explanatory diagram of its operation. In FIG. 3, 1 and 2 are counters C1 and C2, respectively, whose operation is the same as that of the conventional example shown in FIG. 1, and as shown in FIG. Count clock pulses C'K by F and output Q1 and Q at times T1 and T2.
2f: Occurs.

The difference from the conventional example is that the counter C4 in FIG.
Instead, 7 lip-flops e(F F4), 1°(DF6) to operate the counter C3 of 3 twice.
and a NOR circuit 11.

In FIG. 3, shift lip 70 knob FF4 is set and DF6 is reset by the fall of output Q2 of counter C2. The NOR circuit 11, which had been "H" until then, becomes "L".

On the other hand, assuming that the counter C3 enters the counting state when its P terminal is 'L', it starts counting for the first time.Then, after a period of -, it completes the runt, and the output Q3 causes 7 rigs 70. Tsubu D...
F5 is inverted and becomes @H"', and flip 17 and 70 FF are reset and become 1L", but the output of NOR circuit 11 does not change and counter C3 starts counting for the second time. . Then, the count ends in the same way, and the output of the 7 logic loop DF6 is inverted by the output Q3 and becomes "L", and the output of the NOR circuit 11 becomes "H".
Therefore, the counter C3 stops operating.

In FIG. 4, the AND circuit 7 of outputs Q1 and 06 detects that TF-T0- has been reached, and the AND circuit 8 of Ql and Q- detects that TF=T0- has been reached. What you can do is the same as what you can do.

As described above, according to the frequency detection circuit of the present invention, the counter C4 in the conventional column is set to
By replacing it with DF6 and DF6, it is effective to reduce the number of internal elements and reduce the chip size when integrating the circuit.

[Brief explanation of drawings]

Figure 1 shows block diagrams 1 and 2 of a conventional frequency detection circuit.
3 is a block diagram showing the circuit configuration of the present invention, and FIG. 4 is an explanatory diagram of the operation of the same circuit. 1...First counter, 2...Second counter, 3...Third counter, 7, 8...t...A
SD circuit, 9...I 17th lip flop, 10'-
...Fist No. 27 Ripflop, 11 ...NO
R circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person11
Figure rk Figure 12 Gate-1I Ce) Nail Figure 13 k Figure 14

Claims (1)

[Claims] A first counter that starts counting clock pulses manually based on the detected signal, stops its operation after counting a certain value, and produces an output only during operation, and an Eri clock pulse count as an operation stop signal for the first counter. start,
a second counter that stops its operation after counting a certain value and produces an output only during operation; a first flip 70 set by h1+i, which stops the operation of the second counter; and stops the operation of the second counter. a twenty-seventh lip-flop reset by the signal and connected so that its output resets the first flip-flop 70;
N ORl! whose inputs are the respective outputs of the first and 27th lip frontogs. a third counter whose counting operation is controlled by the Jl path and the output of the NO.8 circuit, and is connected so that after counting clock pulses of a constant value, a count end signal is generated, and the signal inverts the 27th lip-frog. an AND circuit between the output of the first counter and the output of the first logic flop, and an AND circuit between the output of the first counter and the 27th lip 7
A frequency detection circuit that detects the frequency by an AND circuit with the output of 0p and p.