JPS62130023A - Initializing method for logic circuit - Google Patents

Abstract

PURPOSE:To stabilize the initializing operation by inputting >=2 pulses to a clock terminal of a shift register so as to release the initialization of a logic circuit to be initialized. CONSTITUTION:When power is applied at a time t0, a voltage in excess of a logic threshold value of a buffer 17 from an initializing circuit 15 at a time t1 is fed to a reset terminal of FFs f1, f2 to release the reset of the FFs f1, f2 at a time t2. Then the logic of a D input of the FF f1 is a Q output of the FF f1 by a clock pulse at a terminal 16 and the logic of the D input of the FF f2 is its Q output at a time t3. Thus, the logic at a terminal 13 is logical '0' at a period of times t0-t3 and shift registers F1-F5 in the circuit 11 to be initialized are all initialized to logical '1' up to the time t34. After the initialization is released at the time t3, the circuit 11 applied 1/10 frequency division to the clock and sends the result.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a method for initializing a logic circuit.

In conventional logic circuits such as TTI, 0MO8, ECL, IIL, and #, it is often necessary to determine the internal logic state when the power is turned on. In such cases, a method is often used in which the initialization terminal of the logic circuit is kept in a reset state for a certain period of time after the power is turned on, and the reset is released after the certain period of time has elapsed.

FIG. 3 shows a W-periodization circuit of a conventionally used logic circuit. FIG. 4 shows signal waveforms at each part in FIG.

Reference numeral 11 denotes a logic circuit to be initialized, and in this figure, a partial cycle circuit composed of six stages of shift registers is used as an example. 12 is a first clock pulse input terminal of the logic circuit 11 to be initialized; 13 is an initialization terminal of the logic circuit 11 to be initialized;
4 is an output terminal of the circuit 11 to be initialized. 26 is a conventional initialization circuit, 26 is a buffer, R1 is a resistor, and C1 is a capacitor.

The waveforms (2L) to 0) in Figure 4 are shown in Figure 3, respectively.
Shows the waveform of the points.

Now, assume that the circuit is powered on at time to. The power to each logic circuit is turned on at this time to (FIG. 4(a)). The potential at point ■ of the initialization circuit 16 is the resistance R
1 and the time constant of the capacitor C1, the waveform becomes as shown in Figure 4 (0:I), and the logic at the 0 point (initialization terminal 13) is reversed to 1 and initialization is canceled at the potential at the 0 point. is the time t1 when the signal crosses the logical threshold of the buffer 26.

In this way, initialization terminal 1 between 101 from to to tl
Since 3 is the logic Q, the shift 1/register (5 7-linops 70 from F1 to F6) in the initialized logic circuit 11
4), all of them change to logic 1 and initialize iυ1 by time t1, as shown in FIG. 4(f') to (3). After the initialization is canceled at time t1 (the logic at the 0 point is inverted to 1), the wave-cut jυ unity logic circuit 11 functions as the original partial cycle circuit, and at time t in FIG. 4 (f' to lj).
1.0 point clock as shown below (Figure 4(d))
is divided by Ko and output to the output terminal 14.

However, what problem does the invention try to solve? In the initial 1υ1 conversion method since +Y', initial jC1j conversion may not be completed completely due to noise.

Figure 6 shows the waveforms at points ■ to ■ in Figure 3 when initialization is not completed completely due to noise.1For example,
Assume that noise that crosses the logic threshold of the next buffer 26 is mixed into the signal at point 0 in FIG. 3 immediately after time t1, as shown in FIG. 6(b). As a result, the waveform at the @point initialization terminal 13 in FIG. 3 becomes as shown in FIG. 5(C). Such a waveform is generated by the initialization circuit 25 shown in FIG.
When the signal is input to the initial jυ1 terminal 13 of the circuit to be initialized 11, the subsequent waveforms at points ■ to ■ become as shown in FIG. This has the disadvantage that the frequency-divided waveform is no longer output from the output terminal 14.

In view of the above-mentioned drawbacks, the present invention seeks to provide a method for initial ItJlization of a logic circuit that can obtain stable initialization operations.

Means for Solving the Problems In order to solve the above problems, the logic circuit initialization method of the present invention connects two or more stages of shift registers in front of the initialization terminal of the wave-cut 1tJ, l-shaped logic circuit. After the logic circuit to be initialized is initialized, the reset of the register is released and two or more pulses are input to the clock terminal of the shift l/jimeta, and the logic circuit to be initialized is initialized. It is designed to remove the

Function: By the method described above, it is possible to realize a method for initializing a logic circuit that does not cause malfunctions due to noise or the like.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a process diagram showing an embodiment of the logic circuit initialization method according to the present invention.

15 is an initialization circuit which forms the main part of the present invention.

fl. and fl are flip-flops, respectively, and constitute a two-stage shift register. 16 is initialization circuit 1
5 is the input terminal for the second clock pulse.

The part at the center has the same function as that of the same number and symbol in FIG.

The waveforms (a) to (l!+) in FIG. 2 show the 1-h shape of the point ■ to 0 in FIG. Assume that the circuit is powered on at time to. The power supply of each logic circuit is turned on at this time t.

(Fig. 2(a)). The potential at the 0 point of the initialization circuit 15 has the waveform shown in FIG. 2(b) due to the time constant of the resistor R1 and the capacitor C1. This is the time t1 when the logic threshold of the buffer 17 is crossed. Furthermore, noise that crosses the logic threshold of the buffer 17 is present in the 0 point signal at time t1.
When mixed immediately after the buffer 17, the output of the buffer 17 is as shown in FIG.
) is the waveform shown.

Next, at time t2, the input waveforms of the reset terminals of flip-flops f1 and fl (point @ in FIG. 1, waveform C in FIG. 2) are logic 1, and the reset is released, so the second clock pulse The logic of the D input (fixed to logic 1) of the flip-flop f1 is transmitted to the Q output (0 point) of the flip-flop f1 by the clock pulse input from the input terminal 16 (FIG. 2(d)), and as shown in FIG. e)
3, when the logic is inverted to 1 as shown in FIG. (connected to the Q output of f1) is the Q output of flip-flop f2 (0 point)
The logic is inverted to 1 as shown in Figure 2 (0(()).

As a result, even if there is noise that crosses the logic threshold at the 0 point, it is possible to suppress the logic inversion around time t1 in FIG. 2(C) caused by the noise.

In this way, the initialization terminal 13 (
Since the Q output (connected to the 0 point) of the flip-flop f2 is logic 0, the shift register in the initialized circuit 13 (consisting of six flip-flop knobs F1 to F5) is set to the second As shown in Figures (1) to (m), time t
In Ma 5, all logic 1 becomes RJ for the first time, and it becomes l. Time t3
After the initialization is canceled (the logic at the 0 point is inverted to 1), the initialized circuit 11 works as the original partial cycle circuit, and the 0 point logic is reversed to 1.
The clock at the point is partially divided and outputted to the output terminal 14.

In this embodiment, the number of stages of the shift register in the initialization circuit is two, but any number of stages may be used as long as it is two or more stages.

In addition, as an example of a circuit to be initialized, we used a frequency dividing circuit using a six-stage shift register, but if the output of the initialization circuit becomes a waveform like that shown in Figure 2 (0) due to noise etc., it may not be initialized properly. Any circuit is fine as long as it is suitable.

Effects of the Invention The initialization method of the present invention completely eliminates the possibility that the circuit that initializes jυ1 when the power is turned on is not properly initialized to jυ1 due to noise, etc., and stable initialization can be performed, which is very effective. It is a big thing.

[Brief explanation of drawings]

Fig. 1 is a block diagram for explaining the logic circuit initialization method according to the present invention, Fig. 2 is a diagram showing waveforms of each part of Fig. 1, and Fig. 3 is a diagram explaining the conventional logic circuit initialization method. The block diagram of the system, FIGS. 4 and 6, are waveform diagrams of each part of FIG. 3. 11... Logic circuit to be initialized, 12... First clock pulse input terminal, 13... Initialization terminal, 16... Initialization circuit, 16... ...Second clock pulse input terminal, 17...Buffer, f,, f2. Fl, F2°F3. F4. F5...
...Flip-flop, R1...Resistor, C1...
...Capacitor. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 1 to t+ Ethics deficiency

Claims (1)

[Claims] In a logic circuit in which a shift register composed of two or more stages of flip-flops is connected to the front stage of an initialization terminal of a logic circuit to be initialized, the reset of the shift register is released after the logic circuit to be initialized is initialized. and input two or more pulses to the clock terminal of the shift register,
A method for initializing a logic circuit, comprising canceling initialization of the logic circuit to be initialized.