JPH0128408B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device controlled by a program such as a microcomputer. In particular, the present invention relates to improving the power consumption of a data processing device configured with a complementary field effect transistor (hereinafter referred to as "C-MOS") circuit.

[Conventional technology]

Conventionally, when a data processing device is operated by a battery, low power consumption is a necessary condition, and a battery life of several years is required in applications where it is difficult to replace the battery.

Therefore, in order to reduce the power consumption of data processing equipment, a clock circuit, a means for starting the operation of the clock circuit, and a means for generating a clock signal during a clock period and stopping generation of a clock signal during a non-clock period are required. Therefore, there is a technique for operating the device for a certain period of time and then stopping the operation (Japanese Unexamined Patent Publication No. 149432/1983).
Alternatively, a technique (Japanese Unexamined Patent Application Publication No. 53-111) is provided with a clock control means that stops the supply of a system clock signal, which is frequency-divided and given from an oscillation circuit that generates a basic clock signal, to the calculation means in response to an instruction code decode signal. - Publication No. 68051) has been proposed.

[Problem that the invention seeks to solve]

However, since the first technique described above also operates the device only for the time determined by the clock circuit, it is necessary to control the stoppage of the data processing device under conditions where the operating time differs depending on the data to be processed. However, there was a problem in that the amount of hardware required to perform complex control increased. Furthermore, even with the technology of stopping the supply of the system clock signal using the clock control means, the oscillation circuit and frequency dividing circuit themselves operate even when the calculation means is stopped, so the power consumption can be reduced by that amount. I couldn't.

The present invention solves this problem mentioned above.
The clock signal in the data processing device is controlled to stop at a necessary point by the program, and the clock signal is latched in synchronization with the operating state of the oscillator circuit using the device input, and operation is restarted while maintaining the continuity of the clock signal. Therefore, it is an object of the present invention to provide a data processing device that can change control contents by changing a program, which can suppress unnecessary transition states and efficiently reduce power consumption.

[Means for solving problems]

The present invention comprises a clock signal generation section including an oscillation circuit that generates a reference clock signal, a control section that decodes programmed instructions and outputs a control signal, and a clock signal generation section that synchronizes with the clock signal from the clock signal generation section and controls the clock signal. In a data processing device comprising a data processing section that performs data processing based on a control signal from the control section, a control signal based on a programmed instruction in the control section may be used to control a predetermined circuit including a circuit that is not operated. a control means for selectively stopping the supply of a clock signal; a control means for stopping the supply of the clock signal by stopping the oscillation circuit in response to the control signal; The present invention is characterized in that it comprises latch circuit means for synchronizing the clock signal, and control means for restarting the supply of the clock signal based on the output of the latch circuit means.

[Effect]

The control signal from the control unit that decodes the instructions of the program stored in the memory of the data processing device allows the clock signal from the clock signal generation unit to be supplied only to the display circuit, including circuits that are not operating. Stop.

Further, in order to stop the entire operation of the data processing device, the control section can stop the operation of the oscillation circuit of the clock signal generation section, thereby stopping the operation of the data processing device.

When the operation of the entire data processing device is stopped, when an operation restart input signal, that is, data input, is made to the clock signal generator from outside the device,
Since the oscillation operation is restarted by synchronizing the clock signal of the oscillation circuit, the data processing apparatus can execute instructions while supplying the clock signal to each part of the data processing apparatus and maintaining the continuity of the clock signal.

In this way, the timing at which it can be stopped can be adjusted by the program, and the power consumption of the data processing device can be reduced.

[Principle of the invention]

This will be explained in detail based on the drawings. FIG. 1 is a basic configuration diagram of a C-MOS inversion circuit.
The C-MOS circuit consists of a P-channel field effect transistor 1 (hereinafter referred to as "P-MOS") and an N-channel field effect transistor 2 (hereinafter referred to as "M-MOS").
It's called MOS. ) are connected in a complementary manner. When the input voltage V _IN is at ground level (hereinafter referred to as "0" level), P-MOS1 is on and N-MOS2 is on.
is off and the output voltage V _OUT is at the power supply level (hereinafter referred to as "1").
It's called a level. ). Input voltage V _IN is “1”
When it is at the level, P-MOS1 is off, N-MOS2 is on, and the output voltage V _OUT is at the "0" level, forming an inverting circuit. In this way, in a C-MOS circuit, P
-MOS and N-MOS are connected complementary, and
Various logic circuits such as OR are realized, and a data processing device is configured by a combination of the logic circuits.

FIG. 2 is a diagram showing the input/output characteristics of the above-mentioned inversion circuit. In the steady state of the C-MOS circuit, P
-MOS1 and N-MOS2 are not both in the on state; one of them is in the off state, so no current flows. Current that charges and discharges the load capacitance such as the output capacitance, wiring capacitance, and input capacitance of the circuit in a transition state where the input and output voltages change from the “0” level to the “1” level or from the “1” level to the “0” level. flows. Furthermore, in this transition state, both P-MOS1 and N-MOS2 may be turned on, and current flows here as well. The current in this transition state accounts for most of the power consumption of the C-MOS circuit. In conventional devices, this transition state occurs throughout the device, resulting in large power consumption.

〔Example〕

FIG. 3 is a configuration diagram of one embodiment of the present invention. Reference numeral 3 denotes a clock signal generating section, which generates a reference clock signal using an internal oscillation circuit, controls this signal, and supplies clock signals CK ₁ and CK ₂ to each part of the apparatus. A device input signal i for controlling clock signals CK ₁ and CK ₂ is connected to this clock signal generating section 3 .

The part surrounded by the dotted line in FIG. 3 is the data processing unit 5.
It is. This data processing unit 5 includes a processing procedure, that is, a program memory 6 for storing programs, a program counter 7 for specifying the address of the program memory 6, a data memory 8 for storing data to be processed, and data specifying the address of the data memory 8. A pointer 9, an accumulator 10 that serves as a central register for data processing, a processing circuit 11 that performs calculations and judgments, an input circuit 12 that processes the input signal i from outside the device, and an output circuit that processes the output signal O to the outside of the device. 13, and a data bus 14 for transferring data between each circuit.

15 is a control unit, which stores a program memory 6 addressed by the program counter 7;
Deciphers the output command e and sends control signals to each part of the device.
It is for generating C ₁ to _Co. The control signals C ₁ and C ₂ are connected to the clock signal generator 3.

16 is a display section, and the clock signal CK ₂
It operates in synchronization with the data memory 8, receives display data f from the data memory 8, and outputs a liquid crystal display time division drive signal d to a low power consumption liquid crystal display element.

In such a configuration, the power consumption reduction operation by clock control, which is a feature of the present invention, will be explained.

First, when the control signals C ₁ and C ₂ from the control section 15 are both at the "1" level, the oscillation circuit in the clock signal generation section 3 operates, and the reference clock signal and the clock signals CK ₁ and CK ₂ are generated. (hereinafter referred to as the "first state") will be explained. In the first state, all circuits of the data processing device operate in synchronization with changes in the clock signals CK ₁ and CK ₂ , and most of the circuits of the
When a signal changes in a MOS circuit, a current flows in a transition state. The power consumed in this first state is the maximum value for the operation of the data processing device. In this embodiment, the power supply current is several hundred μA (microamperes).

Next, the control signal C ₂ from the control unit 15 is “0”
A state (hereinafter referred to as "second state") in which only the supply of the clock signal _CK1 is stopped in the clock signal generator 3 and the reference clock signal and the clock signal _CK2 are generated at this level will be described. In this second state, the supply of the clock signal CK ₁ is stopped, so the data processing section 5 and the control section 15 stop their respective circuit operations, suppressing data changes, and the C-MOS circuit in that part stops. It is in a steady state and no current flows. Reference clock signal and clock signal
In synchronization with the change in _CK2 , the clock signal generating section 3 and the C-MOS circuit of the display section 16 operate, and a current flows in a transition state. Therefore, the power consumption of the data processing device in this second state is the power consumption by the clock signal generator 16. The power consumption in this second state is reduced from the power consumption in the first state in proportion to the amount of operating circuits. In this embodiment, the number of gates in the clock generating section 3 and the display section 16 is about 1/10 of that of the entire data processing device, and the power supply current is also about 1/10, about 10 μA.

This second state realizes only the function of display,
When no other calculations or processing are performed, the control signal C ₁ is activated by executing the programmed stop command 1 in a state intended to reduce power consumption.
The level becomes "0" and the second state is set.

Next, the control signal C ₂ from the control unit 15 is “0”
level, and in the clock signal generator 3,
A state in which the oscillation circuit stops and the reference clock signal and clock signals _CK1 and _CK2 stop (hereinafter referred to as the "third state") will be described. In this third state, since there is no change in the clock signal, the C-MOS circuit of the data processing device is in a steady state and no current flows. In this third state, the operation of the data processing device is stopped, but the data storage function of the data memory 8 is maintained, and the lowest power consumption is achieved. The power consumption in this third state is the minimum value for the operation of the data processing device. In this embodiment, the power supply is less than 1 μA, which is close to the self-discharge of a battery. This third state is set by executing the programmed stop command 2 so that the control signal _C2 becomes the "0" level. When it becomes necessary to operate the data processing apparatus from the second or third state, the apparatus input signal i is input to the clock signal generator 3, and the first state is set by this activation signal.

As described above, in the data processing apparatus according to the present invention, when a necessary process is completed, the second or third state is set by the program, and when a new process is required, the first state is set by a start signal. As a result, overall power consumption can be reduced by selecting a desired state and performing intermittent operation according to the functions required of the data processing device.

Here, a specific example of the clock generating section 3 will be shown and explained in more detail. FIG. 4 is a circuit diagram of the clock signal generating section 3 according to the first embodiment of the present invention. This example is a clock signal generating section that uses an oscillation circuit whose oscillation frequency is determined by the time constant of a capacitor and a resistor. Other oscillation circuits include LC oscillation and oscillation using a resonant element such as a crystal resonator, and various circuit connections are available.

Reference numeral 20 denotes an oscillation circuit, which is composed of inverting circuits 21 to 23, a capacitor 24, a resistor 25, and an AND circuit 26 as shown in the figure.An oscillation effect is caused by positive feedback by the capacitor 24 and negative feedback by the resistor 25, and the capacitor 24 and The oscillation frequency is controlled by the value of the resistor 25. _a1 to _a3 are frequency control input/output signals that control the oscillation frequency. .

i ₁ -i ₃ are device input signals for clock control and correspond to signal i in FIG. The device input signals i ₁ to _{i 3} are input to an OR circuit 29 . The output of this OR circuit 29 is connected to a latch circuit 30. This latch circuit 30 is connected to the OR circuit 2
This circuit synchronizes the output signal of 9 with the basic clock signal, and includes an inverting circuit 31, AND circuits 32, 33,
The OR circuit 34 is configured as shown in the figure. The output of this latch circuit 30 is OR circuit 36, 37.
are connected to each. Also, OR circuit 3
Control signals C ₁ and C ₂ from the control unit 15 are connected to the other inputs of 6 and 37, respectively. The output of this OR circuit 37 is connected to the input of the AND circuit 26. The output of the OR circuit 36 is
It is connected to the input of the AND circuit 38. The output of the OR circuit 36 and the other input of the AND circuit 38 are connected to the output of the inverting circuit 22.
CK ₁ and CK ₂ in FIG. 4 are clock signals.

FIG. 5 is an operation time chart showing the signal waveform diagram at the points indicated by the x marks in FIG. In Figure 5,
X ₁ represents stop command 1, X ₂ and X ₄ represent device input signals, and X ₃ represents stop command 2, respectively.

With such a configuration, the AND circuit 26 connects the resistor 25
The output signal of the OR circuit 37 controls the oscillation operation of the oscillation circuit 20. Further, the output of the inverting circuit 22 is output from the clock signal generating section 3.
It is also the clock signal _CK2 to the display section 16. The OR circuit 36 and the AND circuit 38 are circuits that control the clock signal _CK1 to the data processing section 5, and are connected to the latch circuit 30 or the control signal.
A clock signal _CK1 is supplied to the data section ₅ when any one of the clock signals C1 is at the "1" level. here,
The control signal C ₁ from the control unit 15 becomes "0" level when the program stop command 1 is executed, and the control signal C ₂ becomes "0" level when the program stop command 2 is executed. In execution, the level is "1".

Now, the data processing device is issuing a stop command 1 and a stop command 2.
When executing other operations, the control signals C ₁ and C ₂ are at the "1" level, the outputs of the OR circuits 36 and 37 are at the "1" level, the AND circuit 26 outputs the signal from the inverting circuit 23, and the output from the resistor 25 is Negative feedback is performed and the oscillation circuit 20 oscillates. Also, AND circuit 3
8 outputs the signal of the inverting circuit 22 and outputs the clock signal.
CK ₁ and CK ₂ are supplied to each part of the data processing device to perform processing operations. This is the first state shown in FIG.

From the time the data processing device executes the stop command 1, the clock control signal _C1 becomes the "0" level,
When the latch circuit 30 is also at the "0" level, the output of the OR circuit 36 is at the "0" level, and even when the signal from the inverting circuit 22 is input to the AND circuit 38, the output is at the "0" level. Therefore, the clock signal _CK1 is not supplied, and the data processing section 5 that operates in synchronization with it is not supplied with the clock signal CK1.
stops working. On the other hand, the clock control signal C ₂
is supplied. This is the second state shown in FIG.

When a "1" level is input to any of the device input signals _i1 to _i3 , the OR circuit 29 outputs a "1" level. This output is input to an AND circuit 32. Here, the other input of this AND circuit 32 is the reference clock signal "0" from the inverting circuit 22.
level, the inverted input "1" level is input,
The output of this AND circuit 32 is at the "1" level. This reference clock signal "0" level is also input to the AND circuit 33. The outputs of the AND circuits 32 and 33 are input to the OR circuit 34 and
4 outputs a "1" level. Therefore, the output of the latch circuit 30 is at the "1" level when the reference clock signal is at the "0" level. The "1" level of the latch circuit 30 is input to the OR circuit 36. At this time, the other input of the OR circuit 36 is set to "0" of the control signal _C1 by executing the stop command 1.
The level is entered. Therefore, OR circuit 3
6 outputs a “1” level, and this output is given to the input of the AND circuit 38. The AND circuit 38 is
The signal from the inverting circuit 22 is output, and the clock signal _CK1 , which was stopped in FIG. 5, is again supplied to the data processing section 5. This is shown in FIG. 5 and is in the first state. In this first state, clock signals CK ₁ and CK ₂ are supplied to various parts of the data processing device and other instructions of the program are executed. At this time, the control signal _C1, which had been at the "0" level due to the execution of the stop command 1, becomes the "1" level.

From the time the data processing device executes the stop command 2, the control signal _C2 becomes the "0" level. At this time, there is no output from the OR circuit 39 and the latch circuit 30 is at the "0" level, the output of the OR circuit 37 is at the "0" level, the output signal of the inverting circuit 23 is inhibited by the AND circuit 26, and the resistor 25 The negative feedback is no longer applied and oscillation stops. As the oscillation is stopped, the output of the inverting circuit 22, which is the reference clock signal, becomes the "0" level, and the clock signals CK ₁ and CK ₂ to each part of the data processing apparatus remain at the "0" level and do not change. This is the third state shown in FIG. 5, and each part of the data processing device stops operating.

Next, set "1" to any of the device input signals i ₁ to i ₃ .
When the level is input, the output of the OR circuit 29 becomes the "1" level. “1” of this OR circuit 29
The level is input to an AND circuit 32, and the other input of this AND circuit 32 is a reference clock signal "0".
Level inversion input "1" level is input. Therefore, the AND circuit 32 outputs a "1" level. Further, the reference clock signal is at the "0" level, and the AND circuit 33 to which it is input becomes the "0" level. The OR circuit 34 to which the outputs of the AND circuits 32 and 33 are input outputs the "1" level, and the output of the latch circuit 30 also becomes the "1" level.

The "1" level of the latch circuit 30 is input to the OR circuit 37, and the OR circuit 37 outputs the "1" level. The "1" level of this OR circuit 37 is
The signal is input to an AND circuit 26, and the AND circuit 26 outputs the signal from the inversion circuit 23. The output of the inverting circuit 23 causes negative feedback to be applied by the resistor 25 to restart the oscillation operation. Due to this oscillation operation, clock signals CK ₁ and CK ₂ are supplied to various parts of the data processing device, and execution of other instructions begins. At this time, the control signal _C2, which had been at the "0" level due to the execution of the stop command 2, becomes the "1" level. This is Figure 5 V
This is the first state.

The latch circuit 30 receives asynchronous device input signals _i1 to _i3.
This circuit synchronizes the oscillation circuit 20 and ensures continuity of the pulse width of the clock signal at the time of restarting the oscillation of the oscillation circuit 20 and restarting the supply of the stopped clock signals CK ₁ to CK ₂ . By doing so, it becomes possible to control the clock signal without impairing the functions of various parts such as data storage in the data memory.

A case will be described in which the present invention is applied to an electronic water meter. In this example, an electronic water meter uses a magnetic sensor to convert the movement of an impeller that rotates in proportion to the flow rate of water into an electrical signal, and a data processing device according to the present invention converts the number of revolutions into a flow rate of water and integrates it. do. Also, when reading the meter, the memorized cumulative amount of water is digitally displayed on the liquid crystal display.

The data processing device is normally in state 3, the power consumption is minimal and the power supply current is less than 1 μA. The first state is reached by the rotation signal from the sensor, and the flow rate is converted.
Performs integration data processing. The time for this process is
The power supply current is about 600 μA at about 0.5 mS (millisecond). When the processing is completed, the data processing device executes the stop command 2 and enters the third state. This flow rate calculation is performed 10 to 20 times per second when water is being used, and when the user is sleeping, water is not used much and the data processing device is mostly in the third state. The cumulative amount of water is stored in the data memory, so when reading the meter, when a display start signal is given from a key switch, etc., the first
The integrated water amount data stored in the data memory is segment decoded and converted into display data. After that, the stop command 1 is executed and the second state is entered. In the second state, a liquid crystal display time division drive signal corresponding to display data is output. The power supply current at this time is about 60 μA. The data processing device changes from the first state to the third state by the stop command 2 in response to the display end signal when the meter reading ends.
This meter reading is done once a month and takes about 1 minute.

As described above, the data processing device according to the present invention controls the state of the clock signal using commands and external signals, thereby achieving the minimum power consumption while realizing the required functions.

In the example of an electronic water meter, the annual power consumption is about 20 mAh (milliampere hour), and if a battery with a current capacity of 200 mAh is used, it can operate for 10 years. When a conventional data processing device is operated with the same battery, the clock state cannot be controlled as in the present invention, so the battery life is about 300 hours in continuous operation in the first state, making it difficult to replace the battery. Application to this becomes possible for the first time with the present invention. The data processing device according to the present invention is capable of controlling clock signals and power consumption states using a program, and even if the device to which it is applied changes, by changing the program, the functions and power consumption required by that device can be adjusted. realizable.

In this embodiment, two clock signals are controlled by two stop commands and three device input signals, and in the example of an electronic water meter, a rotation signal from a sensor, a display start signal for meter reading, The end of display signal controls the clock state as a device input signal. In the embodiment, two controlled clock signals are supplied to the data processing section and the display section to control the clock states and reduce power consumption. The present invention can be realized by combining circuits of various parts within the data processing device, in addition to the data processing part and display part of the embodiments, as destinations to which the controlled clock signal is supplied, such as input/output circuits and other parts. It is possible.

〔Effect of the invention〕

According to the present invention, as described above, there is provided a clock signal generating section that includes an oscillation circuit that generates a reference clock signal, a control section that decodes a programmed command and outputs a control signal, and a clock signal generating section that generates a reference clock signal. In a data processing device, the clock signal generation section including the oscillator is controlled by the control signal from the control section, and the data processing section performs data processing based on the control signal from the control section in synchronization with a clock signal from the control section. We decided to synchronize the clock signals and maintain their continuity while supplying the clock signals only to the data processing units necessary for data processing.

Therefore, it is possible to reduce power consumption in areas where data processing is not performed. Furthermore, since power consumption can be reduced, it is possible to apply the present invention to devices in which battery replacement is difficult. In particular, in data processing devices whose operating times vary depending on the data being processed, arithmetic control is possible by synchronizing the clock signal every time data is input and maintaining its continuity, while freely setting the operating time corresponding to the data. Therefore, it can be applied to equipment that uses a data processing device that requires complex control. Furthermore, by changing the program, even if the device to which it is applied changes, it is possible to achieve efficient power consumption while still performing the functions required by the device.

[Brief explanation of drawings]

Fig. 1 is a basic configuration diagram of a C-MOS inversion circuit, and Fig. 2 is an input/output characteristic diagram of the above configuration diagram. FIG. 3 is a configuration diagram of one embodiment of the present invention. FIG. 4 is a configuration diagram of the clock signal generating section of the above example. FIG. 5 is an operation time chart of the above configuration diagram. 1...P channel type field effect transistor,
2...N-channel field effect transistor, 3
...clock signal generation section, 5...data processing section,
6...Program memory, 7...Program counter, 8...Data memory, 10...Accumulator, 15...Control section, 16...Display section, 2
0...Oscillation circuit, 21-23, 31...Inverting circuit, 24...Capacitor, 25...Resistor, 26,
32, 33, 38...AND circuit, 29, 34,
36, 37...OR circuit, 30...Latch circuit.

Claims (1)

[Claims] 1. A clock signal generation section including an oscillation circuit for generating a reference clock signal, a control section that decodes programmed commands and outputs a control signal, and a first half control section that is synchronized with the clock signal from the clock signal generation section. a data processing unit that performs data processing based on a control signal from the controller; control means for selectively stopping the supply of the signal; control means for stopping the generation of the reference clock signal by stopping the oscillation circuit in response to the control signal; A data processing device comprising latch circuit means for synchronizing the clock signal with the oscillation state as a gate signal, and control means for restarting the supply of the clock signal and the oscillation operation of the oscillation circuit by the output of the latch circuit means. .