JP3040635B2 - Clock generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit using a phase locked loop circuit (PLL circuit).

[0002]

2. Description of the Related Art When the operating frequency of an integrated circuit typified by a microprocessor or a microcontroller exceeds 40 MHz, the delay of the internal clock signal with respect to the external clock signal due to the delay of the clock driver inside the integrated circuit ( = Clock skew) is an important issue. Further, from the viewpoint of system design, it is desired to improve the performance by increasing only the frequency of the internal clock signal without increasing the frequency of the external clock signal. In order to satisfy these problems and requirements, a clock generation circuit using a PLL circuit has been used in an integrated circuit.

FIG. 12 shows a conventional example of a clock generation circuit using a PLL circuit. Here, an example of a clock generation circuit that generates an internal clock signal having a frequency twice the frequency of the external clock signal is shown. The phase difference detection circuit 10 receives a reference clock signal 4 supplied from the outside.
The phase of 0 is compared with the phase of the feedback clock signal 32 obtained by dividing the internal clock signal 34 having twice the frequency thereof by half. A signal corresponding to the phase difference is supplied to the charge pump circuit 1
The signal is sent to the loop filter circuit 14 via the line 2 and converted into a voltage value according to the phase difference. This voltage is applied to the voltage controlled oscillator 16
A signal having a frequency four times as high as that of the reference clock signal 40 is generated as a control voltage of the reference clock signal 40, and the oscillation output of the voltage controlled oscillator 16 is converted by the first frequency divider 18 into a duty ratio 50 %, And drives the load circuit via the clock driver 21. The internal clock signal 34, which is the output signal of the clock driver 21,
The frequency divider 24 further divides the frequency by a factor of 2 to become a feedback clock signal 32.

A PLL circuit having the above-described circuit configuration generates an internal clock signal 34 having a frequency twice as high as that of the reference clock signal 40, and matches the phases of the reference clock signal 40 and the internal clock signal 34 Let me
Its clock skew is minimized. An implementation example of such a clock generation circuit is described in IA Young et al., "A PLL
Clock Generator with 5 to 110MHz Lock Range for Mi
croprocessors ", ISSCCDigest of Technical Papers, pp.
50-51, Feb. 1992.

[0005]

In the above-mentioned conventional configuration, clocking of the internal clock signal 34 cannot be started from a specific phase or the clocking cannot be temporarily stopped at a specific phase. There was a problem.

For example, when the supply of the reference clock signal 40 to the PLL circuit is started, a time (= lock-in time) until the internal clock signal 34 is synchronized with the reference clock signal 40 is required. The internal clock signal 34 not synchronized with the clock signal 40 is supplied to each load circuit inside the integrated circuit.

The internal clock signal 34 to the load circuit
When the supply of the reference clock signal 40 to the PLL circuit is stopped in order to temporarily stop the supply of
Cannot operate normally, and the entire PLL circuit loses the phase-locked (= locked) state. For this reason, the internal clock signal 34 not synchronized with the reference clock signal 40 is temporarily supplied to the load circuit. If clocking is subsequently resumed, a lock-in time is required again, during which time the internal clock signal 34 not synchronized with the reference clock signal 40 is supplied to the load circuit. Further, it is impossible to immediately restart the supply of the internal clock signal 34 to the load circuit from the cycle immediately after the supply of the reference clock signal 40 is stopped.

[0008] Pausing the internal clock signal 34 at a specific phase or restarting the clocking from a specific phase can be performed by step execution at the time of debugging hardware or software of a system using an integrated circuit. This technology is required to pause / resume operation,
This technique is also necessary for controlling the clock signal when managing the power consumption of the system or the integrated circuit itself. However, because of the existence of the lock-in time described above, it is not possible to know the timing at which clocking is actually started / restarted from outside the integrated circuit. It was difficult to determine.

An object of the present invention is to provide a clock generating circuit having the functions of starting clocking from a specific phase of an internal clock signal, temporarily stopping clocking at a specific phase, and resuming clocking from a specific phase. Is to make it happen. Another object of the present invention is to realize a function of automatically releasing an asserted internal reset signal at an appropriate timing according to clocking of an internal clock signal.

[0010]

In order to achieve the above object, the present invention employs a configuration provided with means for controlling timing for transmitting a primitive clock signal generated by a PLL circuit as an internal clock signal. It was done.
Further, means for automatically releasing the assertion of the internal reset signal after the start of the supply of the internal clock signal is further provided.

More specifically, the invention of claim 1 is:
As shown in FIGS. 1 and 8, in a clock generation circuit for supplying an internal clock signal 34 synchronized with a reference clock signal 40 to a load circuit, a source clock signal 30 having an integral multiple frequency of the reference clock signal 40 is used. The PLL circuit 1 for adjusting the phase of the generated source clock signal 30 so that the generated source clock signal 30 is synchronized with the reference clock signal 40 and the supply of the internal clock signal 34 to the load circuit are controlled. The clock buffer circuit 5 interposed between the PLL circuit 1 and the load circuit
Until the source clock signal 30 output from the LL circuit 1 is synchronized with the reference clock signal 40, the clock buffer circuit 5 does not supply the internal clock signal 34 to the load circuit, and the source clock signal 30 Clock signal supply start control means 2 for controlling the clock buffer circuit 5 so that the clock buffer circuit 5 starts supplying the internal clock signal 34 to the load circuit in synchronization with the reference clock signal 40
3 (2a, 2b, 3) and a clock buffer such that when the clock stop request signal 42 is asserted, the clock buffer circuit 5 stops supplying the internal clock signal 34 to the load circuit in synchronization with the reference clock signal 40. A configuration including a clock signal supply stop control means 4 for controlling the circuit 5 is adopted.

According to a second aspect of the present invention, in the clock generation circuit according to the first aspect of the present invention, when the phase of the feedback clock signal 32 is advanced with respect to the reference clock signal 40, the phase of the PLL circuit 1 is advanced. A phase difference detection circuit 10 for outputting a phase delay signal when the signal is delayed, and a voltage of an output signal according to the phase advance signal and the phase delay signal output from the phase difference detection circuit 10. A charge pump circuit 12 for adjustment, a loop filter circuit 14 for outputting a control voltage by passing a low frequency component of an output signal of the charge pump circuit 12, and an output signal from the loop filter circuit 14. A voltage controlled oscillator 16 for generating a source clock signal 30 having a frequency corresponding to the control voltage
And a frequency divider 24 for supplying a signal having a frequency obtained by dividing the source clock signal 30 generated by the step 6 to the phase difference detection circuit 10 as a feedback clock signal 32.

According to the third aspect of the present invention, as shown in FIGS.
As described above, in the clock generation circuit according to the first aspect of the present invention,
Supply of the internal clock signal 34 to the load circuit starts.
Of the internal reset signal 80 to the load circuit after the
Reset control means 6, 55 for releasing the
I decided to prepare.

According to a fourth aspect of the present invention, there is provided the method according to the third aspect.
The reset control means.
Sets a predetermined pulse of the internal clock signal 34 to the load circuit.
Reset signal 8 to the load circuit when counting
Outputs count completion signal 61 to release assertion of 0
And a counter circuit 51 for performing the operation.

According to a fifth aspect of the present invention, in accordance with the third aspect of the present invention,
Reset control means in the clock generation circuit
Counter circuit 51 is input to the PLL circuit 1.
The pulses of the reference clock signal 40 are counted.

According to a sixth aspect of the present invention, there is provided a clock generating circuit for supplying an internal clock signal 34 synchronized with a reference clock signal 40 to a load circuit, as shown in FIGS. PLL for generating a source clock signal 30 having a double frequency and adjusting the phase of the source clock signal 30 so that the generated source clock signal 30 is synchronized with the reference clock signal 40
Circuit 1, a clock buffer circuit 5 interposed between the PLL circuit 1 and the load circuit so as to control the supply of the internal clock signal 34 to the load circuit, and a primitive clock signal 30 output from the PLL circuit 1 as a reference. The clock buffer circuit 5 does not supply the internal clock signal 34 to the load circuit until the clock signal 40 is synchronized with the clock signal 40, and when the original clock signal 30 is synchronized with the reference clock signal 40, the clock buffer circuit 5 Signal supply start control means 2, 3 (2a, 2b, 3) for controlling the clock buffer circuit 5 so as to start supplying the internal clock signal 34 to the load circuit in synchronization with
Are adopted. Moreover, the P
The LL circuit 1 includes a phase difference detection circuit 10 for outputting a phase advance signal when the phase of the feedback clock signal 32 is advanced with respect to the reference clock signal 40 and outputting a phase delay signal when the phase is delayed. And a charge pump circuit 12 for adjusting the voltage of the output signal according to the phase advance signal and the phase delay signal output from the phase difference detection circuit 10.
A loop filter circuit 14 for outputting a control voltage by passing a low frequency component of an output signal of the charge pump circuit 12; and a loop filter circuit 14 having a frequency corresponding to the control voltage output from the loop filter circuit 14. A voltage controlled oscillator 16 for generating a primitive clock signal 30,
A frequency divider 24 for supplying a signal having a frequency obtained by dividing the original clock signal 30 generated by the voltage controlled oscillator 16 to the phase difference detection circuit 10 as a feedback clock signal 32; The source clock signal 30 generated by the voltage controlled oscillator 16 is delayed so that the phase difference between the clock signal 30 and the internal clock signal 34 based on the delay in the clock buffer circuit 5 becomes equal to the phase difference between the source clock signal 30 and the internal clock signal 34. And a delay circuit 22 for this purpose.

A seventh aspect of the present invention is a clock generating circuit for supplying an internal clock signal 34 synchronized with a reference clock signal 40 to a plurality of load circuits, as shown in FIGS. A PLL circuit 1 for generating a source clock signal 30 having a frequency that is an integral multiple of the same and adjusting the phase of the source clock signal 30 so that the generated source clock signal 30 is synchronized with the reference clock signal 40; Supply of the internal clock signal 34 to each of the load circuits is arranged between the PLL circuit 1 and a plurality of load circuits in the vicinity of each load circuit, and the supply of the original clock signal 30 from each of the PLL circuits 1 is controlled. The source clock signal 30 output from the plurality of clock buffer circuits 5 and the PLL circuit 1 is synchronized with the reference clock signal 40. In the meantime, each of the plurality of clock buffer circuits 5 does not supply the internal clock signal 34 to each load circuit, and when the original clock signal 30 is synchronized with the reference clock signal 40, each of the plurality of clock buffer circuits 5 Clock signal supply start control means 2, 3 (2a, 2b, 3) for controlling the plurality of clock buffer circuits 5 so as to start supplying the internal clock signal 34 to each load circuit in synchronization with the clock signal 40. Are adopted. Moreover, the PLL
The circuit 1 outputs a phase advance signal when the phase of the feedback clock signal 32 is advanced with respect to the reference clock signal 40,
A phase difference detection circuit 10 for outputting each of the phase delay signals when the signals are delayed, and a voltage for adjusting the output signal according to the phase advance signal and the phase delay signal output from the phase difference detection circuit 10 A charge pump circuit 12, a loop filter circuit 14 for outputting a control voltage by passing a low frequency component of an output signal of the charge pump circuit 12, and a control voltage output from the loop filter circuit 14. A voltage-controlled oscillator 16 for generating a source clock signal 30 having a frequency corresponding to the frequency, and a source clock signal 30 generated by the voltage-controlled oscillator 16
The signal having the frequency obtained by dividing the frequency
Divider 2 for supplying as feedback clock signal 32 to
4 and a clock driver 21 for driving a signal line based on the output of the voltage controlled oscillator 16 so as to supply the primitive clock signal 30 to each of the plurality of clock buffer circuits 5.

According to an eighth aspect of the present invention, there is provided a clock generating circuit for supplying an internal clock signal 34 synchronized with a reference clock signal 40 to a load circuit, as shown in FIG.
A PLL circuit for generating a source clock signal 30 having a frequency that is an integral multiple of the reference clock signal 40 and adjusting the phase of the source clock signal 30 so that the generated source clock signal 30 is synchronized with the reference clock signal 40 1
And a primitive clock signal 30 output from the PLL circuit 1.
AND circuit 52, which receives the reference clock signal 40 as one input, such that it measures a predetermined time sufficient to synchronize with the reference clock signal 40;
And a counter circuit 50 for outputting a count completion signal 60 when the predetermined number of output signal pulses are counted. The count completion signal 60 output from the counter circuit 50 is the other input of the AND circuit 52. , A clock buffer circuit 5 interposed between the PLL circuit 1 and the load circuit to control the supply of the internal clock signal 34 to the load circuit, and a count completion signal 60 from the counter circuit 50. Is not output so that the clock buffer circuit 5 does not supply the internal clock signal 34 to the load circuit, and when the count completion signal 60 is output, the clock buffer circuit 5 A start control circuit 3 for controlling the clock buffer circuit 5 to start supplying the clock signal 34; Internal clock signal to the load circuit clock buffer circuit 5 is synchronized with the reference clock signal 40 when the lock stop request signal 42 is asserted 34
The clock buffer circuit 5 is controlled so as to stop the supply of the clock signal. When the assertion of the clock stop request signal 42 is released, the clock buffer circuit 5
And a stop control circuit 4 for controlling the clock buffer circuit 5 so as to immediately restart the supply of the internal clock signal 34 to the load circuit using the held count completion signal 60 from Is adopted. Moreover, the PLL circuit 1
Is the feedback clock signal 3 with respect to the reference clock signal 40.
A phase difference detection circuit 10 for outputting a phase advance signal when the phase 2 is advanced, and a phase delay signal when the phase 2 is late, and a phase advance signal output from the phase difference detection circuit 10 A charge pump circuit for adjusting a voltage of an output signal according to a phase delay signal, and a loop filter for outputting a control voltage by passing a low frequency component of the output signal of the charge pump circuit Circuit 14 and a primitive clock signal 30 having a frequency corresponding to the control voltage output from the loop filter circuit 14.
And a signal for supplying a signal having a frequency obtained by dividing the original clock signal 30 generated by the voltage controlled oscillator 16 to the phase difference detection circuit 10 as a feedback clock signal 32. And a circulator 24.

The ninth aspect of the present invention is based on FIG.
The internal clock signal 34 synchronized with the quasi-clock signal 40 is
In a clock generation circuit for supplying to a load circuit,
A primitive clock having a frequency that is an integral multiple of the reference clock signal 40
Clock signal 30 and the generated primitive clock signal.
So that the signal 30 is synchronized with the reference clock signal 40.
PLL circuit 1 for adjusting the phase of lock signal 30
And a primitive clock signal 3 output from the PLL circuit 1.
0 is the reference clock signal 40 input to the PLL circuit 1.
Synchronization detecting means 2a, 2 for detecting the synchronization with
b, and synchronization is detected by the synchronization detecting means 2a, 2b.
During this period, the primitive clock signal output from the PLL circuit 1
No. 30 to the load circuit as an internal clock signal 34.
To control the transmission of the primitive clock signal 30
And a clock signal transmission control means 3-5.
It was used. Moreover, the PLL circuit 1
Phase of feedback clock signal 32 with respect to clock signal 40
If the signal is ahead, the phase advance signal
First phase difference detection for outputting a phase delay signal
Output circuit 10 and the output from the first phase difference detection circuit 10.
Output signal according to the phase advance signal and phase delay signal
A charge pump circuit 12 for adjusting a voltage ;
Low frequency component of the output signal of the charge pump circuit 12
To output the control voltage by passing
From the filter circuit 14 and the loop filter circuit 14
A primitive clock signal with a frequency corresponding to the output control voltage
A voltage controlled oscillator 16 for generating the voltage controlled oscillator 30;
The primitive clock signal 30 generated by the control oscillator 16 is
A signal having a frequency divided by a first phase difference detection circuit 10
Divider 2 for supplying as feedback clock signal 32 to
4 is provided. Further, the synchronization detecting means includes:
The signal is input to the first phase difference detection circuit 10 in the PLL circuit 1.
Of the reference clock signal 40 and the feedback clock signal 32
Clock signal transmission when it is determined that the phase difference has disappeared
The control means 3 to 5 supply the internal clock signal 34 to the load circuit.
The synchronization detection signal 98 is output so as to start the supply.
And phase difference detecting means 2a and 2b. Change
The phase difference detection means compares the phase of the reference clock signal 40 and the phase of the feedback clock signal 32 input to the first phase difference detection circuit 10 in the PLL circuit 1, and provides feedback to the reference clock signal 40. A second phase difference detection circuit 11 for outputting a phase advance signal 90 as a phase difference detection signal when the phase of the clock signal 32 is advanced, and a phase delay signal 91 when the phase of the clock signal 32 is delayed; When the state in which the second phase difference detection circuit 11 does not output the phase difference detection signals 90 and 91 continues over a period of a plurality of pulses of the reference clock signal 40, the second phase difference detection circuit 11 outputs the synchronization detection signal 98 and outputs the output synchronization detection signal 98 , And the second phase difference detection circuit 11 is set to have lower phase difference detection accuracy than the first phase difference detection circuit 10.

According to a tenth aspect of the present invention, in the clock generating circuit according to the ninth aspect of the present invention, the clock signal transmission control means controls the supply of the internal clock signal 34 to the load circuit with the PLL circuit 1 and the load. A clock buffer circuit 5 interposed between the clock buffer circuit 5 and the phase difference detecting means 2a,
2b, the clock buffer circuit 5 does not supply the internal clock signal 34 to the load circuit while the synchronization detection signal 98 is not output, and the clock buffer circuit 5 synchronizes with the reference clock signal 40 when the synchronization detection signal 98 is output. A start control circuit 3 for controlling the clock buffer circuit 5 so as to start supplying the internal clock signal 34 to the load circuit, and when the clock stop request signal 42 is asserted, the clock buffer circuit 5 The clock buffer circuit 5 stops the supply of the internal clock signal 34 to the load circuit in synchronization with
And when the clock stop request signal 42 is deasserted, the clock buffer circuit 5 uses the held synchronization detection signal 98 from the synchronization confirmation means 2b and synchronizes with the reference clock signal 40 to internal the load circuit. A stop control circuit 4 for controlling the clock buffer circuit 5 so as to immediately restart the supply of the clock signal 34 is provided.

[0021]

According to the first and second aspects of the present invention, the PLL circuit 1
Until the source clock signal 30 output from the source clock signal is synchronized with the reference clock signal 40, the propagation of the source clock signal 30 is prevented. As a result, the internal clock signal 34 not synchronized with the reference clock signal 40 It will not be supplied. When the primitive clock signal 30 synchronizes with the reference clock signal 40, the clock buffer circuit 5 interposed between the PLL circuit 1 and the load circuit synchronizes the internal clock signal 34 to the load circuit with the reference clock signal 40. Is controlled so as to start supply. Thereby, clocking start and restart from a specific phase of the internal clock signal 34 can be realized. Further, when the clock stop request signal 42 is asserted, the clock buffer circuit 5 is controlled to stop supplying the internal clock signal 34 to the load circuit in synchronization with the reference clock signal 40. Thereby, clocking suspension at a specific phase of the internal clock signal 34 can be realized.

According to the third aspect of the present invention, the load circuit
After the supply of the external clock signal 34 is started, the load circuit
Assertion of the internal reset signal 80 to the road is automatically released
Is done. By such automation, the internal clock signal 3
Timing when clocking of 4 actually starts / resumes
It does not matter if you can not know from outside. this is,
Only when the internal clock signal 34 is correctly supplied
Load circuit that correctly receives the
It is convenient.

According to the fourth aspect of the present invention, the internal reset signal
No. 80 is released from the internal clock signal
The internal clock, as determined by the pulse count of 34
Assertion of internal reset signal 80 after start of supply of signal 34
Release is guaranteed.

According to the fifth aspect of the present invention, the internal reset signal
The timing of deassertion of signal 80 is, for example,
Lock-in of PLL circuit required by simulation
Pulse count of the reference clock signal 40 in consideration of time
Is determined by

According to the sixth aspect of the present invention, the propagation of the source clock signal 30 is prevented until the source clock signal 30 output from the PLL circuit 1 is synchronized with the reference clock signal 40, so that the reference clock signal The internal clock signal 34 not synchronized with 40 is not supplied to the load circuit. When the primitive clock signal 30 synchronizes with the reference clock signal 40, the clock buffer circuit 5 interposed between the PLL circuit 1 and the load circuit synchronizes the internal clock signal 34 to the load circuit with the reference clock signal 40. Is controlled so as to start supply. Thereby, clocking start and restart from a specific phase of the internal clock signal 34 can be realized. Moreover, the PLL circuit 1
By providing the delay circuit 22 therein, the clock skew of the internal clock signal 34 with respect to the reference clock signal 40 is eliminated.

According to the seventh aspect of the present invention, since the clock driver 21 is provided in the PLL circuit 1, the delay of the original clock signal 30 with respect to the reference clock signal 40 is limited only to the delay of the frequency divider 24 for feedback. Limited. Moreover,
The propagation of the primitive clock signal 30 is controlled in the clock buffer circuit 5 provided on each load circuit side. That is, without providing a special delay circuit in the PLL circuit 1,
Clock skew of the internal clock signal 34 with respect to the reference clock signal 40 is reduced.

According to the eighth aspect of the present invention, while the timer circuit 2 does not complete the measurement of a predetermined time sufficient for the source clock signal 30 output from the PLL circuit 1 to be synchronized with the reference clock signal 40, the source clock signal is not changed. As a result of the transmission of the clock signal 30 being prevented, the internal clock signal 34 not synchronized with the reference clock signal 40 is not supplied to the load circuit. In addition, when the predetermined number of pulses of the reference clock signal 40 input to the PLL circuit 1 are counted, the supply of the internal clock signal 34 to the load circuit starts. That is, the counter circuit 50 counts the pulses of the reference clock signal 40 supplied through the AND circuit 52. When the count value reaches a set value set in consideration of the lock-in time of the PLL circuit 1, the counter circuit 50 outputs a count completion signal 60. Once the count completion signal 60 is output in this way, the output is output from the AND circuit 52.
Self-holding by returning to. When the source clock signal 30 is synchronized with the reference clock signal 40,
The clock buffer circuit 5 interposed between the PLL circuit 1 and the load circuit is controlled so as to start supplying the internal clock signal 34 to the load circuit in synchronization with the reference clock signal 40. Thus, clocking can be started from a specific phase of the internal clock signal 34. When the clock stop request signal 42 is asserted, the clock buffer circuit 5 is controlled to stop supplying the internal clock signal 34 to the load circuit in synchronization with the reference clock signal 40. Thereby, the internal clock signal 34
Clocking suspension at a specific phase of
Further, when the assertion of the clock stop request signal 42 is released, the clock buffer circuit 5 controls the supply of the internal clock signal 34 to the load circuit immediately by using the held count completion signal 60 by using the held count completion signal 60. Is done. Moreover, the restart of the supply of the internal clock signal 34 is as follows.
This is performed in synchronization with the reference clock signal 40. As a result, speedy clocking restart from a specific phase of the internal clock signal 34 can be realized.

According to the ninth aspect of the present invention, the PLL circuit 1
The primitive clock signal 30 output from the
Synchronization to the synchronization signal 40 is transmitted to the synchronization detecting means 2a and 2b.
Clock signal transmission control means 3 to 3
5 prevents transmission of the original clock signal 30.
As a result, internal clocks not synchronized with the reference clock signal 40
The lock signal 34 is not supplied to the load circuit. So
To the first phase difference detection circuit 10 in the PLL circuit 1.
Input reference clock signal 40 and feedback clock signal 32
Load circuit when it is determined that the phase difference with
The supply of the internal clock signal 34 to the CPU starts. Further, the second phase difference detection circuit 11 for controlling the transmission of the source clock signal 30 has a lower accuracy than the first phase difference detection circuit 10 in the PLL circuit 1 between the reference clock signal 40 and the feedback clock signal 32. Detect the phase difference. In other words, the second phase difference detection circuit 11 allows the slight phase jitter of the original clock signal 30 and, when the phase of the feedback clock signal 32 is advanced with respect to the reference clock signal 40, the phase advance signal 90. If the signal is delayed, the phase delay signal 91
Are output as phase difference detection signals. Thereby, the convergence of the synchronization detection is improved. Then, when the synchronization confirmation unit 2b confirms that the state in which the second phase difference detection circuit 11 does not output the phase difference detection signals 90 and 91 has continued for a plurality of pulse periods of the reference clock signal 40,
It is determined that the original clock signal 30 is synchronized with the reference clock signal 40, and a synchronization detection signal 98 is output. The synchronization detection signal 98 output in this manner is held by the synchronization confirmation means 2b.

According to the tenth aspect of the present invention, when it is determined that the original clock signal 30 is synchronized with the reference clock signal 40, the clock buffer circuit 5 interposed between the PLL circuit 1 and the load circuit operates as the reference clock signal. Clock signal 40
Is controlled so that the supply of the internal clock signal 34 to the load circuit is started in synchronization with. Thus, clocking can be started from a specific phase of the internal clock signal 34. When the clock stop request signal 42 is asserted, the clock buffer circuit 5 synchronizes the internal clock signal 34 to the load circuit in synchronization with the reference clock signal 40.
Is controlled so as to stop the supply. Thereby, clocking suspension at a specific phase of the internal clock signal 34 can be realized. Further, when the assertion of the clock stop request signal 42 is released, the clock buffer circuit 5
By using the held synchronization detection signal 98,
The supply of the internal clock signal 34 to the load circuit is controlled to be restarted immediately. Moreover, the internal clock signal 3
4 is restarted in synchronization with the reference clock signal 40. As a result, speedy clocking restart from a specific phase of the internal clock signal 34 can be realized.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a clock generation circuit according to an embodiment of the present invention will be described with reference to the drawings. In each embodiment, a case is considered where the internal clock signal of the integrated circuit has twice the frequency of the reference external clock signal. It is needless to say that the frequency of the internal clock signal need not be limited to twice the frequency of the external clock signal, and may be arbitrarily set as needed.

(Embodiment 1) FIG. 1 shows a configuration of a clock generation circuit according to a first embodiment of the present invention. According to FIG. 1, the clock generation circuit according to the present embodiment includes a PLL circuit 1, a timer circuit 2,
It comprises a start control circuit 3, a stop control circuit 4, and a clock buffer circuit 5. The PLL circuit 1 includes a phase difference detection circuit 10 and a charge pump circuit 1
2, a loop filter circuit 14, a voltage controlled oscillator 16
, A first frequency divider 18, a delay circuit 22, and a second frequency divider 24. The timer circuit 2 includes a counter circuit 50 and a first AND circuit 52. Start and stop control circuits 3 and 4
The second AND circuit 54 includes first and second flip-flops 56 and 58. The clock buffer circuit 5 includes a third AND circuit 26 and an inverter circuit 28
And

Externally supplied reference clock signal 40
And the feedback clock signal 32 output from the second frequency divider 24 are input to the phase difference detection circuit 10. The output of the phase difference detection circuit 10 is supplied to the charge pump circuit 12, the output of the charge pump circuit 12 is supplied to the loop filter circuit 14,
The output of the loop filter circuit 14 is a voltage controlled oscillator 16
The output of the voltage controlled oscillator 16 is sequentially input to the first frequency divider 18. The original clock signal 30 output from the first frequency divider 18 is supplied as one input to a third AND circuit 26 in the clock buffer circuit 5 and is input to the delay circuit 22 and One flip-flop 56 is provided as a clock input. The output of the delay circuit 22 is input to the second frequency divider 24 so as to generate the feedback clock signal 32.

The reference clock signal 40 is also supplied to the first AND circuit 52 as one input thereof, and is also supplied to the second flip-flop 58 as a clock input. The output of the first AND circuit 52 is
Is input to The count completion signal 60 output from the counter circuit 50 is supplied to the second AND circuit 54 as one of its inputs, and is supplied to the first AND circuit 52 as the other input. The clock stop request signal 42 provided from the outside is provided to the second flip-flop 58 as a data input. Second flip-flop 5
The clock stop control signal 64 output from 8 is supplied to the second AND circuit 54 as the other input. The output of the second AND circuit 54 is provided to the first flip-flop 56 as a data input.

The clock propagation control signal 62 output from the first flip-flop 56 is supplied to the third AND circuit 26
Is given as the other input. The output of the third AND circuit 26 is supplied to the load circuit as an internal clock signal 34 via the inverter circuit 28. Further, the reset signal 44 given from the outside is the phase difference detection circuit 1
0, the voltage-controlled oscillator 16, the counter circuit 50, and the first flip-flop 56.

The operation of the clock generation circuit configured as described above will be described below. Phase difference detection circuit 10
Compares the phase of the reference clock signal 40 with the phase of the feedback clock signal 32 obtained by dividing the original clock signal 30 having a frequency twice that of the reference clock signal 40 by half. A pulse signal generated according to the phase difference is sent to the loop filter circuit 14 via the charge pump circuit 12. The charge pump circuit 12 and the loop filter circuit 14 convert a pulse signal generated according to the phase difference into a voltage value. The voltage controlled oscillator 16
A signal having a frequency four times the frequency of the reference clock signal 40 is generated using a voltage corresponding to the phase difference as a control voltage. The oscillation output of the voltage controlled oscillator 16 is frequency-divided by the first frequency divider 18 to obtain an original clock signal 30 having a frequency twice as high as the reference clock signal 40 and a duty ratio of 50%. The original clock signal 30 is supplied to the second frequency divider 2 via the delay circuit 22.
4 and further divided by と into a feedback clock signal 32. The operation of the PLL circuit 1 is as described above.

The clock buffer circuit 5 drives a load circuit with an internal clock signal 34 obtained by buffering the original clock signal 30. However, there is a certain amount of delay in driving this load circuit. That is, a phase difference occurs between the original clock signal 30 and the internal clock signal 34. Therefore, the delay circuit 22 is added to the feedback loop of the PLL circuit 1.
And the delay value of the delay circuit 22 is set so as to match the delay value in the clock buffer circuit 5 together with the delay value in the second frequency divider 24. Thus, the internal clock signal 34 having a frequency twice as high as that of the reference clock signal 40 is generated, and the phases of the reference clock signal 40 and the internal clock signal 34 are matched to minimize the clock skew.

The counter circuit 50 receives the reference clock signal 4
The pulse of 0 is counted in synchronization with the fall, and when the set number of counts is completed, the count completion signal 60 is output. The number of pulses of the reference clock signal 40 to be counted is set to be equal to or more than the number required for the PLL circuit 1 to lock in to the reference clock signal 40. The setting of the number of pulses may be fixed by hardware or may be set by software based on a certain control. The count completion signal 60 is synchronized at the falling edge of the source clock signal 30 in the first flip-flop 56, and then applied to the clock buffer circuit 5 as a clock propagation control signal 62 to propagate the source clock signal 30 to the load circuit. Control to be performed. While the count completion signal 60 is not output, the clock buffer circuit 5
Is controlled by a clock propagation control signal 62 so as not to propagate the primitive clock signal 30 to the load circuit,
Until the circuit 1 locks in to the reference clock signal 40, the source clock signal 30 whose phase and frequency are not guaranteed is prevented from being supplied to the load circuit. Further, when the count completion signal 60 is output, the first AND circuit 52 prevents the propagation of the reference clock signal 40 to the counter circuit 50, stops the counting operation in the counter circuit 50, and performs an unnecessary counting operation. Control not to perform. That is, the count completion signal 60 is held by itself.

The clock stop request signal 42 is synchronized at the falling edge of the reference clock signal 40 in the second flip-flop 58 to become the clock stop control signal 64, and the clock buffer circuit 5 sends the primitive clock signal 30 to the load circuit. Control to prevent propagation. The clock stop request signal 42 is used when the supply of the primitive clock signal 30 to the load circuit is forcibly stopped irrespective of the state of the PLL circuit 1 or the counter circuit 50.

FIG. 2 is a diagram showing a sequence when the clock generation circuit of this embodiment starts generating the internal clock signal 34. When the reset signal 44 is released in synchronization with the reference clock signal 40 in the first cycle, the voltage controlled oscillator 16 starts oscillating, and the counter circuit 50 counts the pulses in synchronization with the fall of the reference clock signal 40. Start. PLL circuit 1
Works so that the frequency and the phase of the reference clock signal 40 and the frequency and the phase of the feedback clock signal 32 output from the second frequency divider 24 match. On the other hand, after the reset signal 44 is released,
When the clock stop request signal 42 is released in synchronization with the rise of the reference clock signal 40 in the second cycle,
The second flip-flop 58 controls the clock stop control signal 6
4 is generated. The generated clock stop control signal 64 is input to the second AND circuit 54, and the control path is switched so that the clock propagation control signal 62 is controlled by the count completion signal 60 generated by the counter circuit 50.
When the count completion signal 60 is output in synchronization with the falling edge of the reference clock signal 40 in the nth cycle, the clock propagation control signal 62 is output in synchronization with the falling edge of the original clock signal 30 in the same cycle. Propagation control signal 62 activates clock buffer circuit 5. Thus, the internal clock signal 34 is generated from the subsequent (n + 1) th cycle to drive the load circuit.

Since the number of pulses of the reference clock signal 40 counted by the counter circuit 50 is set to a number sufficient for the PLL circuit 1 to lock in, the clock buffer circuit 5 is synchronized with the reference clock signal 40. The unprimed clock signal 30 is not transmitted to the load circuit. That is, after the original clock signal 30 sufficiently synchronized with the reference clock signal 40 is generated, it can be supplied to the load circuit as the internal clock signal 34.

FIG. 3 is a diagram showing a sequence when the internal clock signal 34 is stopped in the clock generation circuit of the present embodiment. When the clock stop request signal 42 is asserted in synchronization with the rise of the reference clock signal 40 in the nth cycle, the clock stop control signal 64 is asserted in synchronization with the fall of the reference clock signal 40 in the same cycle. Clock stop control signal 64
Are synchronized by the fall of the primitive clock signal 30, become the clock propagation control signal 62, and inhibit the clock buffer circuit 5 from generating the internal clock signal 34 and driving the load circuit. Thus, the supply of the internal clock signal 34 can be stopped from the next reference clock cycle in which the clock stop request signal 42 is asserted.

As shown in FIG. 3, when the reset signal 44 is asserted in synchronization with the rise of the reference clock signal 40 in the subsequent (n + 1) th cycle, the phase difference detection circuit 10, the voltage controlled oscillator 16, the counter circuit 50, and the first
Is reset. Thus, when the supply of the internal clock signal 34 is stopped, the PLL circuit 1
Stopping the operation itself reduces power consumption. Further, as a result of releasing the count completion signal 60, the lock-in time at the time of restart can be measured.

In the (n + 1) th cycle, the reset signal 4
When 4 is not asserted, the PLL circuit 1 continues to operate and the count completion signal 60 is held, so that speedy clocking can be restarted. FIG. 4 is a diagram showing a sequence when the supply of the internal clock signal 34 which has been temporarily stopped without giving the reset signal 44 in the clock generation circuit of the present embodiment is restarted. When the assertion of the clock stop request signal 42 is released in synchronization with the rise of the reference clock signal 40 in the nth cycle, the assertion of the clock stop control signal 64 is released in synchronization with the fall of the reference clock signal 40 in the same cycle. . The de-asserted clock stop control signal 64 is synchronized by the fall of the original clock signal 30, and clock propagation control is performed so as to allow the clock buffer circuit 5 to generate the internal clock signal 34 and drive the load circuit. A signal 62 is output. Thus, the supply of the internal clock signal 34 can be immediately restarted from the next reference clock cycle in which the assertion of the clock stop request signal 42 is released.

As described above, according to this embodiment, the PLL
The clock propagation control signal 62 is generated by counting the number of pulses required for the circuit 1 to lock in to the reference clock signal 40 by the counter circuit 50, and until the PLL circuit 1 locks in to the reference clock signal 40. By preventing the propagation of the primitive clock signal 30 to the load circuit by the clock buffer circuit 5, the internal clock signal 34
A function of starting clocking from a specific phase can be realized. Further, by controlling the clock buffer circuit 5 based on the clock stop request signal 42,
Each function of clocking pause at a specific phase and clocking restart from a specific phase can be realized.

In order to eliminate the clock skew, the second frequency divider 24 may have a delay by omitting the arrangement of the delay circuit 22 in the PLL circuit 1.

(Embodiment 2) FIG. 5 shows a configuration of a clock generation circuit according to a second embodiment of the present invention. According to FIG. 5, the clock generation circuit of the present embodiment includes a PLL circuit 1, a timer circuit 2,
It comprises a start control circuit 3, a stop control circuit 4, and a plurality of clock buffer circuits 5. P
The LL circuit 1 includes a phase difference detection circuit 10, a charge pump circuit 12, a loop filter circuit 14, a voltage controlled oscillator 16, a first frequency divider 18, a clock driver 21
And a second frequency divider 24. The configurations of the timer circuit 2, the start control circuit 3, the stop control circuit 4, and the clock buffer circuits 5 are the same as those in the first embodiment. However, the plurality of clock buffer circuits 5 are respectively arranged in the vicinity of the plurality of load circuits constituting the functional blocks in the integrated circuit.

In the PLL circuit 1, the original clock signal 30 is output from the clock driver 21 based on the output of the first frequency divider 18. The output primitive clock signal 30 is input to each of the clock buffer circuits 5 and the second frequency divider 24, and is also applied as a clock input to a first flip-flop 56 constituting the start control circuit 3. Further, the clock propagation control signal 62 output from the first flip-flop 56 is input to each clock buffer circuit 5.

According to the present embodiment, the clock driver 21 is provided at the output stage of the PLL circuit 1, so that the delay of the original clock signal 30 with respect to the reference clock signal 40 is limited to the delay in the second frequency divider 24 only. Limited. In addition, the propagation of the primitive clock signal 30 is controlled in the clock buffer circuit 5 provided on each load circuit side. That is, even if the delay circuit 22 is not provided in the PLL circuit 1 as in the first embodiment, the clock skew of the internal clock signal 34 with respect to the reference clock signal 40 is the conventional example (see FIG. 12).
It is reduced to the same extent.

(Embodiment 3) FIG. 6 shows a configuration of a clock generation circuit according to a third embodiment of the present invention. According to FIG. 6, the clock generation circuit of the present embodiment is obtained by adding reset control means including the second timer circuit 6 and the signal selection circuit 55 to the configuration of the first embodiment. The second timer circuit 6 has a configuration similar to that of the first timer circuit 2, and includes a second counter circuit 51 and a fourth AND circuit 53.

The internal clock signal 34 output from the clock buffer circuit 5 is supplied to a fourth AND circuit 53 as one of its inputs. The output of the fourth AND circuit 53 is input to the second counter circuit 51. Second count completion signal 61 output from second counter circuit 51
Is supplied to the signal selection circuit 55 as a first selected input signal, and is also supplied to the fourth AND circuit 53 as the other input. The signal selection circuit 55 is further supplied with a system reset signal 72 as a second selected input signal and an auto reset control signal 70 as a selection control signal. The internal reset signal 80 output from the signal selection circuit 55 is supplied to a load circuit together with the internal clock signal 34. Further, the reset signal 44 supplied from the outside corresponds to the phase difference detection circuit 10, the voltage controlled oscillator 1
6, used not only for resetting the first counter circuit 50 and the first flip-flop 56, but also for resetting the second counter circuit 51.

The signal selection circuit 55 switches the reset mode according to the automatic reset control signal 70. That is, when the auto reset control signal 70 is set to “H” level, the auto reset mode is selected, and when it is set to “L” level, the non-auto reset mode is selected. These reset modes are modes relating to a method of applying an internal reset signal 80 for resetting a load circuit as a target functional block.

In the auto reset mode, when the generation of the internal clock signal 34 is started, the second counter circuit 51
Internal reset signal 80 for the number of cycles set in
Is continuously asserted, and then the internal reset signal 80 is automatically deasserted. At this time, the second
The counter circuit 51 counts the pulses of the internal clock signal 34 in synchronization with the rise thereof, and outputs a second count completion signal 61 when the set number of counts is completed.
The number of pulses of the internal clock signal 34 to be counted is set to a number necessary to reset the load circuit. The setting of the number of pulses may be fixed by hardware or may be set by software based on a certain control. The second count completion signal 61 is input to the signal selection circuit 55 to control the application of the internal reset signal 80 to the load circuit. Furthermore, the second
Is output, the fourth AND circuit 53 outputs the internal clock signal 3 to the second counter circuit 51.
4 is stopped, the counting operation in the second counter circuit 51 is stopped, and control is performed so that unnecessary counting operation is not performed. On the other hand, the non-auto reset mode is a mode in which the system reset signal 72 is directly connected to the internal reset signal 80 regardless of the internal state of the second counter circuit 51.

FIG. 7 is a timing chart showing the operation of the auto reset mode. In the first cycle, the reset signal 4 is synchronized with the reference clock signal 40.
When 4 is released, the voltage controlled oscillator 16 starts oscillating. The PLL circuit 1 operates so that the frequency and phase of the reference clock signal 40 and the frequency of the feedback clock signal 32 output from the second frequency divider 24 are matched. Thereafter, as described in the first embodiment, the supply of the internal clock signal 34 starts from the (n + 1) th cycle, and the load circuit is driven. If the reset signal 44 has been released, the second counter circuit 51 counts the pulses in synchronization with the rise of the internal clock signal 34, and when the set number has been counted, a second count completion signal 61 is output. "H"
In the auto-reset mode in which the level auto-reset control signal 70 is given, the signal selection circuit 55 keeps asserting the internal reset signal 80 until the second count completion signal 61 is output. When the second count completion signal 61 is output, the internal reset signal 8
The assertion of 0 is released. Note that the internal clock signal 3
In the pause / resume sequence of No. 4, the auto reset control signal 70 is set to the “L” level so that the internal reset signal 80 is not output when the supply of the internal clock signal 34 is resumed.

As described above, according to the present embodiment, the number of cycles to which the internal reset signal 80 is to be applied is counted by the second counter circuit 51, and the internal clock signal 34 is internally clocked for a predetermined period from the start of clocking. By continuously giving the reset signal 80 and then automatically releasing it,
The internal reset signal 80 can be provided without being aware of the clocking start timing of the internal clock signal 34. The time for applying the internal reset signal 80 can be easily controlled by changing the value set in the second counter circuit 51.

The pulses of the reference clock signal 40 may be counted by the second counter circuit 51 instead of the internal clock signal 34. However, the set value of the second counter circuit 51 is made larger than the set value of the first counter circuit 50 so that the assertion of the internal reset signal 80 is released after the supply of the internal clock signal 34 is started.

(Embodiment 4) FIG. 8 shows a configuration of a clock generation circuit according to a fourth embodiment of the present invention. According to FIG. 8, the clock generation circuit of the present embodiment includes a PLL circuit 1 and a synchronization detection circuit 2a.
, A shift register 2b, a start control circuit 3, a stop control circuit 4, and a clock buffer circuit 5. Among them, the configurations of the PLL circuit 1, the start control circuit 3, the stop control circuit 4, and the clock buffer circuit 5 are the same as those in the first embodiment. However, the two-input AND circuit 54 in FIG.
4a. The synchronization detection circuit 2a
, The third and fourth flip-flops 57a and 57b, and an exclusive OR (EX-NOR)
And a circuit 82. The shift register 2b has a fifth
To the seventh flip-flops 59a, 59b, 59c.

Reference clock signal 40 externally applied
And the feedback clock signal 32 output from the second frequency divider 24 in the PLL circuit 1
The signal is also input to the second phase difference detection circuit 11.
The phase advance signal 90 and the phase delay signal 91 output from the second phase difference detection circuit 11 are supplied as data inputs to third and fourth flip-flops 57a and 57b, respectively. The advance latch signal 92 output from the third flip-flop 57a and the fourth flip-flop 57
The delay latch signal 93 output from b is input to the exclusive OR circuit 82. The EX-NOR signal 94 output from the exclusive OR circuit 82 is connected to the shift register 2b.
Is provided as a data input to the fifth flip-flop 59a constituting the first stage. Fifth flip-flop 5
The first-stage signal 95 output from 9a is supplied to the sixth flip-flop 59b as a data input. Furthermore,
The second-stage signal 96 output from the sixth flip-flop 59b is provided as a data input to the seventh flip-flop 59c. The third-stage signal 97 output from the seventh flip-flop 59c is the clock stop control signal 6
4 and the first and second stage signals 95 and 96 are input to the 4-input AND circuit 54a. 4-input AND circuit 5
The synchronization detection signal 98 output from 4a is provided to the first flip-flop 56 as a data input.

Further, the reference clock signal 40 is supplied to the third and fifth to seventh flip-flops 57a, 59a, 59
b, 59c are also provided as clock inputs. The feedback clock signal 32 is also provided to the fourth flip-flop 57b as a clock input. Further, the reset signal 44 given from the outside is the first phase difference detection circuit 10,
It is used not only for resetting the voltage-controlled oscillator 16 and the first flip-flop 56 but also for resetting the second phase difference detection circuit 11 and the fifth to seventh flip-flops 59a, 59b, 59c.

The operation of the clock generation circuit configured as described above will be described below. The first phase difference detection circuit 10 includes a reference clock signal 40 and a feedback clock signal 3
2 and the phase is compared. In parallel with this, the second phase difference detection circuit 11 also compares the phases of the reference clock signal 40 and the feedback clock signal 32. The second phase difference detection circuit 11 checks the timing of the rise of the feedback clock signal 32 with respect to the rise of the reference clock signal 40, and outputs the phase lead signal 90 and the phase delay signal 91 as phase difference detection signals. If the phase of the feedback clock signal 32 is advanced with respect to the reference clock signal 40, a pulse-shaped phase advance signal 90 is output in synchronization with the rise of the feedback clock signal 32. Conversely, if the phase of the feedback clock signal 32 is delayed with respect to the reference clock signal 40, a pulse-shaped phase delay signal 91 is output in synchronization with the rise of the reference clock signal 40. Phase lead signal 9
“0” is latched at the timing of the reference clock signal 40 in the third flip-flop 57 a and becomes a latch signal 92. On the other hand, the phase delay signal 91 is latched by the fourth flip-flop 57b at the timing of the feedback clock signal 32 and becomes a delay latch signal 93. The EX-NOR representing the period during which neither the phase advance signal 90 nor the phase delay signal 91 is output by the exclusive OR circuit 82 is output from the advance latch signal 92 and the delay latch signal 93.
A signal 94 is obtained.

EX output from exclusive OR circuit 82
The NOR signal 94 is connected to the fifth to seventh flip-flops 5;
9a, 59b and 59c synchronize and shift at the falling edge of the reference clock signal 40. And the 5th
A state in which all of the first to third stage signals 95 to 97 output from the seventh flip-flops 59a, 59b, 59c indicate the absence of the pulse of the phase advance signal 90 and the phase delay signal 91 ("H" level). ) And the clock stop control signal 64 is not asserted (“L” level)
The synchronization detection signal 98 is asserted by the 4-input AND circuit 54a only when This synchronization detection signal 98
When the clock propagation control signal 62 is asserted in response to the assertion, the clock buffer circuit 5 is activated,
The primitive clock signal 30 is supplied to the load circuit as the internal clock signal 34. That is, when the second phase difference detection circuit 11 determines that there is no phase difference between the reference clock signal 40 and the feedback clock signal 32 in three consecutive cycles of the reference clock signal 40, the PLL circuit 1 The clock propagation control signal 62 is asserted assuming that the lock-in is performed.

The phase difference detection accuracy of the second phase difference detection circuit 11 is set lower than the phase difference detection accuracy of the first phase difference detection circuit 10 in the PLL circuit 1. Thereby, the convergence of the synchronization detection can be improved. That is, the accuracy of the loop filter circuit 14, the stability of the voltage controlled oscillator 16,
Even if the phase synchronization in the PLL circuit 1 is not completely performed due to a power supply voltage fluctuation, external noise, or the like, if the phase difference detection accuracy of the second phase difference detection circuit 11 is within the accuracy, the primitive clock signal 30 is used as the internal clock. The signal 34 can be supplied to a load circuit. Further, when a phase shift occurs in a range exceeding the phase difference detection accuracy of the second phase difference detection circuit 11, it acts to prevent the original clock signal 30 from being propagated as the internal clock signal 34, and It is also possible to prevent a malfunction due to the occurrence.

FIG. 9 is a diagram showing a sequence when the internal clock signal 34 is started to be generated in the clock generation circuit of this embodiment. When the reset signal 44 is released in synchronization with the reference clock signal 40 in the first cycle, the voltage controlled oscillator 16 starts oscillating. The PLL circuit 1 operates so that the frequency and phase of the reference clock signal 40 and the frequency of the feedback clock signal 32 output from the second frequency divider 24 are matched. In FIG. 9, the phase delay of the feedback clock signal 32 is detected in the second cycle, the phase advance of the feedback clock signal 32 is detected in the third and fourth cycles, and the feedback clock signal 3 is detected in the fifth cycle.
2 shows an example in which a phase delay of 2 is detected and the phase difference between the reference clock signal 40 and the feedback clock signal 32 is not detected after the sixth cycle. After the sixth cycle, the exclusive OR circuit 82 outputs the EX-NOR signal 9 of “H” level.
4 continues to be asserted. The EX-NOR signal 9 over three reference clock cycles of the sixth, seventh and eighth cycles
4 is continuously asserted, the synchronization detection signal 98 is asserted, and the clock propagation control signal 6 continues.
2 is asserted. Thus, the internal clock signal 34 starts to be supplied to the load circuit from the ninth cycle.

The sequence for stopping the internal clock signal 34 and the temporarily stopped internal clock signal 34
The sequence when restarting the supply of is the same as in FIG. 3 and FIG.

As described above, according to this embodiment, the phase difference between the reference clock signal 40 and the feedback clock signal 32 is detected by the second phase difference detection circuit 11, and the third to seventh flip-flops 57a , 57b, 59a, 59b, 59c, an exclusive OR circuit 82, and a four-input AND circuit 54a to perform synchronization detection to generate a clock propagation control signal 62, and the PLL circuit 1 By blocking the propagation of the primitive clock signal 30 to the load circuit until the lock-in is performed by the clock buffer circuit 5, a function of starting clocking from a specific phase of the internal clock signal 34 can be realized. In addition, by controlling the clock buffer circuit 5 based on the clock stop request signal 42, each function of clocking suspension at a specific phase and clocking restart from a specific phase can be realized.

In this embodiment, the reference clock signal 40
It is assumed that the phase synchronization of the PLL circuit 1 is realized when the state where there is no phase difference between the feedback clock signal 32 and the reference clock signal 32 lasts for three reference clock cycles. However, the number of flip-flops in the shift register 2b and the AND circuit This period can be freely set by changing the number of inputs of 54a.

If a relatively large phase jitter is allowed in the original clock signal 30 output from the PLL circuit 1, the arrangement of the second phase difference detection circuit 11 is omitted, and It is also possible to use the output of the first phase difference detection circuit 10 as the phase lead signal 90 and the phase delay signal 91.

(Embodiment 5) FIG. 10 shows a configuration of a clock generation circuit according to a fifth embodiment of the present invention. The relationship between the fourth embodiment (FIG. 8) and the fifth embodiment (FIG. 10) is similar to that of the first embodiment (FIG. 1).
Since the relationship is the same as that of the second embodiment (FIG. 5), a detailed description of the clock generation circuit of the fifth embodiment is omitted.

According to the fifth embodiment, the clock driver 2 is connected to the output stage of the PLL circuit 1 as in the second embodiment.
1, the delay circuit 22 in the PLL circuit 1 is provided.
Is not provided, the clock skew of the internal clock signal 34 with respect to the reference clock signal 40 is reduced to about the same level as in the conventional example (see FIG. 12).

(Embodiment 6) FIG. 11 shows a configuration of a clock generation circuit according to a sixth embodiment of the present invention. The relationship between the fourth embodiment (FIG. 8) and the sixth embodiment (FIG. 11) is similar to that of the first embodiment (FIG. 1).
And the third embodiment (FIG. 6), the detailed description of the clock generation circuit of the sixth embodiment is omitted.

According to the sixth embodiment, similarly to the third embodiment, the number of cycles to which the internal reset signal 80 is to be applied is counted by the second counter circuit 51, and the clock of the internal clock signal 34 is counted. By continuously providing the internal reset signal 80 for a predetermined period from the start of locking, and then automatically releasing the internal reset signal 80, the internal reset signal 8 can be provided without being aware of the clocking start timing of the internal clock signal 34.
0 can be given.

[0071]

As described above in detail, according to the first and second aspects of the present invention, the internal clock is maintained until the original clock signal 30 output from the PLL circuit 1 is synchronized with the reference clock signal 40. When the signal 34 is not supplied to the load circuit and the original clock signal 30 is synchronized with the reference clock signal 40, the supply of the internal clock signal 34 to the load circuit is started in synchronization with the reference clock signal 40, and the clock stop request signal 42 Is asserted, the supply of the internal clock signal 34 to the load circuit is changed to the reference clock signal 40.
, The internal clock signal 34 not synchronized with the reference clock signal 40 can be prevented from being supplied to the load circuit, and the clocking of the internal clock signal 34 from a specific phase can be started. Resumption and clocking suspension at a specific phase of the internal clock signal 34 can be realized.

According to the third aspect of the present invention, the load circuit
After the supply of the external clock signal 34 is started, the load circuit
Assertion of the internal reset signal 80 to the road is automatically released
Is done. Thereby, the clock of the internal clock signal 34 is
Externally knows the timing at which
There is no need to

According to the fourth aspect of the present invention, the internal reset signal
Internal clock signal
Since the configuration determined by the pulse count of 34 was adopted,
Internal reset signal after start of supply of internal clock signal 34
Deassertion of 80 is guaranteed.

According to the fifth aspect of the present invention, the internal reset signal
The timing of deassertion of signal 80 is, for example,
Lock-in of PLL circuit required by simulation
Pulse count of the reference clock signal 40 in consideration of time
Is determined by

According to the sixth aspect of the present invention, the clock skew of the internal clock signal with respect to the reference clock signal is eliminated by providing the delay circuit in the PLL circuit.

According to the seventh aspect of the present invention, by providing the clock driver 21 in the PLL circuit 1, the clock skew of the internal clock signal 34 with respect to the reference clock signal 40 is reduced to the same level as in the conventional case.

According to the eighth aspect of the present invention, while the timer circuit 2 does not complete the measurement of a predetermined time sufficient for the source clock signal 30 output from the PLL circuit 1 to be synchronized with the reference clock signal 40, the source clock signal is not measured. Since the configuration for preventing transmission of the clock signal 30 is employed, supply of the internal clock signal 34 not synchronized with the reference clock signal 40 to the load circuit can be prevented. In addition, the counter circuit 50 and the AND circuit 52 operate so that the supply of the internal clock signal 34 to the load circuit is started when a predetermined number of pulses of the reference clock signal 40 input to the PLL circuit 1 are counted. With a simple configuration, the supply start timing of the internal clock signal 34 can be controlled. Further, not only can clocking start from a specific phase of the internal clock signal 34 and clocking suspension at a specific phase be realized, but also speedy restarting of clocking from a specific phase of the internal clock signal 34 can be realized. realizable.

According to the ninth aspect of the present invention, the PLL circuit 1
The primitive clock signal 30 output from the
Synchronization to the synchronization signal 40 is transmitted to the synchronization detecting means 2a and 2b.
Clock signal transmission control means 3 to 3
5 prevents transmission of the primitive clock signal 30.
Since it is adopted, it is synchronized with the reference clock signal 40.
To prevent the internal clock signal 34 from being supplied to the load circuit.
Wear. Moreover, the first phase difference detection circuit in the PLL circuit 1
Reference clock signal 40 and feedback clock input to 10
When it is determined that the phase difference with the signal 32 has disappeared
The supply of the internal clock signal 34 to the load circuit starts.
Further, the second phase difference detection circuit 11 for controlling the transmission of the original clock signal 30 has a lower precision than the first phase difference detection circuit 10 in the PLL circuit 1 between the reference clock signal 40 and the feedback clock signal 32. Since the phase difference is detected, the convergence of the synchronization detection is improved. When the synchronization confirmation means 2b confirms that the state in which the second phase difference detection circuit 11 does not output the phase difference detection signals 90 and 91 continues for a plurality of pulses of the reference clock signal 40, the synchronization detection signal 98 is output. Is output, the accuracy of synchronization detection is improved.

According to the tenth aspect of the present invention, not only clocking start from a specific phase of the internal clock signal 34 and clocking suspension at a specific phase can be realized, but also specific clocking of the internal clock signal 34 can be realized. Speedy clocking restart from the phase can be realized.

In general, according to the present invention, a clock having the functions of starting clocking from a specific phase of the internal clock signal 34, temporarily stopping clocking at a specific phase, and resuming clocking from a specific phase. A generation circuit can be realized. Further, a function of automatically releasing the asserted internal reset signal 80 at an appropriate timing according to the clocking of the internal clock signal 34 can be realized. In a system using an integrated circuit employing a clock generation circuit according to the present invention, step execution and operation suspension / resumption during debugging of hardware and software can be performed, and power consumption management of the system and the integrated circuit itself can be performed. This is a very useful technique for controlling the clock signal at the time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a clock generation circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a sequence when the clock generation circuit of FIG. 1 starts generating an internal clock signal.

FIG. 3 is a timing chart showing a sequence when the supply of an internal clock signal is stopped in the clock generation circuit of FIG. 1;

4 is a timing chart showing a sequence when the supply of an internal clock signal is restarted in the clock generation circuit of FIG. 1;

FIG. 5 is a block diagram showing a clock generation circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a clock generation circuit according to a third embodiment of the present invention.

FIG. 7 is a timing chart showing a sequence when the clock generation circuit of FIG. 6 starts generating an internal clock signal in an auto-reset mode.

FIG. 8 is a block diagram illustrating a clock generation circuit according to a fourth embodiment of the present invention.

9 is a timing chart illustrating a sequence when the clock generation circuit of FIG. 8 starts generating an internal clock signal.

FIG. 10 is a block diagram showing a clock generation circuit according to a fifth embodiment of the present invention.

FIG. 11 is a block diagram showing a clock generation circuit according to a sixth embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a conventional clock generation circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 phase locked loop circuit (PLL circuit) 2, 6 timer circuit 2 a synchronization detection circuit 2 b shift register 3 start control circuit 4 stop control circuit 5 clock buffer circuit 10, 11 phase difference detection circuit 12 charge pump circuit 14 loop filter circuit 16 voltage Control oscillator (VCO) 18, 24 Divider 21 Clock driver 22 Delay circuit 26 AND circuit 28 Inverter circuit 30 Primitive clock signal 32 Feedback clock signal 34 Internal clock signal 40 Reference clock signal 42 Clock stop request signal 44 Reset signal 50, 51 counter circuit 52, 53, 54, 54a AND circuit 55 signal selection circuit 56, 57a, 57b, 58, 59a, 59b, 59c
Flip-flops 60, 61 Count complete signal 62 Clock propagation control signal 64 Clock stop control signal 70 Auto reset control signal 72 System reset signal 80 Internal reset signal 82 Exclusive OR circuit (EX-NOR circuit) 90 Phase advance signal 91 Phase delay Signal 92 Lead latch signal 93 Delay latch signal 94 EX-NOR signal 95, 96, 97 First-stage, second-stage, and third-stage signals 98 Synchronization detection signal

Claims (10)

(57) [Claims] 1. A clock generation circuit for supplying an internal clock signal synchronized with a reference clock signal to a load circuit, wherein the clock generation circuit generates a primitive clock signal having a frequency that is an integral multiple of the reference clock signal, and A phase locked loop circuit for adjusting the phase of the source clock signal so that the source clock signal is synchronized with the reference clock signal, and the phase locked loop circuit for controlling the supply of an internal clock signal to the load circuit. A clock buffer circuit interposed between the clock circuit and the load circuit, and the clock buffer circuit converts the internal clock signal to the load circuit until a source clock signal output from the phase locked loop circuit is synchronized with a reference clock signal. Clock source, and when the source clock signal is synchronized with the reference clock signal, the clock A clock signal supply start control means for controlling the clock buffer circuit so that the clock circuit starts supplying the internal clock signal to the load circuit in synchronization with the reference clock signal; and a clock stop request signal is asserted. The clock buffer circuit includes clock signal supply stop control means for controlling the clock buffer circuit so as to stop the supply of the internal clock signal to the load circuit in synchronization with the reference clock signal. Characteristic clock generation circuit. 2. The clock generation circuit according to claim 1, wherein the phase locked loop circuit outputs a phase advance signal when the phase of the feedback clock signal is advanced with respect to the reference clock signal, and outputs a phase advance signal when the phase of the feedback clock signal is delayed. A phase difference detection circuit for outputting a phase delay signal, a charge pump circuit for adjusting a voltage of an output signal according to a phase advance signal and a phase delay signal output from the phase difference detection circuit, A loop filter circuit for outputting a control voltage by passing a low frequency component of an output signal of the charge pump circuit; and a source clock signal having a frequency corresponding to the control voltage output from the loop filter circuit. And a signal having a frequency obtained by dividing a source clock signal generated by the voltage controlled oscillator. A clock generation circuit comprising: a frequency divider for supplying a phase difference detection circuit as a feedback clock signal. 3. The clock generating circuit according to claim 1,
Thus, the supply of the internal clock signal to the load circuit was started.
Release assertion of internal reset signal to the load circuit later
Reset control means for resetting
Clock generation circuit. 4. The clock generation circuit according to claim 3, wherein
The reset control means controls the internal clock to the load circuit.
When the predetermined number of pulses of the
To deassert the internal reset signal to the
A counter circuit for outputting a number completion signal is provided.
A clock generation circuit. 5. The clock generation circuit according to claim 3, wherein
The reset control means enters the phase locked loop circuit.
Counts a specified number of pulses of the reference clock signal
Of the internal reset signal to the load circuit when
To output a count completion signal to cancel
A clock generation circuit comprising a clock circuit. 6. A clock generation circuit for supplying an internal clock signal synchronized with a reference clock signal to a load circuit, wherein the clock generation circuit generates a primitive clock signal having a frequency that is an integral multiple of the reference clock signal, and A phase locked loop circuit for adjusting the phase of the source clock signal so that the source clock signal is synchronized with the reference clock signal, and the phase locked loop circuit for controlling the supply of an internal clock signal to the load circuit. A clock buffer circuit interposed between the clock circuit and the load circuit, and the clock buffer circuit converts the internal clock signal to the load circuit until a source clock signal output from the phase locked loop circuit is synchronized with a reference clock signal. Clock source, and when the source clock signal is synchronized with the reference clock signal, the clock Clock signal supply start control means for controlling the clock buffer circuit so that the power supply circuit starts supply of the internal clock signal to the load circuit in synchronization with the reference clock signal. A phase difference detection circuit for outputting a phase advance signal when the phase of the feedback clock signal is advanced with respect to the reference clock signal, and a phase delay signal when the phase of the feedback clock signal is delayed, A charge pump circuit for adjusting the voltage of the output signal in accordance with the phase advance signal and the phase delay signal output from the circuit, and a control voltage by passing a low frequency component of the output signal of the charge pump circuit. A loop filter circuit for outputting, and a primitive clock signal having a frequency corresponding to a control voltage output from the loop filter circuit A voltage controlled oscillator for generating; a frequency divider for supplying a signal having a frequency obtained by dividing the original clock signal generated by the voltage controlled oscillator to the phase difference detection circuit as a feedback clock signal; and a feedback clock. To delay the source clock signal generated by the voltage controlled oscillator such that the phase difference between the signal and the source clock signal is equal to the phase difference between the source clock signal and the internal clock signal based on the delay in the clock buffer circuit. And a delay circuit. 7. A clock generation circuit for supplying an internal clock signal synchronized with a reference clock signal to a plurality of load circuits, wherein the clock generation circuit generates a primitive clock signal having a frequency that is an integral multiple of the reference clock signal, and A phase locked loop circuit for adjusting the phase of the source clock signal so that the generated source clock signal is synchronized with the reference clock signal, and controlling supply of an internal clock signal to each of the plurality of load circuits. A plurality of clock buffer circuits disposed between the phase-locked loop circuit and the plurality of load circuits in the vicinity of each load circuit, and each receiving a source clock signal from the phase-locked loop circuit; Until the original clock signal output from the loop circuit synchronizes with the reference clock signal, the plurality of clock buffer circuits Each of the plurality of clock buffer circuits is synchronized with the reference clock signal so as not to supply the internal clock signal to each load circuit and when the original clock signal is synchronized with the reference clock signal. Clock signal supply start control means for controlling the plurality of clock buffer circuits so as to start supply of a clock signal, wherein the phase-locked loop circuit has a phase of a feedback clock signal advanced with respect to a reference clock signal. Phase difference signal for outputting a phase lead signal when the signal is delayed, and a phase difference signal for outputting a phase delay signal when the signal is delayed, according to the phase lead signal and the phase delay signal output from the phase difference detection circuit. A charge pump circuit for adjusting the voltage of the output signal; and a low-frequency component of the output signal of the charge pump circuit. A loop filter circuit for outputting a control voltage by passing the voltage, a voltage controlled oscillator for generating a primitive clock signal having a frequency corresponding to the control voltage output from the loop filter circuit, and a voltage controlled oscillator generated by the voltage controlled oscillator. A frequency divider for supplying a signal having a frequency obtained by dividing the divided source clock signal to the phase difference detection circuit as a feedback clock signal, and a source clock signal supplied to each of the plurality of clock buffer circuits. A clock driver for driving a signal line based on an output of the voltage controlled oscillator. 8. A clock generation circuit for supplying an internal clock signal synchronized with a reference clock signal to a load circuit, wherein the clock generation circuit generates a primitive clock signal having a frequency that is an integral multiple of the reference clock signal, and A phase locked loop circuit for adjusting the phase of the source clock signal so that the source clock signal is synchronized with the reference clock signal; and a source clock signal output from the phase locked loop circuit being synchronized with the reference clock signal. And an AND circuit for receiving the reference clock signal as one input so as to measure a predetermined time sufficient to output a count completion signal when a predetermined number of pulses of the output signal of the AND circuit are counted. And a count completion signal output from the counter circuit as the other input of the AND circuit. A returned clock circuit, a clock buffer circuit interposed between the phase locked loop circuit and the load circuit so as to control supply of an internal clock signal to the load circuit, and a count completion signal from the counter circuit. The clock buffer circuit does not supply the internal clock signal to the load circuit while the clock signal is not output, and the clock buffer circuit synchronizes with the reference clock signal to output the internal clock to the load circuit when the count completion signal is output. A start control circuit for controlling the clock buffer circuit so as to start supplying a signal; and when the clock stop request signal is asserted, the clock buffer circuit synchronizes with the reference clock signal to generate an internal clock to the load circuit. Controlling the clock buffer circuit to stop supplying the signal; When the assertion of the clock stop request signal is released, the clock buffer circuit immediately supplies the internal clock signal to the load circuit using the held count completion signal from the counter circuit and in synchronization with the reference clock signal. A stop control circuit for controlling the clock buffer circuit to restart, the phase-locked loop circuit, when the phase of the feedback clock signal is advanced with respect to the reference clock signal, the phase advance signal, A phase difference detection circuit for outputting each of the phase delay signals when delayed, and a charge for adjusting the voltage of the output signal in accordance with the phase advance signal and the phase delay signal output from the phase difference detection circuit A pump circuit; and passing a control voltage by passing a low frequency component of an output signal of the charge pump circuit. A voltage-controlled oscillator for generating a source clock signal having a frequency corresponding to the control voltage output from the loop filter circuit; and a source-side clock signal generated by the voltage-controlled oscillator. A frequency divider for supplying a signal having the divided frequency to the phase difference detection circuit as a feedback clock signal. 9. An internal clock synchronized with a reference clock signal.
Clock generator to supply the clock signal to the load circuit.
Source clock with a frequency that is an integer multiple of the reference clock signal
Signal, and based on the generated source clock signal.
Of the original clock signal so as to be synchronized with the quasi-clock signal.
A phase locked loop circuit for adjusting a phase, and a primitive clock signal output from the phase locked loop circuit.
Signal is input to the phase locked loop circuit.
Synchronization detection means for detecting synchronization with the signal, while the synchronization detection means does not detect synchronization
The primitive clock signal output from the phase locked loop circuit is
Do not supply the load circuit as an internal clock signal
A clock for controlling the transmission of the primitive clock signal.
Signal transmission control means, wherein the phase-locked loop circuit advances the phase of the feedback clock signal with respect to the reference clock signal.
Phase lead signal if it is
First phase difference detection circuit for outputting each phase delay signal
And a phase advance signal output from the first phase difference detection circuit
And adjust the voltage of the output signal according to the phase delay signal.
And a low-frequency component of the output signal of the charge pump circuit.
To output the control voltage by passing
And loop filter circuit, according to a control voltage output from the loop filter circuit
Control to generate a source clock signal with different frequency
An oscillator and a primitive clock signal generated by the voltage controlled oscillator
The signal having the frequency obtained by dividing the frequency
And a frequency divider for supplying a feedback clock signal to the
The phase-locked loop circuit includes:
Reference clock signal and the feedback is input to the phase difference detecting circuit
When it is determined that the phase difference with the clock signal has disappeared
The clock signal transmission control means
Synchronization detection signal to start the supply of the external clock signal
And a phase difference detecting means for comparing a phase of a reference clock signal and a phase of a feedback clock signal input to a first phase difference detecting circuit in the phase locked loop circuit. And a second phase difference for outputting a phase advance signal as a phase difference detection signal when the phase of the feedback clock signal is advanced with respect to the reference clock signal, and as a phase difference detection signal when the phase is delayed. A detection circuit, outputting a synchronization detection signal when the state in which the second phase difference detection circuit does not output the phase difference detection signal continues for a plurality of pulse periods of the reference clock signal, and A clock confirming means for holding the clock signal, wherein the second phase difference detection circuit is set to have lower phase difference detection accuracy than the first phase difference detection circuit. Raw circuit. 10. The clock generation circuit according to claim 9 , wherein the clock signal transmission control means controls the supply of an internal clock signal to the load circuit between the phase locked loop circuit and the load circuit. A clock buffer circuit interposed between the clock buffer circuit and the phase difference detection unit so that the clock buffer circuit does not supply an internal clock signal to the load circuit while the synchronization detection signal is not output, and the synchronization detection signal is output when the synchronization detection signal is output. A start control circuit for controlling the clock buffer circuit so that the clock buffer circuit starts supplying the internal clock signal to the load circuit in synchronization with a reference clock signal; and a clock stop request signal is asserted when the clock stop request signal is asserted. A clock buffer circuit synchronizes with the reference clock signal to generate an internal clock to the load circuit. The clock buffer circuit is controlled so as to stop the supply of the clock signal, and when the clock stop request signal is deasserted, the clock buffer circuit uses the held synchronization detection signal from the synchronization confirmation unit. And a stop control circuit for controlling the clock buffer circuit so as to immediately restart supply of the internal clock signal to the load circuit in synchronization with a reference clock signal.