JPS6146615A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To inhibit the transmission of an abnormal oscillation output by giving a time difference between the restart of a clock oscillating circuit and its output transmission timing. CONSTITUTION:When an operation stop signal HLT is brought into a high level by a timer circuit TM, an FF1 is driven by the rising edge of a frequency division output phi1, an output signal A goes to a high level to open a NAND circuit G1 and the clock oscillating circuit OSC2 starts its oscillation. On the other hand, when the signal A goes to high level, an FF2 is driven by the rising edge of a frequency division output phi2, an output signal B goes to a high level, a NAND circuit G2 is opened and the oscillating output of the clock oscillating circuit OSC2 is transmitted. Since the frequency dividion output phi2 is delayed than the frequency division output phi1 in this case, the NAND circuit G2 is opened slower than the NAND circuit G1 and the abnormal oscillation just after the start of oscillation of the clock oscillating circuit is not transmitted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device, and, for example, to a technique effective for use in a semiconductor integrated circuit device having a microcomputer function.

[Background technology]

For example, a liquid crystal display control circuit using a single-chip microcomputer function is known (see "Liquid Crystal Drive Type LCD III User's Manual" published by II Hitachi, September 1983).

This semiconductor integrated circuit device LCD] Tr is provided with a function of reducing power consumption by halting the operation of the clock oscillation circuit by a program and halting the operation of the internal circuit. The above operation stoppage is canceled by a predetermined time signal generated by a separately provided timer oscillation circuit.

In order to highly stabilize the frequency of the above clock oscillation circuit,
When a crystal resonator or a ceramic resonator is used, when the suspension of its operation is canceled, in other words, when the clock oscillation circuit is put into operation again, abnormal oscillation occurs and a stable frequency signal cannot be obtained. It will take some time until it is completed. Therefore, if a clock oscillation circuit is configured using the above-mentioned resonator, there is a risk that the internal circuit may malfunction due to abnormal oscillation when the above-mentioned bolt operation is released. A problem arises in that the operation cannot be performed.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device having a microcomputer function with stable operation.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the clock oscillation circuit is regenerated to form the clock signal for the internal circuit by utilizing the time difference in the frequency division stage output of the frequency division circuit that receives the oscillation output from the timer square oscillation circuit and forms the time pulse for the hour hand circuit. By providing a time difference between activation and its output sending timing, sending out of abnormal oscillation output is prohibited.

〔Example〕

FIG. 1 shows a block diagram of one embodiment of the invention. Each circuit block in the figure is formed on a semiconductor substrate of 1 llil, such as, but not limited to, single crystal silicon, using known semiconductor integrated circuit manufacturing techniques.

The oscillation surface 1i03c1 forms a reference frequency signal for a timer. That is, although not particularly limited, 0MO3(
The input and output of the complementary MO8) inverter circuit IVI are:
Each is coupled to an external terminal.

A bias resistor R1 and a crystal resonator X1 are connected between these external terminals. Further, capacitors CI and C2 are provided between each external terminal and the ground potential point of the circuit, respectively. The oscillation output obtained from the output of the CMOS inverter circuit IVI is the output of the CMOS inverter circuit IV
2, and is supplied to the input of the frequency divider circuit DVI. The frequency dividing stage output φ1 of the frequency dividing circuit DVI is further supplied to the input of the frequency dividing circuit DV2 to form a predetermined time pulse. Although not particularly limited, the oscillation frequency of the oscillation circuit 0301 is set to 32768Hz, and the oscillation frequency is set to 32768Hz, which is
A 1 second pulse is formed by dividing the frequency in 5 steps. Although not particularly limited, the output φ1 of the frequency dividing circuit DVI is 12
8 Hz, and the output φ2 of the frequency divider circuit DV2 is set to 16 Hz. The output φ2 of the frequency dividing circuit DV2 is supplied to a timer circuit TM (not shown), where the frequency is further divided to form, for example, a one-second pulse.

Oscillation surface 1i! 8.03c2 forms the reference frequency signal for the clock. In this embodiment, by stopping the clock signal during the period when the internal circuit does not perform its information processing operation, the operation of the internal circuit is stopped and power consumption is reduced. In order to selectively stop the operation of the lock signal in this way, the amplifier circuit constituting the oscillation circuit 05C2 is not particularly limited, but may be a NAND
A gate circuit G1 is used. That is, one input and output of the Nant gate circuit G1 are each coupled to an external terminal. A bias resistor R2 and, although not particularly limited, a crystal resonator X2 are connected to these external terminals, respectively. Further, capacitors C3 and C4 are connected to each external terminal and the ground potential point of the circuit. The other input of the Nant gate circuit G1 has a high level (logic "1").
) is supplied, the gate is kept open, so oscillation is performed according to the constant of the external element. Furthermore, when a low level (logic "0") is supplied to the other input, the gate is closed, and its output is set to a high level (logic "1") regardless of the one input level. This causes the oscillation to stop.

In order to control the operation of the oscillation plane I7#roSC2 as described above, the control signal A obtained from the output Q of the flip-flop circuit FFI is supplied to the other input of the Nant gate circuit G2. The clock terminal CK of this Frisop flop circuit FFI is supplied with the output signal φ1 of the frequency dividing circuit DVI, and the operation stop signal HLT is supplied to the input terminal thereof.
is supplied.

Further, the output signal of the oscillation circuit 03C2 is transmitted to a clock 5cpc (not shown) through a Nant gate circuit G2 which also functions as waveform shaping.

The opening and closing of the gate of this Nant gate circuit G2 is controlled by the next control signal B. That is, although not particularly limited, the output signal A of the flip-flop circuit FFI is supplied to the input terminal of the flip-flop circuit FF2. The output signal φ2 of the frequency dividing circuit DV2 is supplied to the clock terminal CK of this flip-flop circuit FF2.

The control signal B is generated from the output Q of this flip-flop circuit FF2.

The operation of this embodiment circuit will now be described with reference to the waveform diagram shown in FIG.

When no information processing operation is performed in the internal circuit, the operation stop signal HLT is set to a low level. As a result, the output signal A of the flip-flop circuit FFI is brought to a low level in synchronization with the frequency-divided output φ1. As a result, the output 03C2 of the Nant gate circuit G1 is brought to a high level, and its oscillation operation is stopped.

Note that due to the low level of the signal A and the frequency divided output φ2, the control signal B obtained from the output of the flip-flop circuit FF2 also becomes low level, so that the gate of the Nant gate circuit G2 is also kept in a closed state.

In such a state, when the operation stop signal HLT is set to high level by the timer circuit TM or the like, in other words, when the internal circuit is restarted, the rising edge of the frequency-divided output φ1 , the flip-flop circuit 1"F1 reads it and sets its output signal A to a high level. As a result, the gate of the Nant gate circuit G1 is opened again, and the oscillation operation starts. At this time, the oscillation output 03C2 causes abnormal oscillation immediately after the start of its operation, and it takes time to obtain a stable frequency signal.

The Nant gate circuit G2 is provided to prevent clock pulses from being generated by frequency signals generated by such abnormal oscillation operations. When the output signal A of the flip-flop circuit FFI rises to a high level, the oscillation circuit 03C2 immediately starts an oscillation operation, but at this time the gate circuit G2 is still closed. That is, since the frequency-divided output φ2 is supplied to the clock terminal GK of the flip-flop FF2, from the time the signal A goes high until the division output φ2 rises to the high level, the previous frequency output φ2 is This is because the state is maintained. When the frequency-divided output φ2 rises to a high level, the flip-flop circuit FF2 reads the high level of the signal A and sets its output signal B to a high level to open the Nant gate circuit G2. As a result, the output of the oscillation circuit 03G2 is prohibited from being sent to the clock circuit CPG only during the time difference between the frequency-divided outputs φ1 and φ2. This time difference is set to be longer than the time required for the oscillation operation to stabilize. Normally, in an oscillation circuit using a crystal resonator or a ceramic resonator, the time required to divide 128Hz into three stages (16H,z) is shorter than the time required to divide 128Hz into three stages (16H,z), so the abnormal oscillation frequency causes the clock signal to can be prevented from forming.

The circuit of the embodiment shown in FIG. 1 is built into a one-chip microcomputer or the liquid crystal display control circuit (LCD III) having a microcomputer function.

〔effect〕

(1) Utilizing the time difference in the frequency dividing stage output of the frequency dividing circuit for the timer, by creating a time difference between the operation start timing of the lock oscillation circuit and its output timing, oscillation in the oscillation circuit using a resonator is achieved. It is possible to prohibit the transmission of abnormal oscillation output immediately after the start. This provides the effect that the vibrator can be used as a clock oscillation circuit whose operation is selectively stopped.

(2) According to (1) above, since a clock signal can be generated by an oscillation circuit using a vibrator, a highly stable clock signal with a relatively high frequency can be generated, and it can be stopped at will. This effect can be obtained.

(3) Since the output of the divider stage of the timer circuit is used to prohibit the output of abnormal oscillation immediately after the start of oscillation in the clock oscillation circuit, the advantage is that the configuration can be extremely simple. It will be done.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. The clock oscillation circuit and the output gate circuit may use a NOR gate circuit or the like. In addition, the amplifier circuit that constitutes the clock oscillation circuit is a power switch MO3FE.
By selectively supplying power by T,
The operation may be performed selectively. Furthermore, the circuit that uses the two frequency-divided outputs to provide a time difference between the start of clock oscillation and its output timing can be modified in various ways. Further, the operation stop signal HLT may be an internally formed signal and/or a signal supplied from an external terminal.

[Application field]

INDUSTRIAL APPLICATION This invention is widely applicable to a microcomputer or a semiconductor integrated circuit device having a microcomputer function, which includes a timer circuit and a clock oscillation circuit constituted by an external resonator, and in which a clock signal can be selectively stopped.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 2 is a waveform diagram showing an example of the operation.

Claims (1)

[Claims] 1. The oscillation frequency is determined by an oscillation circuit for a timer, a frequency dividing circuit that receives the oscillation output and forms a time pulse for a clock circuit, and an external vibrator. a clock oscillation circuit that forms a clock signal for the circuit; a control circuit that stops the operation of the clock oscillation circuit using an internal circuit operation stop control signal in synchronization with the first frequency division stage output of the frequency division circuit; A semiconductor integrated circuit comprising: a gate circuit that controls the output timing of the clock oscillation circuit based on the time difference between the output of the first frequency division stage and the output of a second frequency division stage subsequent to the first frequency division stage. circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a one-chip microcomputer function.